- Import project
- Clean up
This commit is contained in:
10
.gitignore
vendored
Executable file
10
.gitignore
vendored
Executable file
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*.bld
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*.ngc
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*.xrpt
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*.prj
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*.srp
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*~
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netlist.lst
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toplevel.lso
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xst/
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_xmsgs/
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14
2d_display_engine.xst
Executable file
14
2d_display_engine.xst
Executable file
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run
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-ifn 2d_display_engine.prj
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-ifmt mixed
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-top toplevel
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-ofn 2d_display_engine.ngc
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-ofmt NGC
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-p xc3s700an-fgg484-4
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-opt_mode Speed
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-opt_level 1
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-fsm_encoding auto
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-sd coregen/
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-rtlview no
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-iob auto
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-keep_hierarchy soft
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122
Makefile
Executable file
122
Makefile
Executable file
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COMMON_INFILES=ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd \
|
||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
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||||
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
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src/toplevel.vhd src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
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src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc.vhd src/wb_ddr_ctrl_wb_sc.vhd \
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SYN_INFILES=
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PSMFILES=
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CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr
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PRJNAME=2d_display_engine
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NGCFILE=$(PRJNAME).ngc
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XSTFILE=$(PRJNAME).xst
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UCF=constr/$(PRJNAME).ucf constr/vhdl_bl4.ucf
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PCFFILE=$(PRJNAME).pcf
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NGDFILE=$(PRJNAME).ngd
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NCDFILE=$(PRJNAME).ncd
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NCDFILE_R=$(PRJNAME)_routed.ncd
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BITFILE=$(PRJNAME).bit
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TWRFILE=$(PRJNAME).twr
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PRJFILE=$(PRJNAME).prj
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PART=xc3s700an-fgg484-4
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NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
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MAPOPTS=-p $(PART) -cm area
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||||
PAROPTS=-rl high -pl high
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BITGENOPTS=
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TRACEOPTS=-v -u 100
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SIM_INFILES=
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SIM_INFILES_VLOG=ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
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GHDLOPTS=--workdir=ghdl -Pghdl --ieee=synopsys -fexplicit
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||||
VLOGCOMPOPTS=-d x512Mb -d sg5E -d x16
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SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
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SIMALLFILES=$(COMMON_INFILES) $(SIM_INFILES)
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SIMALLFILESXDB=$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
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$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
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CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
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||||
XILPATH=
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XST=$(XILPATH)xst
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||||
NGDBUILD=$(XILPATH)ngdbuild
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MAP=$(XILPATH)map
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PAR=$(XILPATH)par
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BITGEN=$(XILPATH)bitgen
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TRCE=$(XILPATH)trce
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VHPCOMP=$(XILPATH)vhpcomp
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VLOGCOMP=$(XILPATH)vlogcomp
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FUSE=$(XILPATH)fuse
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all: $(BITFILE)
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%.vhd: %.psm
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../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
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$(PRJFILE): Makefile
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rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done
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|
||||
$(NGCFILE): $(SYNALLFILES) $(PRJFILE) $(XSTFILE)
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||||
$(XST) -ifn $(XSTFILE)
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||||
|
||||
$(NGDFILE): $(NGCFILE) $(UCF)
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||||
$(NGDBUILD) $(NGDOPTS) $(NGCFILE) $(NGDFILE)
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||||
|
||||
$(PCFFILE) $(NCDFILE) : $(NGDFILE)
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||||
$(MAP) $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
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||||
|
||||
$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
|
||||
$(PAR) -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
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||||
|
||||
$(BITFILE): $(NCDFILE_R) $(PCFFILE)
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||||
$(BITGEN) -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
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||||
|
||||
$(TWRFILE): $(NCDFILE_R) $(PCFFILE)
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||||
$(TRCE) $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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||||
|
||||
isim/work/%.vdb: src/%.vhd
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||||
$(VHPCOMP) $<
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||||
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||||
isim/work/%.vdb: ddr2_sdram/vhdl_bl4/example_design/rtl/%.vhd
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$(VHPCOMP) $<
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||||
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isim/work/%.sdb: ddr2_sdram/vhdl_bl4/example_design/sim/%.v
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$(VLOGCOMP) $< $(VLOGCOMPOPTS)
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||||
isim/work/%.vdb: tb/%.vhd
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$(VHPCOMP) $<
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||||
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isim/work/%.vdb: coregen/%.vhd
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$(VHPCOMP) $<
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||||
|
||||
wb_ddr_ctrl_tb.exe: isim/work/wb_ddr_ctrl_tb.vdb $(SIMALLFILESXDB) $(CORESVDB)
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$(FUSE) work.wb_ddr_ctrl_tb -o $@
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clean:
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rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB)
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||||
.PSEUDO=all clean
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33
constr/2d_display_engine.ucf
Executable file
33
constr/2d_display_engine.ucf
Executable file
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# Timing constraints
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NET "CLKIN_50MHZ" PERIOD = 20.0ns HIGH 40%;
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NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%;
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# Location and I/O defs
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# Clocks
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NET "CLKIN_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
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NET "CLKIN_133MHZ" LOC = "V12"| IOSTANDARD = LVCMOS33 ;
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# VGA output
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NET "VGA_R<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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||||
NET "VGA_B<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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||||
NET "VGA_B<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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||||
NET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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# SPI flash
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NET "DATAFLASH_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
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NET "DATAFLASH_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "DATAFLASH_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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||||
NET "DATAFLASH_SS" LOC = "Y4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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||||
# write-protect and reset controls for Atmel AT45DB161D PROM
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NET "DATAFLASH_WP" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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||||
NET "DATAFLASH_RST" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
630
constr/vhdl_bl4.ucf
Executable file
630
constr/vhdl_bl4.ucf
Executable file
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#################################################################################################################
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##
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## Xilinx, Inc. 2008 www.xilinx.com
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## Fri January 4 11:51: 2008
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##
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||||
##
|
||||
##################################################################################################################
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||||
## File name : vhdl_bl4.ucf
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##
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||||
## Description : Constraints file
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||||
## targetted to FPGA: xc3s700afg484
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||||
## Speed Grade: -4
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||||
## FPGA family: spartan3a
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||||
## Design Entry: vhdl
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||||
## Frequency: 133 MHz
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||||
## Data width: 16
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||||
## Memory: DDR2_SDRAM/Components/MT47H32M16XX-5E
|
||||
## Supported Part Numbers: MT47H32M16BN-5E;MT47H32M16CC-5E;MT47H32M16FN-5E;MT47H32M16GC-5E
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||||
## Design: with Test bench
|
||||
## DCM Used: Enabled
|
||||
## Data Mask: Enabled
|
||||
##
|
||||
####################################################################################################################
|
||||
|
||||
#####################################################################################################################
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||||
## Clock constraints
|
||||
#####################################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/sys_clk_ibuf" TNM_NET = "SYS_CLK";
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5187 ns HIGH 50 %;
|
||||
|
||||
#######################################################################################################################
|
||||
## Calibration Circuit Constraints
|
||||
#######################################################################################################################
|
||||
## Placement constraints for LUTS in tap delay ckt
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||||
#######################################################################################################################
|
||||
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;
|
||||
|
||||
#######################################################################################################################
|
||||
# Placement constraints for first stage flops in tap delay ckt #
|
||||
#######################################################################################################################
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;
|
||||
|
||||
#######################################################################################################################
|
||||
## BEL constraints for LUTS in tap delay ckt
|
||||
#######################################################################################################################
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l0" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l1" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l2" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l3" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l4" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l5" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l6" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l7" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l8" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l9" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l10" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l11" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l12" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l13" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l14" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l15" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l16" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l17" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l18" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l19" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l20" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l21" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l22" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l23" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l24" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l25" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l26" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l27" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l28" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l29" BEL= F;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l30" BEL= G;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l31" BEL= F;
|
||||
|
||||
##############################################################################################################
|
||||
## Area Group Constraint For tap_dly and cal_ctl module.
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/l0" RLOC_ORIGIN=X28Y16;
|
||||
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
|
||||
INST "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
|
||||
AREA_GROUP "cal_ctl" RANGE = SLICE_X26Y8:SLICE_X37Y21;
|
||||
AREA_GROUP "cal_ctl" GROUP = CLOSED;
|
||||
################################################################################################################
|
||||
#**************************************************************************************************************#
|
||||
# CONTROLLER 0 #
|
||||
#**************************************************************************************************************#
|
||||
################################################################################################################
|
||||
# I/O STANDARDS
|
||||
################################################################################################################
|
||||
#NET "sys_clk_in" IOSTANDARD = LVCMOS33;
|
||||
NET "ddr2_a[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ba[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_cke" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_cs_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ras_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_cas_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_we_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_odt" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dm[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "rst_dqs_div_in" IOSTANDARD = SSTL18_I;
|
||||
NET "rst_dqs_div_out" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dq[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
|
||||
####################################################################################################################
|
||||
# Banks 2
|
||||
# Pin Location Constraints for System clock signals
|
||||
####################################################################################################################
|
||||
#NET "sys_clk_in" LOC = "V12"; # on board clock
|
||||
#NET "sys_clk_in" LOC = "U12"; #external clock
|
||||
|
||||
####################################################################################################################
|
||||
# Banks 3
|
||||
# Pin Location Constraints for Clock,Masks, Address, and Controls
|
||||
####################################################################################################################
|
||||
NET "ddr2_ck[0]" LOC = "M1" ;
|
||||
NET "ddr2_ck_n[0]" LOC = "M2" ;
|
||||
NET "ddr2_dm[0]" LOC = "J3" ;
|
||||
NET "ddr2_dm[1]" LOC = "E3" ;
|
||||
NET "ddr2_a[0]" LOC = "R2" ;
|
||||
NET "ddr2_a[1]" LOC = "T4" ;
|
||||
NET "ddr2_a[2]" LOC = "R1" ;
|
||||
NET "ddr2_a[3]" LOC = "U3" ;
|
||||
NET "ddr2_a[4]" LOC = "U2" ;
|
||||
NET "ddr2_a[5]" LOC = "U4" ;
|
||||
NET "ddr2_a[6]" LOC = "U1" ;
|
||||
NET "ddr2_a[7]" LOC = "Y1" ;
|
||||
NET "ddr2_a[8]" LOC = "W1" ;
|
||||
NET "ddr2_a[9]" LOC = "W2" ;
|
||||
NET "ddr2_a[10]" LOC = "T3" ;
|
||||
NET "ddr2_a[11]" LOC = "V1" ;
|
||||
NET "ddr2_a[12]" LOC = "Y2" ;
|
||||
NET "ddr2_ba[0]" LOC = "P3" ;
|
||||
NET "ddr2_ba[1]" LOC = "R3" ;
|
||||
NET "ddr2_cke" LOC = "N3" ;
|
||||
NET "ddr2_cs_n" LOC = "M5" ;
|
||||
NET "ddr2_ras_n" LOC = "M3" ;
|
||||
NET "ddr2_cas_n" LOC = "M4" ;
|
||||
NET "ddr2_we_n" LOC = "N4" ;
|
||||
NET "ddr2_odt" LOC = "P1" ;
|
||||
|
||||
#NET "reset_in_n" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ;
|
||||
#NET "cntrl0_led_error_output1" LOC = "R20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO | PULLDOWN ;
|
||||
#NET "cntrl0_data_valid_out" LOC = "T19" | IOSTANDARD = LVTTL;
|
||||
#NET "cntrl0_init_done" LOC = "V16" | IOSTANDARD = LVTTL;
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## MAXDELAY constraints
|
||||
##############################################################################################################
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
|
||||
## accurate calibration of tap delays. The following constraints are independent of frequency.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[7]" MAXDELAY = 400ps;
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 400ps;
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 400ps;
|
||||
|
||||
##############################################################################################################
|
||||
## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the
|
||||
## wire delays between the LUTs.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*" MAXDELAY = 190ps;
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*" MAXDELAY = 200 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint from the dqs PAD to input of LUT delay element.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/dqs_int_delay_in*" MAXDELAY = 580 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint from rst_dqs_div_in PAD to input of LUT delay element.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/dqs_div_rst" MAXDELAY = 460 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.
|
||||
## These constraints are required since these paths are not covered by timing analysis. The requirement is total
|
||||
## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 3007 ps;
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/fifo*_wr_en*" MAXDELAY = 3007 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## The MAXDELAY value on fifo write address should be less than clock period. This constraint is
|
||||
## required since this path is not covered by timing analysis.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/fifo*_wr_addr[*]" MAXDELAY = 6390 ps;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[1]" LOC = K5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit1" LOC = SLICE_X0Y58;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit1" LOC = SLICE_X0Y59;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[0]" LOC = H1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit0" LOC = SLICE_X2Y62;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit0" LOC = SLICE_X2Y63;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 3, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[3]" LOC = L3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit3" LOC = SLICE_X2Y52;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit3" LOC = SLICE_X2Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 2, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[2]" LOC = K1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit2" LOC = SLICE_X0Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit2" LOC = SLICE_X0Y51;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dqs[0]" LOC = K3;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs_n, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
#############################################################
|
||||
NET "ddr2_dqs_n[0]" LOC = K2;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col0
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X2Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X2Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X2Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X2Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X3Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col1
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X0Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X0Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X0Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X0Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X1Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X1Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for Fifo write address and write enable
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X1Y53;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X3Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 5, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[5]" LOC = L1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit5" LOC = SLICE_X2Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit5" LOC = SLICE_X2Y51;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 4, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[4]" LOC = L5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit4" LOC = SLICE_X0Y52;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit4" LOC = SLICE_X0Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 7, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[7]" LOC = H2;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit7" LOC = SLICE_X0Y62;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit7" LOC = SLICE_X0Y63;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 6, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[6]" LOC = K4;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit6" LOC = SLICE_X2Y58;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit6" LOC = SLICE_X2Y59;
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 9, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[9]" LOC = G4;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit1" LOC = SLICE_X2Y78;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit1" LOC = SLICE_X2Y79;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 8, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[8]" LOC = F2;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit0" LOC = SLICE_X0Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit0" LOC = SLICE_X0Y71;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 11, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[11]" LOC = H6;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit3" LOC = SLICE_X2Y76;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit3" LOC = SLICE_X2Y77;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 10, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[10]" LOC = G1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit2" LOC = SLICE_X2Y68;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit2" LOC = SLICE_X2Y69;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dqs[1]" LOC = K6;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs_n, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
#############################################################
|
||||
NET "ddr2_dqs_n[1]" LOC = J5;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col0
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X2Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X2Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X2Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X2Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X3Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X3Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col1
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X0Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X0Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X0Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X0Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X1Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X1Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for Fifo write address and write enable
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC = SLICE_X1Y72;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC = SLICE_X3Y72;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 13, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[13]" LOC = F1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit5" LOC = SLICE_X2Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit5" LOC = SLICE_X2Y71;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 12, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[12]" LOC = H5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit4" LOC = SLICE_X0Y76;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit4" LOC = SLICE_X0Y77;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 15, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[15]" LOC = F3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit7" LOC = SLICE_X0Y78;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit7" LOC = SLICE_X0Y79;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 14, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[14]" LOC = G3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit6" LOC = SLICE_X0Y68;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit6" LOC = SLICE_X0Y69;
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1
|
||||
##############################################################################################################
|
||||
NET "rst_dqs_div_in" LOC = H4;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for delayed rst_dqs_div signal
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "rst_dqs_div_out" LOC = H3;
|
||||
#################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/controller0/rst_dqs_div_r" LOC = SLICE_X4Y66;
|
||||
1864
coregen/coregen.cgc
Executable file
1864
coregen/coregen.cgc
Executable file
File diff suppressed because it is too large
Load Diff
22
coregen/coregen.cgp
Executable file
22
coregen/coregen.cgp
Executable file
@@ -0,0 +1,22 @@
|
||||
# Date: Tue Feb 26 21:37:12 2013
|
||||
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
SET workingdirectory = .\tmp\
|
||||
|
||||
# CRC: 5076f9de
|
||||
213
coregen/wb_ddr_ctrl_wb_from_ddr.xco
Executable file
213
coregen/wb_ddr_ctrl_wb_from_ddr.xco
Executable file
@@ -0,0 +1,213 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Tue Feb 26 21:32:50 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Common_Clock
|
||||
CSET component_name=wb_ddr_ctrl_wb_from_ddr
|
||||
CSET data_count=false
|
||||
CSET data_count_width=4
|
||||
CSET disable_timing_violations=true
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_assert_value_axis=1022
|
||||
CSET empty_threshold_assert_value_rach=1022
|
||||
CSET empty_threshold_assert_value_rdch=1022
|
||||
CSET empty_threshold_assert_value_wach=1022
|
||||
CSET empty_threshold_assert_value_wdch=1022
|
||||
CSET empty_threshold_assert_value_wrch=1022
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=false
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=false
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=false
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=false
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
|
||||
CSET fifo_implementation_axis=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=13
|
||||
CSET full_threshold_assert_value_axis=1023
|
||||
CSET full_threshold_assert_value_rach=1023
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=1023
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=1023
|
||||
CSET full_threshold_negate_value=12
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=16
|
||||
CSET input_depth_axis=1024
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=Native
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=16
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=4
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=4
|
||||
CSET tstrb_width=4
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=4
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T12:39:56Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: cda6b7a3
|
||||
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd
Executable file
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd
Executable file
@@ -0,0 +1,255 @@
|
||||
--*****************************************************************************
|
||||
-- (c) Copyright 2005 - 2009 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cal_ctl.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates the select lines for the LUT delay
|
||||
-- circuit that generate the required delay for the DQS with
|
||||
-- respect to the DQ. It calculates the dealy of a LUT dynalically
|
||||
-- by finding the number of LUTs in a clock phase.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_cal_ctl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
flop2 : in std_logic_vector(31 downto 0);
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end vhdl_bl4_cal_ctl;
|
||||
|
||||
architecture arc_cal_ctl of vhdl_bl4_cal_ctl is
|
||||
|
||||
signal cnt : std_logic_vector(5 downto 0);
|
||||
signal cnt1 : std_logic_vector(5 downto 0);
|
||||
signal trans_onedtct : std_logic;
|
||||
signal trans_twodtct : std_logic;
|
||||
signal phase_cnt : std_logic_vector(4 downto 0);
|
||||
signal tap_dly_reg : std_logic_vector(31 downto 0);
|
||||
signal enb_trans_two_dtct : std_logic;
|
||||
signal tapfordqs_val : std_logic_vector(4 downto 0);
|
||||
signal cnt_val : integer;
|
||||
signal reset_r : std_logic;
|
||||
|
||||
constant tap1 : std_logic_vector(4 downto 0) := "01111";
|
||||
constant tap2 : std_logic_vector(4 downto 0) := "10111";
|
||||
constant tap3 : std_logic_vector(4 downto 0) := "11011";
|
||||
constant tap4 : std_logic_vector(4 downto 0) := "11101";
|
||||
constant tap5 : std_logic_vector(4 downto 0) := "11110";
|
||||
constant tap6 : std_logic_vector(4 downto 0) := "11111";
|
||||
constant default_tap : std_logic_vector(4 downto 0) := "11101";
|
||||
|
||||
attribute syn_keep : boolean;
|
||||
attribute syn_keep of cnt : signal is true;
|
||||
attribute syn_keep of cnt1 : signal is true;
|
||||
attribute syn_keep of trans_onedtct : signal is true;
|
||||
attribute syn_keep of trans_twodtct : signal is true;
|
||||
attribute syn_keep of tap_dly_reg : signal is true;
|
||||
attribute syn_keep of enb_trans_two_dtct : signal is true;
|
||||
attribute syn_keep of phase_cnt : signal is true;
|
||||
attribute syn_keep of tapfordqs_val : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
dbg_phase_cnt <= phase_cnt;
|
||||
dbg_cnt <= cnt1;
|
||||
dbg_trans_onedtct <= trans_onedtct;
|
||||
dbg_trans_twodtct <= trans_twodtct;
|
||||
dbg_enb_trans_two_dtct <= enb_trans_two_dtct;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
tapfordqs <= tapfordqs_val;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------For Successive Transition-------------------
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if (clk'event and clk = '1') then
|
||||
if(reset_r = '1') then
|
||||
enb_trans_two_dtct <= '0';
|
||||
elsif(phase_cnt >= "00001") then
|
||||
enb_trans_two_dtct <= '1';
|
||||
else
|
||||
enb_trans_two_dtct <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1') then
|
||||
tap_dly_reg <= "00000000000000000000000000000000";
|
||||
elsif(cnt(5) = '1') then
|
||||
tap_dly_reg <= flop2;
|
||||
else
|
||||
tap_dly_reg <= tap_dly_reg;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------Free Running Counter For Counting 32 States ----------------------
|
||||
------- Two parallel counters are used to fix the timing ------------------
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1' or cnt(5) = '1') then
|
||||
cnt(5 downto 0) <= "000000";
|
||||
else
|
||||
cnt(5 downto 0) <= cnt(5 downto 0) + "000001";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1' or cnt1(5) = '1') then
|
||||
cnt1(5 downto 0) <= "000000";
|
||||
else
|
||||
cnt1(5 downto 0) <= cnt1(5 downto 0) + "000001";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if(reset_r = '1' or cnt(5) = '1') then
|
||||
phase_cnt <= "00000";
|
||||
elsif (trans_onedtct = '1' and trans_twodtct = '0') then
|
||||
phase_cnt <= phase_cnt + "00001";
|
||||
else
|
||||
phase_cnt <= phase_cnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------- Checking For The First Transition ------------------
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if (reset_r = '1' or cnt(5) = '1') then
|
||||
trans_onedtct <= '0';
|
||||
trans_twodtct <= '0';
|
||||
elsif (cnt(4 downto 0) = "00000" and tap_dly_reg(0) = '1') then
|
||||
trans_onedtct <= '1';
|
||||
trans_twodtct <= '0';
|
||||
elsif (tap_dly_reg(cnt_val) = '1' and trans_twodtct = '0') then
|
||||
if(trans_onedtct = '1' and enb_trans_two_dtct = '1') then
|
||||
trans_twodtct <= '1';
|
||||
else
|
||||
trans_onedtct <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_val <= conv_integer(cnt(4 downto 0));
|
||||
|
||||
-- Tap values for Left/Right banks
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if(reset_r = '1') then
|
||||
tapfordqs_val <= default_tap;
|
||||
elsif(cnt1(4) = '1' and cnt1(3) = '1' and cnt1(2) = '1' and cnt1(1) = '1'
|
||||
and cnt1(0) = '1') then
|
||||
if ((trans_onedtct = '0') or (trans_twodtct = '0')
|
||||
or (phase_cnt > "01100")) then
|
||||
tapfordqs_val <= tap6;
|
||||
elsif (phase_cnt > "01001") then
|
||||
tapfordqs_val <= tap4;
|
||||
elsif (phase_cnt > "00111") then
|
||||
tapfordqs_val <= tap3;
|
||||
elsif (phase_cnt > "00100") then
|
||||
tapfordqs_val <= tap2;
|
||||
else
|
||||
tapfordqs_val <= tap1;
|
||||
end if;
|
||||
else
|
||||
tapfordqs_val <= tapfordqs_val;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc_cal_ctl;
|
||||
134
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd
Executable file
134
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd
Executable file
@@ -0,0 +1,134 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cal_to.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations cal_ctl and tap_dly.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_cal_top is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk0dcmlock : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end vhdl_bl4_cal_top;
|
||||
|
||||
architecture arc of vhdl_bl4_cal_top is
|
||||
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
|
||||
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_3_ddr2_sp3, Coregen 11.4";
|
||||
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_3,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000}";
|
||||
|
||||
component vhdl_bl4_cal_ctl
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
flop2 : in std_logic_vector(31 downto 0);
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_tap_dly
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapin : in std_logic;
|
||||
flop2 : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal fpga_rst : std_logic;
|
||||
signal flop2_val : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
fpga_rst <= (not reset) or (not clk0dcmlock);
|
||||
|
||||
cal_ctl0 : vhdl_bl4_cal_ctl
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => fpga_rst,
|
||||
flop2 => flop2_val,
|
||||
tapfordqs => tapfordqs,
|
||||
dbg_phase_cnt => dbg_phase_cnt,
|
||||
dbg_cnt => dbg_cnt,
|
||||
dbg_trans_onedtct => dbg_trans_onedtct,
|
||||
dbg_trans_twodtct => dbg_trans_twodtct,
|
||||
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
|
||||
);
|
||||
|
||||
tap_dly0 : vhdl_bl4_tap_dly
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => fpga_rst,
|
||||
tapin => clk,
|
||||
flop2 => flop2_val
|
||||
);
|
||||
|
||||
end arc;
|
||||
127
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd
Executable file
127
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd
Executable file
@@ -0,0 +1,127 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_clk_dcm.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates the system clock for controller block
|
||||
-- This also generates the recapture clock, clock for the
|
||||
-- Refresh counter and also for the data path
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
entity vhdl_bl4_clk_dcm is
|
||||
port(
|
||||
input_clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
clk : out std_logic;
|
||||
clk90 : out std_logic;
|
||||
dcm_lock : out std_logic
|
||||
);
|
||||
end vhdl_bl4_clk_dcm;
|
||||
|
||||
architecture arc of vhdl_bl4_clk_dcm is
|
||||
|
||||
signal clk0dcm : std_logic;
|
||||
signal clk90dcm : std_logic;
|
||||
signal clk0_buf : std_logic;
|
||||
signal clk90_buf : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal dcm1_lock : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
clk <= clk0_buf;
|
||||
clk90 <= clk90_buf;
|
||||
|
||||
DCM_INST1 : DCM
|
||||
generic map(
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => true
|
||||
)
|
||||
port map (
|
||||
CLKIN => input_clk,
|
||||
CLKFB => clk0_buf,
|
||||
DSSEN => gnd,
|
||||
PSINCDEC => gnd,
|
||||
PSEN => gnd,
|
||||
PSCLK => gnd,
|
||||
RST => rst,
|
||||
CLK0 => clk0dcm,
|
||||
CLK90 => clk90dcm,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLKDV => open,
|
||||
CLKFX => open,
|
||||
CLKFX180 => open,
|
||||
LOCKED => dcm1_lock,
|
||||
PSDONE => open,
|
||||
STATUS => open
|
||||
);
|
||||
|
||||
BUFG_CLK0 : BUFG
|
||||
port map (
|
||||
O => clk0_buf,
|
||||
I => clk0dcm
|
||||
);
|
||||
|
||||
BUFG_CLK90 : BUFG
|
||||
port map (
|
||||
O => clk90_buf,
|
||||
I => clk90dcm
|
||||
);
|
||||
|
||||
dcm_lock <= dcm1_lock;
|
||||
|
||||
end arc;
|
||||
1382
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd
Executable file
1382
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd
Executable file
File diff suppressed because it is too large
Load Diff
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd
Executable file
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd
Executable file
@@ -0,0 +1,255 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_controller_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the IOB instantiations to address and control
|
||||
-- signals.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_controller_iobs_0 is
|
||||
port(
|
||||
clk0 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
rst_dqs_div_int : in std_logic;
|
||||
ddr_odt : out std_logic;
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic
|
||||
);
|
||||
end vhdl_bl4_controller_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_controller_iobs_0 is
|
||||
|
||||
signal ddr_web_q : std_logic;
|
||||
signal ddr_rasb_q : std_logic;
|
||||
signal ddr_casb_q : std_logic;
|
||||
signal ddr_cke_q : std_logic;
|
||||
signal ddr_cke_int : std_logic;
|
||||
signal ddr_address_reg : std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
signal ddr_ba_reg : std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
signal ddr_odt_reg : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
attribute iob : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute iob of iob_rasb : label is "FORCE";
|
||||
attribute iob of iob_casb : label is "FORCE";
|
||||
attribute iob of iob_web : label is "FORCE";
|
||||
attribute iob of iob_cke : label is "FORCE";
|
||||
attribute iob of iob_odt : label is "FORCE";
|
||||
attribute syn_useioff of iob_rasb : label is true;
|
||||
attribute syn_useioff of iob_casb : label is true;
|
||||
attribute syn_useioff of iob_web : label is true;
|
||||
attribute syn_useioff of iob_cke : label is true;
|
||||
attribute syn_useioff of iob_odt : label is true;
|
||||
|
||||
begin
|
||||
|
||||
clk180 <= not clk0;
|
||||
|
||||
---- ******************************************* ----
|
||||
---- Includes the instantiation of FD for cntrl ----
|
||||
---- signals ----
|
||||
---- ******************************************* ----
|
||||
|
||||
iob_web : FD
|
||||
port map (
|
||||
Q => ddr_web_q,
|
||||
D => ddr_web_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
iob_rasb : FD
|
||||
port map (
|
||||
Q => ddr_rasb_q,
|
||||
D => ddr_rasb_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
iob_casb : FD
|
||||
port map (
|
||||
Q => ddr_casb_q,
|
||||
D => ddr_casb_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
---- ************************************* ----
|
||||
---- Output buffers for control signals ----
|
||||
---- ************************************* ----
|
||||
|
||||
r16 : OBUF
|
||||
port map (
|
||||
I => ddr_web_q,
|
||||
O => ddr_web
|
||||
);
|
||||
|
||||
r17 : OBUF
|
||||
port map (
|
||||
I => ddr_rasb_q,
|
||||
O => ddr_rasb
|
||||
);
|
||||
|
||||
r18 : OBUF
|
||||
port map (
|
||||
I => ddr_casb_q,
|
||||
O => ddr_casb
|
||||
);
|
||||
|
||||
r19 : OBUF
|
||||
port map (
|
||||
I => ddr_csb_cntrl,
|
||||
O => ddr_csb
|
||||
);
|
||||
|
||||
iob_cke1 : FD
|
||||
port map(
|
||||
Q => ddr_cke_int,
|
||||
D => ddr_cke_cntrl,
|
||||
C => clk0
|
||||
);
|
||||
|
||||
iob_cke : FD
|
||||
port map(
|
||||
Q => ddr_cke_q,
|
||||
D => ddr_cke_int,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
r20 : OBUF
|
||||
port map (
|
||||
I => ddr_cke_q,
|
||||
O => ddr_cke
|
||||
);
|
||||
|
||||
iob_odt : FD
|
||||
port map (
|
||||
Q => ddr_ODT_reg,
|
||||
D => ddr_ODT_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
ODT_iob_obuf : OBUF
|
||||
port map (
|
||||
I => ddr_ODT_reg,
|
||||
O => ddr_ODT
|
||||
);
|
||||
|
||||
---- ******************************************* ----
|
||||
---- Includes the instantiation of FD and OBUF ----
|
||||
---- for row address and bank address ----
|
||||
---- ******************************************* ----
|
||||
|
||||
gen_addr : for i in (ROW_ADDRESS -1) downto 0 generate
|
||||
attribute IOB of iob_addr : label is "FORCE";
|
||||
attribute syn_useioff of iob_addr : label is true;
|
||||
begin
|
||||
iob_addr : FD
|
||||
port map (
|
||||
Q => ddr_address_reg(i),
|
||||
D => ddr_address_cntrl(i),
|
||||
C => clk180
|
||||
);
|
||||
r : OBUF
|
||||
port map (
|
||||
I => ddr_address_reg(i),
|
||||
O => ddr_address(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
gen_ba : for i in (BANK_ADDRESS -1) downto 0 generate
|
||||
attribute IOB of iob_ba : label is "FORCE";
|
||||
attribute syn_useioff of iob_ba : label is true;
|
||||
begin
|
||||
iob_ba : FD
|
||||
port map (
|
||||
Q => ddr_ba_reg(i),
|
||||
D => ddr_ba_cntrl(i),
|
||||
C => clk180
|
||||
);
|
||||
r : OBUF
|
||||
port map (
|
||||
I => ddr_ba_reg(i),
|
||||
O => ddr_ba(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
rst_iob_inbuf : IBUF
|
||||
port map(
|
||||
I => rst_dqs_div_in,
|
||||
O => rst_dqs_div
|
||||
);
|
||||
|
||||
rst_iob_outbuf : OBUF
|
||||
port map (
|
||||
I => rst_dqs_div_int,
|
||||
O => rst_dqs_div_out
|
||||
);
|
||||
|
||||
end arc;
|
||||
210
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd
Executable file
210
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd
Executable file
@@ -0,0 +1,210 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_path_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the write and read data paths for the
|
||||
-- DDR2 memory interface. The write data along with write enable
|
||||
-- signals are forwarded to the DDR IOB FFs. The read data is
|
||||
-- captured in CLB FFs and finally input to FIFOs.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_path_0 is
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
reset : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic; -- Added new signal
|
||||
-- debug signals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end vhdl_bl4_data_path_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_path_0 is
|
||||
|
||||
component vhdl_bl4_data_read_0
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
u_data_val : out std_logic
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_read_controller_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_write_0
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal read_valid_data_1 : std_logic;
|
||||
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col1 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
begin
|
||||
|
||||
data_read0 : vhdl_bl4_data_read_0
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
ddr_dq_in => dq,
|
||||
fifo_0_wr_en => fifo_0_wr_en,
|
||||
fifo_1_wr_en => fifo_1_wr_en,
|
||||
fifo_0_wr_addr => fifo_0_wr_addr,
|
||||
fifo_1_wr_addr => fifo_1_wr_addr,
|
||||
dqs_delayed_col0 => dqs_delayed_col0,
|
||||
dqs_delayed_col1 => dqs_delayed_col1,
|
||||
read_fifo_rden => read_fifo_rden,
|
||||
user_output_data => user_output_data,
|
||||
u_data_val => u_data_val
|
||||
);
|
||||
|
||||
data_read_controller0 : vhdl_bl4_data_read_controller_0
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
delay_sel => delay_sel,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
fifo_0_wr_en_val => fifo_0_wr_en,
|
||||
fifo_1_wr_en_val => fifo_1_wr_en,
|
||||
fifo_0_wr_addr_val => fifo_0_wr_addr,
|
||||
fifo_1_wr_addr_val => fifo_1_wr_addr,
|
||||
dqs_delayed_col0_val => dqs_delayed_col0,
|
||||
dqs_delayed_col1_val => dqs_delayed_col1,
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
data_write0 : vhdl_bl4_data_write_0
|
||||
port map (
|
||||
user_input_data => user_input_data,
|
||||
user_data_mask => user_data_mask,
|
||||
clk90 => clk90,
|
||||
write_enable => write_enable,
|
||||
write_en_val => write_en_val,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r
|
||||
);
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
173
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd
Executable file
173
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd
Executable file
@@ -0,0 +1,173 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_parameters_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations s3_dq_iob, s3_dqs_iob and
|
||||
-- s3_dm_iob modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_path_iobs_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_data_path_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_path_iobs_0 is
|
||||
|
||||
component vhdl_bl4_s3_dqs_iob
|
||||
port(
|
||||
clk : in std_logic;
|
||||
ddr_dqs_reset : in std_logic;
|
||||
ddr_dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic;
|
||||
ddr_dqs_n : inout std_logic;
|
||||
dqs : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_s3_dq_iob
|
||||
port (
|
||||
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
|
||||
write_data_falling : in std_logic; --Transmit data, output on falling edge
|
||||
write_data_rising : in std_logic; --Transmit data, output on rising edge
|
||||
read_data_in : out std_logic; -- Received data
|
||||
clk90 : in std_logic;
|
||||
write_en_val : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_s3_dm_iob
|
||||
port (
|
||||
ddr_dm : out std_logic;
|
||||
mask_falling : in std_logic;
|
||||
mask_rising : in std_logic;
|
||||
clk90 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal ddr_dq_in : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
|
||||
begin
|
||||
|
||||
ddr_dq_val <= ddr_dq_in;
|
||||
|
||||
--***********************************************************************
|
||||
-- DM IOB instantiations
|
||||
--***********************************************************************
|
||||
MASK_INST : if(MASK_ENABLE = 1) generate
|
||||
begin
|
||||
gen_dm: for dm_i in 0 to DATA_MASK_WIDTH-1 generate
|
||||
s3_dm_iob_inst : vhdl_bl4_s3_dm_iob
|
||||
port map (
|
||||
ddr_dm => ddr_dm(dm_i),
|
||||
mask_falling => data_mask_f(dm_i),
|
||||
mask_rising => data_mask_r(dm_i),
|
||||
clk90 => clk90
|
||||
);
|
||||
end generate;
|
||||
end generate MASK_INST;
|
||||
|
||||
--***********************************************************************
|
||||
-- Read Data Capture Module Instantiations
|
||||
--***********************************************************************
|
||||
-- DQS IOB instantiations
|
||||
--***********************************************************************
|
||||
|
||||
gen_dqs: for dqs_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
s3_dqs_iob_inst : vhdl_bl4_s3_dqs_iob
|
||||
port map (
|
||||
clk => clk,
|
||||
ddr_dqs_reset => dqs_reset,
|
||||
ddr_dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr_dqs(dqs_i),
|
||||
ddr_dqs_n => ddr_dqs_n(dqs_i),
|
||||
dqs => dqs_int_delay_in(dqs_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
--******************************************************************************
|
||||
-- DDR Data bit instantiations
|
||||
--******************************************************************************
|
||||
|
||||
gen_dq: for dq_i in 0 to DATA_WIDTH-1 generate
|
||||
s3_dq_iob_inst : vhdl_bl4_s3_dq_iob
|
||||
port map (
|
||||
ddr_dq_inout => ddr_dq(dq_i),
|
||||
write_data_falling => write_data_falling(dq_i),
|
||||
write_data_rising => write_data_rising(dq_i),
|
||||
read_data_in => ddr_dq_in(dq_i),
|
||||
clk90 => clk90,
|
||||
write_en_val => write_en_val
|
||||
);
|
||||
end generate;
|
||||
|
||||
end arc;
|
||||
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd
Executable file
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd
Executable file
@@ -0,0 +1,274 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_read_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : ram8d modules are instantiated for Read data FIFOs. ram8d is
|
||||
-- each 8 bits or 4 bits depending on number data bits per strobe.
|
||||
-- Each strobe will have two instances, one for rising edge data
|
||||
-- and one for falling edge data.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_read_0 is
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic;
|
||||
user_output_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic
|
||||
);
|
||||
end vhdl_bl4_data_read_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_read_0 is
|
||||
|
||||
component vhdl_bl4_rd_gray_cntr
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
rgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_ram8d_0 is
|
||||
port (
|
||||
DOUT : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
WADDR : in std_logic_vector(3 downto 0);
|
||||
DIN : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
RADDR : in std_logic_vector(3 downto 0);
|
||||
WCLK0 : in std_logic;
|
||||
WCLK1 : in std_logic;
|
||||
WE : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_ram8d_1 is
|
||||
port (
|
||||
DOUT : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
WADDR : in std_logic_vector(3 downto 0);
|
||||
DIN : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
RADDR : in std_logic_vector(3 downto 0);
|
||||
WCLK0 : in std_logic;
|
||||
WCLK1 : in std_logic;
|
||||
WE : in std_logic
|
||||
);
|
||||
end component;
|
||||
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
|
||||
|
||||
signal first_sdr_data : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal reset90_r : std_logic;
|
||||
signal fifo0_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo1_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_0_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_1_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_0_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_1_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
|
||||
signal read_fifo_rden_90r1 : std_logic;
|
||||
signal read_fifo_rden_90r2 : std_logic;
|
||||
signal read_fifo_rden_90r3 : std_logic;
|
||||
signal read_fifo_rden_90r4 : std_logic;
|
||||
signal read_fifo_rden_90r5 : std_logic;
|
||||
signal read_fifo_rden_90r6 : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of fifo0_rd_addr_r : signal is true;
|
||||
attribute syn_preserve of fifo1_rd_addr_r : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if(clk90'event and clk90='1') then
|
||||
reset90_r <= reset90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
|
||||
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
|
||||
end generate;
|
||||
|
||||
user_output_data <= first_sdr_data;
|
||||
u_data_val <= read_fifo_rden_90r6;
|
||||
|
||||
-- Read fifo read enable signal phase is changed from 180 to 90 clock domain
|
||||
|
||||
process (clk90)
|
||||
begin
|
||||
if (rising_edge(clk90)) then
|
||||
if reset90_r = '1' then
|
||||
read_fifo_rden_90r1 <= '0';
|
||||
read_fifo_rden_90r2 <= '0';
|
||||
read_fifo_rden_90r3 <= '0';
|
||||
read_fifo_rden_90r4 <= '0';
|
||||
read_fifo_rden_90r5 <= '0';
|
||||
read_fifo_rden_90r6<= '0';
|
||||
else
|
||||
read_fifo_rden_90r1 <= read_fifo_rden;
|
||||
read_fifo_rden_90r2 <= read_fifo_rden_90r1;
|
||||
read_fifo_rden_90r3 <= read_fifo_rden_90r2;
|
||||
read_fifo_rden_90r4 <= read_fifo_rden_90r3;
|
||||
read_fifo_rden_90r5 <= read_fifo_rden_90r4;
|
||||
read_fifo_rden_90r6 <= read_fifo_rden_90r5;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
fifo_0_data_out_r <= fifo_0_data_out;
|
||||
fifo_1_data_out_r <= fifo_1_data_out;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_addr : for addr_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
fifo0_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo0_rd_addr;
|
||||
fifo1_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo1_rd_addr;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if reset90_r = '1' then
|
||||
first_sdr_data <= (others => '0');
|
||||
elsif (read_fifo_rden_90r5 = '1') then
|
||||
first_sdr_data <= (fifo_0_data_out_r & fifo_1_data_out_r);
|
||||
else
|
||||
first_sdr_data <= first_sdr_data;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- fifo0_rd_addr and fifo1_rd_addr counters ( gray counters )
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
fifo0_rd_addr_inst : vhdl_bl4_rd_gray_cntr
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
cnt_en => read_fifo_rden_90r3,
|
||||
rgc_gcnt => fifo0_rd_addr
|
||||
);
|
||||
fifo1_rd_addr_inst : vhdl_bl4_rd_gray_cntr
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
cnt_en => read_fifo_rden_90r3,
|
||||
rgc_gcnt => fifo1_rd_addr
|
||||
);
|
||||
|
||||
strobe0 : vhdl_bl4_ram8d_0
|
||||
Port Map (
|
||||
DOUT => fifo_0_data_out(7 downto 0),
|
||||
WADDR => fifo_0_wr_addr(3 downto 0),
|
||||
DIN => ddr_dq_in(7 downto 0),
|
||||
RADDR => fifo0_rd_addr_r(3 downto 0),
|
||||
WCLK0 => dqs_delayed_col0(0),
|
||||
WCLK1 => dqs_delayed_col1(0),
|
||||
WE => fifo_0_wr_en(0)
|
||||
);
|
||||
strobe0_n : vhdl_bl4_ram8d_0
|
||||
Port Map (
|
||||
DOUT => fifo_1_data_out(7 downto 0),
|
||||
WADDR => fifo_1_wr_addr(3 downto 0),
|
||||
DIN => ddr_dq_in(7 downto 0),
|
||||
RADDR => fifo1_rd_addr_r(3 downto 0),
|
||||
WCLK0 => dqs_delayed_col0_n(0),
|
||||
WCLK1 => dqs_delayed_col1_n(0),
|
||||
WE => fifo_1_wr_en(0)
|
||||
);
|
||||
|
||||
strobe1 : vhdl_bl4_ram8d_1
|
||||
Port Map (
|
||||
DOUT => fifo_0_data_out(15 downto 8),
|
||||
WADDR => fifo_0_wr_addr(7 downto 4),
|
||||
DIN => ddr_dq_in(15 downto 8),
|
||||
RADDR => fifo0_rd_addr_r(7 downto 4),
|
||||
WCLK0 => dqs_delayed_col0(1),
|
||||
WCLK1 => dqs_delayed_col1(1),
|
||||
WE => fifo_0_wr_en(1)
|
||||
);
|
||||
strobe1_n : vhdl_bl4_ram8d_1
|
||||
Port Map (
|
||||
DOUT => fifo_1_data_out(15 downto 8),
|
||||
WADDR => fifo_1_wr_addr(7 downto 4),
|
||||
DIN => ddr_dq_in(15 downto 8),
|
||||
RADDR => fifo1_rd_addr_r(7 downto 4),
|
||||
WCLK0 => dqs_delayed_col0_n(1),
|
||||
WCLK1 => dqs_delayed_col1_n(1),
|
||||
WE => fifo_1_wr_en(1)
|
||||
);
|
||||
|
||||
|
||||
end arc;
|
||||
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd
Executable file
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd
Executable file
@@ -0,0 +1,274 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_read_controller_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Description : This module has instantiations fifo_0_wr_en, fifo_1_wr_en,
|
||||
-- dqs_delay and wr_gray_cntr.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_read_controller_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
-- debug signals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en: in std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_data_read_controller_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_read_controller_0 is
|
||||
|
||||
component vhdl_bl4_dqs_delay
|
||||
port (
|
||||
clk_in : in std_logic;
|
||||
sel_in : in std_logic_vector(4 downto 0);
|
||||
clk_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- wr_gray_cntr is a gray counter with an ASYNC reset for fifo wr_addr
|
||||
|
||||
component vhdl_bl4_wr_gray_cntr
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
wgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
-- fifo_wr_en module generates fifo write enable signal
|
||||
-- enable is derived from rst_dqs_div signal
|
||||
|
||||
component vhdl_bl4_fifo_0_wr_en_0
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
rst_dqs_delay_n : out std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_fifo_1_wr_en_0
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_dqs_delay_n : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal dqs_delayed_col0 : std_logic_vector((data_strobe_width-1) downto 0);
|
||||
signal dqs_delayed_col1 : std_logic_vector((data_strobe_width-1) downto 0);
|
||||
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
|
||||
-- FIFO WRITE ENABLE SIGNALS
|
||||
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
|
||||
signal rst_dqs_div : std_logic;
|
||||
signal reset_r : std_logic;
|
||||
signal rst_dqs_delay_0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal delay_sel_rst_dqs_div : std_logic_vector(4 downto 0);
|
||||
signal delay_sel_dqs : std_logic_vector(4 downto 0);
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
attribute buffer_type : string;
|
||||
attribute buffer_type of dqs_delayed_col0: signal is "none";
|
||||
attribute buffer_type of dqs_delayed_col1: signal is "none";
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
fifo_0_wr_addr_val <= fifo_0_wr_addr;
|
||||
fifo_1_wr_addr_val <= fifo_1_wr_addr;
|
||||
fifo_0_wr_en_val <= fifo_0_wr_en;
|
||||
fifo_1_wr_en_val <= fifo_1_wr_en;
|
||||
dqs_delayed_col0_val <= dqs_delayed_col0 ;
|
||||
dqs_delayed_col1_val <= dqs_delayed_col1 ;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
|
||||
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
|
||||
debug_rst_dqs_div_ena : if (DEBUG_EN = 1) generate
|
||||
delay_sel_rst_dqs_div <= vio_out_rst_dqs_div(4 downto 0) when (vio_out_rst_dqs_div_en = '1')
|
||||
else delay_sel;
|
||||
end generate;
|
||||
|
||||
debug_rst_dqs_div_dis : if (DEBUG_EN = 0) generate
|
||||
delay_sel_rst_dqs_div <= delay_sel;
|
||||
end generate;
|
||||
|
||||
|
||||
-- delayed rst_dqs_div logic
|
||||
|
||||
rst_dqs_div_delayed : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => rst_dqs_div_in,
|
||||
sel_in => delay_sel_rst_dqs_div,
|
||||
clk_out => rst_dqs_div
|
||||
);
|
||||
|
||||
|
||||
debug_ena : if (DEBUG_EN = 1) generate
|
||||
delay_sel_dqs <= vio_out_dqs(4 downto 0) when (vio_out_dqs_en = '1')
|
||||
else delay_sel;
|
||||
end generate;
|
||||
|
||||
debug_dis : if (DEBUG_EN = 0) generate
|
||||
delay_sel_dqs <= delay_sel;
|
||||
end generate;
|
||||
|
||||
|
||||
--******************************************************************************
|
||||
-- DQS Internal Delay Circuit implemented in LUTs
|
||||
--******************************************************************************
|
||||
gen_delay: for dly_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
attribute syn_preserve of dqs_delay_col0: label is true;
|
||||
attribute syn_preserve of dqs_delay_col1: label is true;
|
||||
begin
|
||||
-- Internal Clock Delay circuit placed in the first
|
||||
-- column (for falling edge data) adjacent to IOBs
|
||||
dqs_delay_col0 : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => dqs_int_delay_in(dly_i),
|
||||
sel_in => delay_sel_dqs,
|
||||
clk_out => dqs_delayed_col0(dly_i)
|
||||
);
|
||||
-- Internal Clock Delay circuit placed in the second
|
||||
--column (for rising edge data) adjacent to IOBs
|
||||
dqs_delay_col1 : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => dqs_int_delay_in(dly_i),
|
||||
sel_in => delay_sel_dqs,
|
||||
clk_out => dqs_delayed_col1(dly_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
gen_wr_en: for wr_en_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
fifo_0_wr_en_inst: vhdl_bl4_fifo_0_wr_en_0
|
||||
port map (
|
||||
clk => dqs_delayed_col1_n (wr_en_i),
|
||||
reset => reset_r,
|
||||
din => rst_dqs_div,
|
||||
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
|
||||
dout => fifo_0_wr_en(wr_en_i)
|
||||
);
|
||||
fifo_1_wr_en_inst: vhdl_bl4_fifo_1_wr_en_0
|
||||
port map (
|
||||
clk => dqs_delayed_col0(wr_en_i),
|
||||
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
|
||||
reset => reset_r,
|
||||
din => rst_dqs_div,
|
||||
dout => fifo_1_wr_en(wr_en_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- write pointer gray counter instances
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
gen_wr_addr: for wr_addr_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
fifo_0_wr_addr_inst : vhdl_bl4_wr_gray_cntr
|
||||
port map (
|
||||
clk => dqs_delayed_col1(wr_addr_i),
|
||||
reset => reset_r,
|
||||
cnt_en => fifo_0_wr_en(wr_addr_i),
|
||||
wgc_gcnt => fifo_0_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
|
||||
);
|
||||
fifo_1_wr_addr_inst : vhdl_bl4_wr_gray_cntr
|
||||
port map (
|
||||
clk => dqs_delayed_col0_n(wr_addr_i),
|
||||
reset => reset_r,
|
||||
cnt_en => fifo_1_wr_en(wr_addr_i),
|
||||
wgc_gcnt => fifo_1_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
|
||||
);
|
||||
end generate;
|
||||
|
||||
end arc;
|
||||
196
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd
Executable file
196
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd
Executable file
@@ -0,0 +1,196 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_write0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : Data write operation performed through the pipelines in this
|
||||
-- module.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_write_0 is
|
||||
port(
|
||||
user_input_data : in std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_data_write_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_write_0 is
|
||||
|
||||
|
||||
signal write_en_P1 : std_logic; -- write enable Pipeline stage
|
||||
signal write_data0 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data1 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data2 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data3 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data4 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data_m0 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m1 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m2 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m3 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m4 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data90 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data90_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data90_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data_m90 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m90_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m90_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data270 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data270_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data270_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data_m270 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m270_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m270_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
attribute syn_preserve of write_data0 : signal is true;
|
||||
attribute syn_preserve of write_data1 : signal is true;
|
||||
attribute syn_preserve of write_data2 : signal is true;
|
||||
attribute syn_preserve of write_data3 : signal is true;
|
||||
attribute syn_preserve of write_data4 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data_m0 : signal is true;
|
||||
attribute syn_preserve of write_data_m1 : signal is true;
|
||||
attribute syn_preserve of write_data_m2 : signal is true;
|
||||
attribute syn_preserve of write_data_m3 : signal is true;
|
||||
attribute syn_preserve of write_data_m4 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data90 : signal is true;
|
||||
attribute syn_preserve of write_data90_1 : signal is true;
|
||||
attribute syn_preserve of write_data90_2 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data270 : signal is true;
|
||||
attribute syn_preserve of write_data270_1 : signal is true;
|
||||
attribute syn_preserve of write_data270_2 : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
write_data0 <= user_input_data;
|
||||
write_data_m0 <= user_data_mask;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_data1 <= write_data0;
|
||||
write_data_m1 <= write_data_m0;
|
||||
write_data2 <= write_data1;
|
||||
write_data_m2 <= write_data_m1;
|
||||
write_data3 <= write_data2;
|
||||
write_data_m3 <= write_data_m2;
|
||||
write_data4 <= write_data3;
|
||||
write_data_m4 <= write_data_m3;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_data90 <= write_data4((DATA_WIDTH-1) downto 0);
|
||||
write_data_m90 <= write_data_m4((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data90_1 <= write_data90;
|
||||
write_data_m90_1 <= write_data_m90;
|
||||
write_data90_2 <= write_data90_1;
|
||||
write_data_m90_2 <= write_data_m90_1;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '0' then
|
||||
write_data270 <= write_data4((DATA_WIDTH*2-1) downto DATA_WIDTH);
|
||||
write_data_m270 <= write_data_m4((DATA_MASK_WIDTH*2-1) downto DATA_MASK_WIDTH);
|
||||
write_data270_1 <= write_data270;
|
||||
write_data270_2 <= write_data270_1;
|
||||
write_data_m270_1 <= write_data_m270;
|
||||
write_data_m270_2 <= write_data_m270_1;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
write_data_rising <= write_data270_2;
|
||||
write_data_falling <= write_data90_2;
|
||||
data_mask_r <= write_data_m270_2;
|
||||
data_mask_f <= write_data_m90_2;
|
||||
|
||||
-- write enable for data path
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_en_P1 <= write_enable;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- write enable for data path
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '0' then
|
||||
write_en_val <= write_en_P1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
144
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
Executable file
144
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
Executable file
@@ -0,0 +1,144 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_dqs_delay_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the delay in the dqs signal.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_dqs_delay is
|
||||
port (
|
||||
clk_in : in std_logic;
|
||||
sel_in : in std_logic_vector(4 downto 0);
|
||||
clk_out : out std_logic
|
||||
);
|
||||
end vhdl_bl4_dqs_delay;
|
||||
|
||||
architecture arc_dqs_delay of vhdl_bl4_dqs_delay is
|
||||
|
||||
signal delay1 : std_logic;
|
||||
signal delay2 : std_logic;
|
||||
signal delay3 : std_logic;
|
||||
signal delay4 : std_logic;
|
||||
signal delay5 : std_logic;
|
||||
signal high : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of one : label is true;
|
||||
attribute syn_preserve of two : label is true;
|
||||
attribute syn_preserve of three : label is true;
|
||||
attribute syn_preserve of four : label is true;
|
||||
attribute syn_preserve of five : label is true;
|
||||
attribute syn_preserve of six : label is true;
|
||||
|
||||
begin
|
||||
|
||||
high <= '1';
|
||||
|
||||
one : LUT4 generic map (INIT => x"f3c0")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => sel_in(4),
|
||||
I2 => delay5,
|
||||
I3 => clk_in,
|
||||
O => clk_out
|
||||
);
|
||||
|
||||
two : LUT4 generic map (INIT => x"ee22")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(2),
|
||||
I2 => high,
|
||||
I3 => delay3,
|
||||
O => delay4
|
||||
);
|
||||
|
||||
three : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(0),
|
||||
I2 => delay1,
|
||||
I3 => high,
|
||||
O => delay2
|
||||
);
|
||||
|
||||
four : LUT4 generic map (INIT => x"ff00")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => high,
|
||||
I2 => high,
|
||||
I3 => clk_in,
|
||||
O => delay1
|
||||
);
|
||||
|
||||
five : LUT4 generic map (INIT => x"f3c0")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => sel_in(3),
|
||||
I2 => delay4,
|
||||
I3 => clk_in,
|
||||
O => delay5
|
||||
);
|
||||
|
||||
six : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(1),
|
||||
I2 => delay2,
|
||||
I3 => high,
|
||||
O => delay3
|
||||
);
|
||||
|
||||
end arc_dqs_delay;
|
||||
92
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd
Executable file
92
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd
Executable file
@@ -0,0 +1,92 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_fifo_0_wr_en_0.v
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the write enable signal to the fifos,
|
||||
-- which are driven by negedge of data strobe
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_fifo_0_wr_en_0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
rst_dqs_delay_n : out std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_fifo_0_wr_en_0;
|
||||
|
||||
architecture arc of vhdl_bl4_fifo_0_wr_en_0 is
|
||||
|
||||
signal din_delay : std_ulogic;
|
||||
signal tie_high : std_ulogic;
|
||||
|
||||
begin
|
||||
|
||||
rst_dqs_delay_n <= not din_delay;
|
||||
dout <= din or din_delay;
|
||||
tie_high <= '1';
|
||||
|
||||
delay_ff : FDCE
|
||||
port map (
|
||||
Q => din_delay,
|
||||
C => clk,
|
||||
CE => tie_high,
|
||||
CLR => reset,
|
||||
D => din
|
||||
);
|
||||
|
||||
end arc;
|
||||
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd
Executable file
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_fifo_0_wr_en_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the write enable signal to the fifos,
|
||||
-- which are driven by posedge of data strobe
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_fifo_1_wr_en_0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_dqs_delay_n : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end vhdl_bl4_fifo_1_wr_en_0;
|
||||
|
||||
architecture arc of vhdl_bl4_fifo_1_wr_en_0 is
|
||||
|
||||
signal din_delay : std_ulogic;
|
||||
signal tie_high : std_ulogic;
|
||||
signal dout0 : std_ulogic;
|
||||
signal rst_dqs_delay : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
rst_dqs_delay <= not rst_dqs_delay_n;
|
||||
dout0 <= din and rst_dqs_delay_n;
|
||||
dout <= rst_dqs_delay or din_delay;
|
||||
tie_high <= '1';
|
||||
|
||||
delay_ff_1 : FDCE
|
||||
port map (
|
||||
Q => din_delay,
|
||||
C => clk,
|
||||
CE => tie_high,
|
||||
CLR => reset,
|
||||
D => dout0
|
||||
);
|
||||
|
||||
end arc;
|
||||
110
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd
Executable file
110
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd
Executable file
@@ -0,0 +1,110 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_infrastructure is
|
||||
port(
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
rst_calib1 : in std_logic;
|
||||
clk_int : in std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic
|
||||
);
|
||||
end vhdl_bl4_infrastructure;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure is
|
||||
|
||||
signal delay_sel_val1 : std_logic_vector(4 downto 0);
|
||||
signal rst_calib1_r1 : std_logic;
|
||||
signal rst_calib1_r2 : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
delay_sel_val1_val <= delay_sel_val1;
|
||||
dbg_delay_sel <= delay_sel_val1;
|
||||
dbg_rst_calib <= rst_calib1_r2;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '0' then
|
||||
rst_calib1_r1 <= rst_calib1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '1' then
|
||||
rst_calib1_r2 <= rst_calib1_r1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '1' then
|
||||
if (rst_calib1_r2 = '0') then
|
||||
delay_sel_val1 <= delay_sel_val;
|
||||
else
|
||||
delay_sel_val1 <= delay_sel_val1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
125
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd
Executable file
125
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd
Executable file
@@ -0,0 +1,125 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the FDDRRSE instantiations to the clocks.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_infrastructure_iobs_0 is
|
||||
port(
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
clk0 : in std_logic
|
||||
);
|
||||
end vhdl_bl4_infrastructure_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure_iobs_0 is
|
||||
|
||||
signal ddr2_clk_q : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
---- **************************************************
|
||||
---- iob attributes for instantiated FDDRRSE components
|
||||
---- **************************************************
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
vcc <= '1';
|
||||
clk180 <= not clk0;
|
||||
|
||||
--- ***********************************
|
||||
---- This includes instantiation of the output DDR flip flop
|
||||
---- for ddr clk's and dimm clk's
|
||||
---- ***********************************************************
|
||||
|
||||
|
||||
|
||||
|
||||
U_clk_i : FDDRRSE
|
||||
port map (
|
||||
Q => ddr2_clk_q,
|
||||
C0 => clk0,
|
||||
C1 => clk180,
|
||||
CE => vcc,
|
||||
D0 => vcc,
|
||||
D1 => gnd,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
---- ******************************************
|
||||
---- Ouput BUffers for ddr clk's and dimm clk's
|
||||
---- ******************************************
|
||||
|
||||
|
||||
|
||||
|
||||
r_inst : OBUFDS
|
||||
port map (
|
||||
I => ddr2_clk_q,
|
||||
O => ddr2_ck(0),
|
||||
OB => ddr2_ck_n(0)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
293
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd
Executable file
293
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd
Executable file
@@ -0,0 +1,293 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure_top.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has instantiations clk_dcm,cal_top and generate
|
||||
-- reset signals to the design
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_infrastructure_top is
|
||||
port(
|
||||
reset_in_n : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_clkb : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
sys_rst_val : out std_logic;
|
||||
sys_rst90_val : out std_logic;
|
||||
clk_int_val : out std_logic;
|
||||
clk90_int_val : out std_logic;
|
||||
sys_rst180_val : out std_logic;
|
||||
wait_200us : out std_logic;
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_infrastructure_top;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure_top is
|
||||
|
||||
component vhdl_bl4_clk_dcm
|
||||
port(
|
||||
input_clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
clk : out std_logic;
|
||||
clk90 : out std_logic;
|
||||
dcm_lock : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_cal_top
|
||||
port (
|
||||
clk : in std_logic;
|
||||
clk0dcmlock : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal user_rst : std_logic;
|
||||
signal user_cal_rst : std_logic;
|
||||
signal clk_int : std_logic;
|
||||
signal clk90_int : std_logic;
|
||||
signal dcm_lock : std_logic;
|
||||
signal sys_rst_o : std_logic;
|
||||
signal sys_rst_1 : std_logic := '1';
|
||||
signal sys_rst : std_logic;
|
||||
signal sys_rst90_o : std_logic;
|
||||
signal sys_rst90_1 : std_logic := '1';
|
||||
signal sys_rst90 : std_logic;
|
||||
signal sys_rst180_o : std_logic;
|
||||
signal sys_rst180_1 : std_logic := '1';
|
||||
signal sys_rst180 : std_logic;
|
||||
signal delay_sel_val1 : std_logic_vector(4 downto 0);
|
||||
signal clk_int_val1 : std_logic;
|
||||
signal clk_int_val2 : std_logic;
|
||||
signal clk90_int_val1 : std_logic;
|
||||
signal clk90_int_val2 : std_logic;
|
||||
signal wait_200us_i : std_logic;
|
||||
signal wait_200us_int : std_logic;
|
||||
signal wait_clk90 : std_logic;
|
||||
signal wait_clk270 : std_logic;
|
||||
signal counter200 : std_logic_vector(15 downto 0);
|
||||
signal sys_clk_ibuf : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
DIFF_ENDED_CLKS_INST : if(CLK_TYPE = "DIFFERENTIAL") generate
|
||||
begin
|
||||
SYS_CLK_INST : IBUFGDS_LVDS_25
|
||||
port map(
|
||||
I => sys_clk,
|
||||
IB => sys_clkb,
|
||||
O => sys_clk_ibuf
|
||||
);
|
||||
end generate;
|
||||
|
||||
SINGLE_ENDED_CLKS_INST : if(CLK_TYPE = "SINGLE_ENDED") generate
|
||||
begin
|
||||
SYS_CLK_INST : IBUFG
|
||||
port map(
|
||||
I => sys_clk_in,
|
||||
O => sys_clk_ibuf
|
||||
);
|
||||
end generate;
|
||||
|
||||
clk_int_val <= clk_int;
|
||||
clk90_int_val <= clk90_int;
|
||||
sys_rst_val <= sys_rst;
|
||||
sys_rst90_val <= sys_rst90;
|
||||
sys_rst180_val <= sys_rst180;
|
||||
delay_sel_val1_val <= delay_sel_val1;
|
||||
|
||||
|
||||
-- To remove delta delays in the clock signals observed during simulation
|
||||
-- ,Following signals are used
|
||||
|
||||
clk_int_val1 <= clk_int;
|
||||
clk90_int_val1 <= clk90_int;
|
||||
clk_int_val2 <= clk_int_val1;
|
||||
clk90_int_val2 <= clk90_int_val1;
|
||||
user_rst <= not reset_in_n when RESET_ACTIVE_LOW = '1' else reset_in_n;
|
||||
user_cal_rst <= reset_in_n when RESET_ACTIVE_LOW = '1' else not reset_in_n;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' then
|
||||
wait_200us_i <= '1';
|
||||
counter200 <= (others => '0');
|
||||
else
|
||||
if( counter200 < 33400) then
|
||||
wait_200us_i <= '1';
|
||||
counter200 <= counter200 + 1;
|
||||
else
|
||||
counter200 <= counter200;
|
||||
wait_200us_i <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
wait_200us <= wait_200us_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
wait_200us_int <= wait_200us_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '0' then
|
||||
if user_rst = '1' or dcm_lock = '0' then
|
||||
wait_clk270 <= '1';
|
||||
else
|
||||
wait_clk270 <= wait_200us_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '1' then
|
||||
wait_clk90 <= wait_clk270;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_200us_int = '1' then
|
||||
sys_rst_o <= '1';
|
||||
sys_rst_1 <= '1';
|
||||
sys_rst <= '1';
|
||||
else
|
||||
sys_rst_o <= '0';
|
||||
sys_rst_1 <= sys_rst_o;
|
||||
sys_rst <= sys_rst_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_clk90 = '1' then
|
||||
sys_rst90_o <= '1';
|
||||
sys_rst90_1 <= '1';
|
||||
sys_rst90 <= '1';
|
||||
else
|
||||
sys_rst90_o <= '0';
|
||||
sys_rst90_1 <= sys_rst90_o;
|
||||
sys_rst90 <= sys_rst90_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '0' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_clk270 = '1' then
|
||||
sys_rst180_o <= '1';
|
||||
sys_rst180_1 <= '1';
|
||||
sys_rst180 <= '1';
|
||||
else
|
||||
sys_rst180_o <= '0';
|
||||
sys_rst180_1 <= sys_rst180_o;
|
||||
sys_rst180 <= sys_rst180_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
clk_dcm0 : vhdl_bl4_clk_dcm
|
||||
port map (
|
||||
input_clk => sys_clk_ibuf,
|
||||
rst => user_rst,
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
dcm_lock => dcm_lock
|
||||
);
|
||||
|
||||
cal_top0 : vhdl_bl4_cal_top
|
||||
port map (
|
||||
clk => clk_int_val2,
|
||||
clk0dcmlock => dcm_lock,
|
||||
reset => user_cal_rst,
|
||||
tapfordqs => delay_sel_val1,
|
||||
dbg_phase_cnt => dbg_phase_cnt,
|
||||
dbg_cnt => dbg_cnt,
|
||||
dbg_trans_onedtct => dbg_trans_onedtct,
|
||||
dbg_trans_twodtct => dbg_trans_twodtct,
|
||||
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
|
||||
);
|
||||
|
||||
end arc;
|
||||
225
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd
Executable file
225
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd
Executable file
@@ -0,0 +1,225 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations infrastructure_iobs,
|
||||
-- data_path_iobs and controller_iobs modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_iobs_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
rst_dqs_div_int : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_iobs_0;
|
||||
|
||||
|
||||
architecture arc of vhdl_bl4_iobs_0 is
|
||||
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
|
||||
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_3_ddr2_sp3, Coregen 11.4";
|
||||
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_3,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000}";
|
||||
|
||||
component vhdl_bl4_infrastructure_iobs_0
|
||||
port(
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
clk0 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_controller_iobs_0
|
||||
port(
|
||||
clk0 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
rst_dqs_div_int : in std_logic;
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
ddr_ODT : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_path_iobs_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
infrastructure_iobs0 : vhdl_bl4_infrastructure_iobs_0
|
||||
port map (
|
||||
clk0 => clk,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n
|
||||
);
|
||||
|
||||
controller_iobs0 : vhdl_bl4_controller_iobs_0
|
||||
port map (
|
||||
clk0 => clk,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl((ROW_ADDRESS -1) downto 0),
|
||||
ddr_ba_cntrl => ddr_ba_cntrl((BANK_ADDRESS -1) downto 0),
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
ddr_rasb => ddr_rasb,
|
||||
ddr_casb => ddr_casb,
|
||||
ddr_web => ddr_web,
|
||||
ddr_ba => ddr_ba((BANK_ADDRESS -1) downto 0),
|
||||
ddr_address => ddr_address((ROW_ADDRESS -1) downto 0),
|
||||
ddr_cke => ddr_cke,
|
||||
ddr_csb => ddr_csb,
|
||||
ddr_odt => ddr_odt,
|
||||
rst_dqs_div => rst_dqs_div,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out
|
||||
);
|
||||
|
||||
datapath_iobs0 : vhdl_bl4_data_path_iobs_0
|
||||
port map (
|
||||
clk => clk,
|
||||
clk90 => clk90,
|
||||
dqs_reset => dqs_reset,
|
||||
dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr_dqs,
|
||||
ddr_dqs_n => ddr_dqs_n,
|
||||
ddr_dq => ddr_dq,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
ddr_dm => ddr_dm,
|
||||
ddr_dq_val => dq
|
||||
);
|
||||
|
||||
end arc;
|
||||
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd
Executable file
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_parameters_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the parameters used in the design
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
package vhdl_bl4_parameters_0 is
|
||||
|
||||
-- The reset polarity is set to active low by default.
|
||||
-- You can change this by editing the parameter RESET_ACTIVE_LOW.
|
||||
-- Please do not change any of the other parameters directly by editing the RTL.
|
||||
-- All other changes should be done through the GUI.
|
||||
|
||||
constant DATA_WIDTH : INTEGER := 16;
|
||||
constant DATA_STROBE_WIDTH : INTEGER := 2;
|
||||
constant DATA_MASK_WIDTH : INTEGER := 2;
|
||||
constant CLK_WIDTH : INTEGER := 1;
|
||||
constant CKE_WIDTH : INTEGER := 1;
|
||||
constant ROW_ADDRESS : INTEGER := 13;
|
||||
constant MEMORY_WIDTH : INTEGER := 8;
|
||||
constant REGISTERED : INTEGER := 0;
|
||||
constant DATABITSPERSTROBE : INTEGER := 8;
|
||||
constant RESET_PORT : INTEGER := 0;
|
||||
constant MASK_ENABLE : INTEGER := 1;
|
||||
constant USE_DM_PORT : INTEGER := 1;
|
||||
constant COLUMN_ADDRESS : INTEGER := 10;
|
||||
constant BANK_ADDRESS : INTEGER := 2;
|
||||
constant DEBUG_EN : INTEGER := 1;
|
||||
constant CLK_TYPE : string := "SINGLE_ENDED";
|
||||
constant LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0010100110010";
|
||||
|
||||
constant EXT_LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0000000000000";
|
||||
|
||||
constant RESET_ACTIVE_LOW : std_logic := '0';
|
||||
constant RAS_COUNT_VALUE : std_logic_vector(4 downto 0) := "00101";
|
||||
constant RP_COUNT_VALUE : std_logic_vector(2 downto 0) := "001";
|
||||
constant RFC_COUNT_VALUE : std_logic_vector(7 downto 0) := "00001101";
|
||||
constant TWR_COUNT_VALUE : std_logic_vector(2 downto 0) := "010";
|
||||
constant MAX_REF_WIDTH : INTEGER := 10;
|
||||
constant MAX_REF_CNT : std_logic_vector(9 downto 0) := "1111100111";
|
||||
|
||||
end vhdl_bl4_parameters_0 ;
|
||||
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd
Executable file
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd
Executable file
@@ -0,0 +1,215 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_ram8d_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates RAM16X1 premitives. There will be 8 or 4 RAM16X1
|
||||
-- instances depending on the number of data bits per strobe.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
library UNISIM;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.STD_LOGIC_ARITH.all;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_ram8d_0 is
|
||||
port (
|
||||
dout : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
waddr : in std_logic_vector(3 downto 0);
|
||||
din : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
raddr : in std_logic_vector(3 downto 0);
|
||||
wclk0 : in std_logic;
|
||||
wclk1 : in std_logic;
|
||||
we : in std_logic
|
||||
);
|
||||
end vhdl_bl4_ram8d_0;
|
||||
|
||||
architecture arc of vhdl_bl4_ram8d_0 is
|
||||
|
||||
begin
|
||||
|
||||
fifo_bit0 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(0),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(0),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit1 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(1),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(1),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit2 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(2),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(2),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit3 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(3),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(3),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit4 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(4),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(4),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit5 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(5),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(5),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit6 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(6),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(6),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit7 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(7),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(7),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
end arc;
|
||||
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd
Executable file
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd
Executable file
@@ -0,0 +1,215 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_ram8d_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:57 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates RAM16X1 premitives. There will be 8 or 4 RAM16X1
|
||||
-- instances depending on the number of data bits per strobe.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
library UNISIM;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.STD_LOGIC_ARITH.all;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_ram8d_1 is
|
||||
port (
|
||||
dout : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
waddr : in std_logic_vector(3 downto 0);
|
||||
din : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
raddr : in std_logic_vector(3 downto 0);
|
||||
wclk0 : in std_logic;
|
||||
wclk1 : in std_logic;
|
||||
we : in std_logic
|
||||
);
|
||||
end vhdl_bl4_ram8d_1;
|
||||
|
||||
architecture arc of vhdl_bl4_ram8d_1 is
|
||||
|
||||
begin
|
||||
|
||||
fifo_bit0 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(0),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(0),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit1 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(1),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(1),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit2 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(2),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(2),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit3 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(3),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(3),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit4 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(4),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(4),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit5 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(5),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(5),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit6 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(6),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(6),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit7 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(7),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(7),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
end arc;
|
||||
147
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd
Executable file
147
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd
Executable file
@@ -0,0 +1,147 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_rd_gray_cntr.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates read address for the FIFOs.
|
||||
--*****************************************************************************
|
||||
|
||||
-- fifo_rd_addr gray counter with synchronous reset
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_rd_gray_cntr is
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
rgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end vhdl_bl4_rd_gray_cntr;
|
||||
|
||||
architecture arc of vhdl_bl4_rd_gray_cntr is
|
||||
|
||||
signal gc_int : std_logic_vector(3 downto 0);
|
||||
signal d_in : std_logic_vector(3 downto 0);
|
||||
signal reset90_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
rgc_gcnt <= gc_int(3 downto 0);
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if(clk90'event and clk90 = '1') then
|
||||
reset90_r <= reset90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(gc_int)
|
||||
begin
|
||||
case gc_int is
|
||||
when "0000" => d_in <= "0001"; --0 > 1
|
||||
when "0001" => d_in <= "0011"; --1 > 3
|
||||
when "0010" => d_in <= "0110"; --2 > 6
|
||||
when "0011" => d_in <= "0010"; --3 > 2
|
||||
when "0100" => d_in <= "1100"; --4 > c
|
||||
when "0101" => d_in <= "0100"; --5 > 4
|
||||
when "0110" => d_in <= "0111"; --6 > 7
|
||||
when "0111" => d_in <= "0101"; --7 > 5
|
||||
when "1000" => d_in <= "0000"; --8 > 0
|
||||
when "1001" => d_in <= "1000"; --9 > 8
|
||||
when "1010" => d_in <= "1011"; --10 > b
|
||||
when "1011" => d_in <= "1001"; --11 > 9
|
||||
when "1100" => d_in <= "1101"; --12 > d
|
||||
when "1101" => d_in <= "1111"; --13 > f
|
||||
when "1110" => d_in <= "1010"; --14 > a
|
||||
when "1111" => d_in <= "1110"; --15 > e
|
||||
when others => d_in <= "0001"; --0 > 1
|
||||
end case;
|
||||
end process;
|
||||
|
||||
bit0 : FDRE
|
||||
port map (
|
||||
Q => gc_int(0),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(0),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit1 : FDRE
|
||||
port map (
|
||||
Q => gc_int(1),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(1),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit2 : FDRE
|
||||
port map (
|
||||
Q => gc_int(2),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(2),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit3 : FDRE
|
||||
port map (
|
||||
Q => gc_int(3),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(3),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
end arc;
|
||||
106
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd
Executable file
106
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd
Executable file
@@ -0,0 +1,106 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dm_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates DDR IOB output flip-flops, and an
|
||||
-- output buffer for the data mask bits.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dm_iob is
|
||||
port (
|
||||
ddr_dm : out std_logic; --Data mask output
|
||||
mask_falling : in std_logic; --Mask output on falling edge
|
||||
mask_rising : in std_logic; --Mask output on rising edge
|
||||
clk90 : in std_logic
|
||||
);
|
||||
end vhdl_bl4_s3_dm_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dm_iob is
|
||||
|
||||
--***********************************************************************\
|
||||
-- Internal signal declaration
|
||||
--***********************************************************************/
|
||||
|
||||
signal mask_o : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
vcc <= '1';
|
||||
clk270 <= not clk90;
|
||||
|
||||
-- Data Mask Output during a write command
|
||||
|
||||
DDR_DM0_OUT : FDDRRSE
|
||||
port map (
|
||||
Q => mask_o,
|
||||
C0 => clk270,
|
||||
C1 => clk90,
|
||||
CE => vcc,
|
||||
D0 => mask_rising,
|
||||
D1 => mask_falling,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
DM1_OBUF : OBUF
|
||||
port map (
|
||||
I => mask_o,
|
||||
O => ddr_dm
|
||||
);
|
||||
|
||||
end arc;
|
||||
135
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd
Executable file
135
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd
Executable file
@@ -0,0 +1,135 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dq_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiate DDR IOB output flip-flops, an
|
||||
-- output buffer with registered tri-state, and an input buffer
|
||||
-- for a single data/dq bit. The DDR IOB output flip-flops
|
||||
-- are used to forward data to memory during a write.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dq_iob is
|
||||
port (
|
||||
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
|
||||
write_data_falling : in std_logic; --Transmit data, output on falling edge
|
||||
write_data_rising : in std_logic; --Transmit data, output on rising edge
|
||||
read_data_in : out std_logic; -- Received data
|
||||
clk90 : in std_logic; --Clock 90
|
||||
write_en_val : in std_logic
|
||||
);
|
||||
end vhdl_bl4_s3_dq_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dq_iob is
|
||||
|
||||
--***********************************************************************\
|
||||
-- Internal signal declaration
|
||||
--***********************************************************************/
|
||||
signal ddr_en : std_logic; -- Tri-state enable signal
|
||||
signal ddr_dq_q : std_logic; -- Data output intermediate signal
|
||||
signal gnd : std_logic;
|
||||
signal clock_en : std_logic;
|
||||
signal enable_b : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
|
||||
attribute iob : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute iob of DQ_T : label is "FORCE";
|
||||
attribute syn_useioff of DQ_T : label is true;
|
||||
|
||||
begin
|
||||
|
||||
clk270 <= not clk90;
|
||||
gnd <= '0';
|
||||
enable_b <= not write_en_val;
|
||||
clock_en <= '1';
|
||||
|
||||
-- Transmission data path
|
||||
|
||||
DDR_OUT : FDDRRSE
|
||||
port map (
|
||||
Q => ddr_dq_q,
|
||||
C0 => clk270,
|
||||
C1 => clk90,
|
||||
CE => clock_en,
|
||||
D0 => write_data_rising,
|
||||
D1 => write_data_falling,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
DQ_T : FD
|
||||
port map (
|
||||
D => enable_b,
|
||||
C => clk270,
|
||||
Q => ddr_en
|
||||
);
|
||||
|
||||
DQ_OBUFT : OBUFT
|
||||
port map (
|
||||
I => ddr_dq_q,
|
||||
T => ddr_en,
|
||||
O => ddr_dq_inout
|
||||
);
|
||||
|
||||
-- Receive data path
|
||||
|
||||
DQ_IBUF : IBUF
|
||||
port map(
|
||||
I => ddr_dq_inout,
|
||||
O => read_data_in
|
||||
);
|
||||
|
||||
end arc;
|
||||
148
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd
Executable file
148
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd
Executable file
@@ -0,0 +1,148 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dqs_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates DDR IOB output flip-flops, an
|
||||
-- output buffer with registered tri-state, and an input buffer
|
||||
-- for a single strobe/dqs bit. The DDR IOB output flip-flops
|
||||
-- are used to forward strobe to memory during a write. During
|
||||
-- a read, the output of the IBUF is routed to the internal
|
||||
-- delay module, dqs_delay.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dqs_iob is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
ddr_dqs_reset : in std_logic;
|
||||
ddr_dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic;
|
||||
ddr_dqs_n : inout std_logic;
|
||||
dqs : out std_logic);
|
||||
end vhdl_bl4_s3_dqs_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dqs_iob is
|
||||
|
||||
|
||||
signal dqs_q : std_logic;
|
||||
signal ddr_dqs_enable1 : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal ddr_dqs_enable_b : std_logic;
|
||||
signal data1 : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
attribute IOB : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute IOB of U1 : label is "FORCE";
|
||||
attribute syn_useioff of U1 : label is true;
|
||||
|
||||
begin
|
||||
|
||||
--******************************************************************************
|
||||
-- Output DDR generation. This includes instantiation of the output DDR flip flop.
|
||||
-- Additionally, to keep synthesis tools from register sharing, manually
|
||||
-- instantiate the output tri-state flip-flop.
|
||||
--******************************************************************************
|
||||
vcc <= '1';
|
||||
gnd <= '0';
|
||||
clk180 <= not clk;
|
||||
ddr_dqs_enable_b <= not ddr_dqs_enable;
|
||||
data1 <= '0' when ddr_dqs_reset = '1' else
|
||||
'1';
|
||||
|
||||
U1 : FD
|
||||
port map (
|
||||
D => ddr_dqs_enable_b,
|
||||
Q => ddr_dqs_enable1,
|
||||
C => clk
|
||||
);
|
||||
|
||||
|
||||
U2 : FDDRRSE
|
||||
port map (
|
||||
Q => dqs_q,
|
||||
C0 => clk,
|
||||
C1 => clk180,
|
||||
CE => vcc,
|
||||
D0 => data1,
|
||||
D1 => gnd,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
|
||||
|
||||
--***********************************************************************
|
||||
-- IO buffer for dqs signal. Allows for distribution of dqs
|
||||
-- to the data (DQ) loads.
|
||||
--***********************************************************************
|
||||
|
||||
|
||||
U3 : OBUFTDS port map (
|
||||
I => dqs_q,
|
||||
T => ddr_dqs_enable1,
|
||||
O => ddr_dqs,
|
||||
OB => ddr_dqs_n
|
||||
);
|
||||
|
||||
U4 : IBUFDS port map(
|
||||
I => ddr_dqs,
|
||||
IB => ddr_dqs_n,
|
||||
O => dqs
|
||||
);
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
386
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd
Executable file
386
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd
Executable file
@@ -0,0 +1,386 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_tap_dly.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :This module generates a 32 bit tap delay register used by the
|
||||
-- cal_ctl module to find out the phase transitions.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_tap_dly is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapin : in std_logic;
|
||||
flop2 : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end vhdl_bl4_tap_dly;
|
||||
|
||||
architecture arc_tap_dly of vhdl_bl4_tap_dly is
|
||||
|
||||
signal tap : std_logic_vector(31 downto 0);
|
||||
signal flop1 : std_logic_vector(31 downto 0);
|
||||
signal high : std_logic;
|
||||
signal low : std_logic;
|
||||
signal flop2_xnor : std_logic_vector(30 downto 0);
|
||||
signal reset_r : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of tap : signal is true;
|
||||
attribute syn_preserve of flop1 : signal is true;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk='1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
high <= '1';
|
||||
low <= '0';
|
||||
|
||||
l0 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tapin,
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(0)
|
||||
);
|
||||
|
||||
l1 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(0),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(1)
|
||||
);
|
||||
l2 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(1),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(2)
|
||||
);
|
||||
l3 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(2),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(3)
|
||||
);
|
||||
l4 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(3),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(4)
|
||||
);
|
||||
l5 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(4),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(5)
|
||||
);
|
||||
l6 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(5),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(6)
|
||||
);
|
||||
l7 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(6),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(7)
|
||||
);
|
||||
l8 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(7),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(8)
|
||||
);
|
||||
l9 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(8),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(9)
|
||||
);
|
||||
l10 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(9),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(10)
|
||||
);
|
||||
l11 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(10),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(11)
|
||||
);
|
||||
l12 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(11),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(12)
|
||||
);
|
||||
l13 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(12),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(13)
|
||||
);
|
||||
l14 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(13),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(14)
|
||||
);
|
||||
l15 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(14),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(15)
|
||||
);
|
||||
l16 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(15),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(16)
|
||||
);
|
||||
l17 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(16),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(17)
|
||||
);
|
||||
l18 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(17),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(18)
|
||||
);
|
||||
l19 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(18),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(19)
|
||||
);
|
||||
l20 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(19),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(20)
|
||||
);
|
||||
l21 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(20),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(21)
|
||||
);
|
||||
l22 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(21),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(22)
|
||||
);
|
||||
l23 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(22),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(23)
|
||||
);
|
||||
l24 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(23),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(24)
|
||||
);
|
||||
l25 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(24),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(25)
|
||||
);
|
||||
l26 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(25),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(26)
|
||||
);
|
||||
l27 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(26),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(27)
|
||||
);
|
||||
l28 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(27),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(28)
|
||||
);
|
||||
l29 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(28),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(29)
|
||||
);
|
||||
l30 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(29),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(30)
|
||||
);
|
||||
l31 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(30),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(31)
|
||||
);
|
||||
|
||||
gen_tap1 : for tap1_i in 0 to 31 generate
|
||||
r : FDR port map (
|
||||
Q => flop1(tap1_i),
|
||||
C => clk,
|
||||
D => tap(tap1_i),
|
||||
R => reset_r
|
||||
);
|
||||
end generate;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to 30 generate
|
||||
flop2_xnor(asgn_i) <= flop1(asgn_i) xnor flop1(asgn_i+1);
|
||||
end generate;
|
||||
|
||||
gen_tap2 : for tap2_i in 0 to 30 generate
|
||||
u : FDR port map (
|
||||
Q => flop2(tap2_i),
|
||||
C => clk,
|
||||
D => flop2_xnor(tap2_i),
|
||||
R => reset_r
|
||||
);
|
||||
end generate;
|
||||
|
||||
u31 : FDR
|
||||
port map (
|
||||
Q => flop2(31),
|
||||
C => clk,
|
||||
D => flop1(31),
|
||||
R => reset_r
|
||||
);
|
||||
|
||||
end arc_tap_dly;
|
||||
374
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd
Executable file
374
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd
Executable file
@@ -0,0 +1,374 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_top_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This modules has the instantiations infrastructure, iobs,
|
||||
-- controller and data_paths modules
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_top_0 is
|
||||
port(
|
||||
wait_200us : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
|
||||
downto 0) := (others => 'Z');
|
||||
user_data_valid : out std_logic;
|
||||
user_input_address : in std_logic_vector(((ROW_ADDRESS +
|
||||
COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
|
||||
user_command_register : in std_logic_vector(2 downto 0);
|
||||
burst_done : in std_logic;
|
||||
auto_ref_req : out std_logic;
|
||||
user_cmd_ack : out std_logic;
|
||||
init_done : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
:= (others => 'Z');
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
|
||||
clk_int : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_top_0;
|
||||
|
||||
architecture arc of vhdl_bl4_top_0 is
|
||||
|
||||
component vhdl_bl4_controller_0
|
||||
port(
|
||||
auto_ref_req : out std_logic;
|
||||
wait_200us : in std_logic;
|
||||
clk : in std_logic;
|
||||
rst0 : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
address : in std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS)-1)
|
||||
downto 0);
|
||||
bank_addr : in std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
command_register : in std_logic_vector(2 downto 0);
|
||||
burst_done : in std_logic;
|
||||
ddr_rasb_cntrl : out std_logic;
|
||||
ddr_casb_cntrl : out std_logic;
|
||||
ddr_web_cntrl : out std_logic;
|
||||
ddr_ba_cntrl : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr_address_cntrl : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_cke_cntrl : out std_logic;
|
||||
ddr_csb_cntrl : out std_logic;
|
||||
ddr_ODT_cntrl : out std_logic;
|
||||
dqs_enable : out std_logic;
|
||||
dqs_reset : out std_logic;
|
||||
write_enable : out std_logic;
|
||||
rst_calib : out std_logic;
|
||||
rst_dqs_div_int : out std_logic;
|
||||
cmd_ack : out std_logic;
|
||||
init : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
read_fifo_rden : out std_logic; -- Added new signal
|
||||
dbg_controller : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_path_0
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
reset : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic; -- Added new signal
|
||||
-- debug singals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_infrastructure
|
||||
port(
|
||||
clk_int : in std_logic;
|
||||
rst_calib1 : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_iobs_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_ODT_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
rst_dqs_div_int : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_calib : std_logic;
|
||||
signal delay_sel : std_logic_vector(4 downto 0);
|
||||
signal write_enable : std_logic;
|
||||
signal dqs_div_rst : std_logic;
|
||||
signal dqs_enable : std_logic;
|
||||
signal dqs_reset : std_logic;
|
||||
signal dqs_int_delay_in : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dq : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_en_val : std_logic;
|
||||
signal data_mask_f : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal data_mask_r : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_falling : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data_rising : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal ddr_rasb_cntrl : std_logic;
|
||||
signal ddr_casb_cntrl : std_logic;
|
||||
signal ddr_web_cntrl : std_logic;
|
||||
signal ddr_ba_cntrl : std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
signal ddr_address_cntrl : std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
signal ddr_cke_cntrl : std_logic;
|
||||
signal ddr_csb_cntrl : std_logic;
|
||||
signal ddr_odt_cntrl : std_logic;
|
||||
signal rst_dqs_div_int : std_logic;
|
||||
signal read_fifo_rden : std_logic;
|
||||
begin
|
||||
|
||||
|
||||
|
||||
|
||||
controller0 : vhdl_bl4_controller_0
|
||||
port map (
|
||||
auto_ref_req => auto_ref_req,
|
||||
wait_200us => wait_200us,
|
||||
clk => clk_int,
|
||||
rst0 => sys_rst,
|
||||
rst180 => sys_rst180,
|
||||
address => user_input_address(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)-1) downto BANK_ADDRESS),
|
||||
bank_addr => user_input_address(BANK_ADDRESS-1 downto 0),
|
||||
command_register => user_command_register,
|
||||
burst_done => burst_done,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_ba_cntrl => ddr_ba_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
dqs_enable => dqs_enable,
|
||||
dqs_reset => dqs_reset,
|
||||
write_enable => write_enable,
|
||||
rst_calib => rst_calib,
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
cmd_ack => user_cmd_ack,
|
||||
init => init_done,
|
||||
ar_done => ar_done,
|
||||
read_fifo_rden => read_fifo_rden, -- Added new signal
|
||||
dbg_controller => dbg_controller
|
||||
);
|
||||
|
||||
data_path0 : vhdl_bl4_data_path_0
|
||||
port map (
|
||||
user_input_data => user_input_data,
|
||||
user_data_mask => user_data_mask,
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
reset => sys_rst,
|
||||
reset90 => sys_rst90,
|
||||
write_enable => write_enable,
|
||||
rst_dqs_div_in => dqs_div_rst,
|
||||
delay_sel => delay_sel,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
dq => dq,
|
||||
u_data_val => user_data_valid,
|
||||
user_output_data => user_output_data,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
read_fifo_rden => read_fifo_rden, -- Added new signal
|
||||
--debug signals
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
infrastructure0 : vhdl_bl4_infrastructure
|
||||
port map (
|
||||
clk_int => clk_int,
|
||||
rst_calib1 => rst_calib,
|
||||
delay_sel_val => delay_sel_val,
|
||||
delay_sel_val1_val => delay_sel,
|
||||
dbg_delay_sel => dbg_delay_sel,
|
||||
dbg_rst_calib => dbg_rst_calib
|
||||
);
|
||||
|
||||
iobs0 : vhdl_bl4_iobs_0
|
||||
port map (
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl,
|
||||
ddr_ba_cntrl => ddr_ba_cntrl,
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
dqs_reset => dqs_reset,
|
||||
dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr2_dqs,
|
||||
ddr_dqs_n => ddr2_dqs_n,
|
||||
ddr_dq => ddr2_dq,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
ddr_odt => ddr2_odt,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
ddr_rasb => ddr2_ras_n,
|
||||
ddr_casb => ddr2_cas_n,
|
||||
ddr_web => ddr2_we_n,
|
||||
ddr_ba => ddr2_ba,
|
||||
ddr_address => ddr2_a,
|
||||
ddr_cke => ddr2_cke,
|
||||
ddr_csb => ddr2_cs_n,
|
||||
rst_dqs_div => dqs_div_rst,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
ddr_dm => ddr2_dm,
|
||||
dq => dq
|
||||
);
|
||||
|
||||
end arc;
|
||||
139
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd
Executable file
139
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd
Executable file
@@ -0,0 +1,139 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_wr_gray_cntr.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :
|
||||
--*****************************************************************************
|
||||
-- fifo_wr_addr gray counter with synchronous reset
|
||||
-- Gray counter is used for FIFO address counter
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_wr_gray_cntr is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
wgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end vhdl_bl4_wr_gray_cntr;
|
||||
|
||||
architecture arc of vhdl_bl4_wr_gray_cntr is
|
||||
|
||||
signal d_in : std_logic_vector(3 downto 0);
|
||||
signal gc_int : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
wgc_gcnt <= gc_int(3 downto 0);
|
||||
|
||||
process(gc_int)
|
||||
begin
|
||||
case gc_int is
|
||||
when "0000" => d_in <= "0001"; --0 > 1
|
||||
when "0001" => d_in <= "0011"; --1 > 3
|
||||
when "0010" => d_in <= "0110"; --2 > 6
|
||||
when "0011" => d_in <= "0010"; --3 > 2
|
||||
when "0100" => d_in <= "1100"; --4 > c
|
||||
when "0101" => d_in <= "0100"; --5 > 4
|
||||
when "0110" => d_in <= "0111"; --6 > 7
|
||||
when "0111" => d_in <= "0101"; --7 > 5
|
||||
when "1000" => d_in <= "0000"; --8 > 0
|
||||
when "1001" => d_in <= "1000"; --9 > 8
|
||||
when "1010" => d_in <= "1011"; --a > b
|
||||
when "1011" => d_in <= "1001"; --b > 9
|
||||
when "1100" => d_in <= "1101"; --c > d
|
||||
when "1101" => d_in <= "1111"; --d > f
|
||||
when "1110" => d_in <= "1010"; --e > a
|
||||
when "1111" => d_in <= "1110"; --f > e
|
||||
when others => d_in <= "0001"; --0 > 1
|
||||
end case;
|
||||
end process;
|
||||
|
||||
bit0 : FDCE
|
||||
port map (
|
||||
Q => gc_int(0),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(0)
|
||||
);
|
||||
|
||||
bit1 : FDCE
|
||||
port map (
|
||||
Q => gc_int(1),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(1)
|
||||
);
|
||||
|
||||
bit2 : FDCE
|
||||
port map (
|
||||
Q => gc_int(2),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(2)
|
||||
);
|
||||
|
||||
bit3 : FDCE
|
||||
port map (
|
||||
Q => gc_int(3),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(3)
|
||||
);
|
||||
|
||||
end arc;
|
||||
1993
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
Executable file
1993
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
Executable file
File diff suppressed because it is too large
Load Diff
1089
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model_parameters.vh
Executable file
1089
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model_parameters.vh
Executable file
File diff suppressed because it is too large
Load Diff
131
src/clk_reset.vhd
Executable file
131
src/clk_reset.vhd
Executable file
@@ -0,0 +1,131 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 02/26/2013 05:31:02 PM
|
||||
-- Design Name:
|
||||
-- Module Name: clk_reset - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
-- Contains DCM instance and related logic for system clock & reset control
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity clk_reset is
|
||||
Generic (
|
||||
reset_dcm_on_ext_reset : BOOLEAN := false
|
||||
);
|
||||
Port ( clkIn50 : in STD_ULOGIC;
|
||||
sysClk50 : out STD_ULOGIC;
|
||||
rstIn : in STD_ULOGIC;
|
||||
sysRst50 : out STD_ULOGIC);
|
||||
end clk_reset;
|
||||
|
||||
architecture Behavioral of clk_reset is
|
||||
signal locked_int, rst_int : std_ulogic;
|
||||
signal clkOut50_int : std_ulogic;
|
||||
|
||||
constant reset_pulse_width : integer := 3;
|
||||
|
||||
signal rstIn_sync_dcm : std_ulogic_vector(2 downto 0) := "000";
|
||||
signal dcm_in_rst : std_ulogic;
|
||||
signal dcm_in_rst_ctr : natural range 0 to reset_pulse_width-1;
|
||||
signal locked_prev : std_ulogic;
|
||||
|
||||
signal rstIn_sync_sys : std_ulogic_vector(2 downto 0) := "000";
|
||||
signal sys_in_rst : std_ulogic;
|
||||
signal sys_in_rst_ctr : natural range 0 to reset_pulse_width-1;
|
||||
|
||||
begin
|
||||
dcm50 : DCM_SP
|
||||
generic map (
|
||||
CLKIN_PERIOD => 20.0
|
||||
)
|
||||
port map (
|
||||
CLKIN => clkIn50,
|
||||
CLKFB => clkOut50_int,
|
||||
CLK0 => clkOut50_int,
|
||||
|
||||
LOCKED => locked_int,
|
||||
RST => rst_int,
|
||||
|
||||
PSEN => '0'
|
||||
);
|
||||
|
||||
dcm_rst_gen : process(clkIn50)
|
||||
begin
|
||||
if rising_edge(clkIn50) then
|
||||
-- sync rstIn to clkIn50 clock
|
||||
rstIn_sync_dcm <= rstIn_sync_dcm(rstIn_sync_dcm'left-1 downto 0) & rstIn;
|
||||
|
||||
-- dcm is reset when a) external reset is applied (if reset_dcm_on_ext_reset is set)
|
||||
-- or b) locked goes from 1 to 0
|
||||
locked_prev <= locked_int;
|
||||
if (rstIn_sync_dcm(rstIn_sync_dcm'left) = '1' and reset_dcm_on_ext_reset) or
|
||||
(locked_prev = '1' and locked_int = '0') then
|
||||
dcm_in_rst <= '1';
|
||||
dcm_in_rst_ctr <= reset_pulse_width-1;
|
||||
rst_int <= '1';
|
||||
elsif dcm_in_rst = '1' then
|
||||
-- the dcm reset must be high for at least 3 clkIn50 cycles
|
||||
if dcm_in_rst_ctr = 0 then
|
||||
rst_int <= '0';
|
||||
dcm_in_rst <= '0';
|
||||
else
|
||||
dcm_in_rst_ctr <= dcm_in_rst_ctr - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process dcm_rst_gen;
|
||||
|
||||
sys_rst_gen : process(clkOut50_int, locked_int)
|
||||
begin
|
||||
if locked_int = '0' then
|
||||
-- hold system in reset while DCM is not locked
|
||||
sysRst50 <= '1';
|
||||
sys_in_rst <= '1';
|
||||
sys_in_rst_ctr <= reset_pulse_width-1;
|
||||
rstIn_sync_sys <= (others => '0');
|
||||
elsif rising_edge(clkOut50_int) then
|
||||
-- sync rstIn to clkOut50 clock
|
||||
rstIn_sync_sys <= rstIn_sync_sys(rstIn_sync_sys'left-1 downto 0) & rstIn;
|
||||
|
||||
-- system is reset when dcm locks or external reset is applied
|
||||
if rstIn_sync_sys(rstIn_sync_sys'left) = '1' then
|
||||
sys_in_rst <= '1';
|
||||
sys_in_rst_ctr <= reset_pulse_width-1;
|
||||
sysRst50 <= '1';
|
||||
elsif sys_in_rst = '1' then
|
||||
-- Hold system in reset for at least 3 clkOut50 cycles
|
||||
if sys_in_rst_ctr = 0 then
|
||||
sysRst50 <= '0';
|
||||
sys_in_rst <= '0';
|
||||
else
|
||||
sys_in_rst_ctr <= sys_in_rst_ctr - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process sys_rst_gen;
|
||||
|
||||
sysClk50 <= clkOut50_int;
|
||||
end Behavioral;
|
||||
184
src/toplevel.vhd
Executable file
184
src/toplevel.vhd
Executable file
@@ -0,0 +1,184 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/02/2012 03:48:47 PM
|
||||
-- Design Name:
|
||||
-- Module Name: toplevel - Mixed
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
use work.all;
|
||||
|
||||
entity toplevel is
|
||||
Port (
|
||||
-- global signals
|
||||
clkin_50MHz : IN std_ulogic;
|
||||
clkin_133MHz : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
|
||||
-- VGA port
|
||||
vga_r, vga_g, vga_b : OUT std_ulogic_vector(3 downto 0);
|
||||
vga_vsync, vga_hsync : OUT std_ulogic;
|
||||
|
||||
-- spi flash
|
||||
dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic;
|
||||
dataflash_miso : IN std_ulogic;
|
||||
|
||||
-- LEDs
|
||||
led : OUT std_ulogic_vector(7 downto 0);
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0)
|
||||
);
|
||||
end toplevel;
|
||||
|
||||
architecture Mixed of toplevel is
|
||||
component clk_reset is
|
||||
Generic (
|
||||
reset_dcm_on_ext_reset : BOOLEAN := false
|
||||
);
|
||||
Port ( clkIn50 : in STD_ULOGIC;
|
||||
sysClk50 : out STD_ULOGIC;
|
||||
rstIn : in STD_ULOGIC;
|
||||
sysRst50 : out STD_ULOGIC);
|
||||
end component;
|
||||
component wb_ddr_ctrl is
|
||||
Port (
|
||||
-- DDR2 control
|
||||
ddr2_clock : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal sysClk, sysRst : std_logic;
|
||||
|
||||
signal wb_ddr_dat_i : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ddr_dat_o : std_ulogic_vector(31 downto 0);
|
||||
signal wb_ddr_ack_o : std_ulogic;
|
||||
signal wb_ddr_adr_i : std_ulogic_vector(25 downto 2);
|
||||
signal wb_ddr_cyc_i : std_ulogic;
|
||||
signal wb_ddr_sel_i : std_ulogic_vector(3 downto 0);
|
||||
signal wb_ddr_stb_i : std_ulogic;
|
||||
signal wb_ddr_we_i : std_ulogic;
|
||||
signal wb_ddr_cti_i : std_ulogic_vector(2 downto 0);
|
||||
signal wb_ddr_bte_i : std_ulogic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
sys_clk_rst : clk_reset
|
||||
port map (
|
||||
clkIn50 => clkin_50MHz,
|
||||
rstIn => reset,
|
||||
sysClk50 => sysClk,
|
||||
sysRst50 => sysRst
|
||||
);
|
||||
|
||||
ddr_ctrl0 : wb_ddr_ctrl
|
||||
port map (
|
||||
-- DDR2 control
|
||||
ddr2_clock => clkin_133MHz,
|
||||
ddr2_reset => reset,
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
|
||||
clk_i => sysClk,
|
||||
rst_i => sysRst,
|
||||
dat_i => wb_ddr_dat_i,
|
||||
dat_o => wb_ddr_dat_o,
|
||||
ack_o => wb_ddr_ack_o,
|
||||
adr_i => wb_ddr_adr_i,
|
||||
cyc_i => wb_ddr_cyc_i,
|
||||
sel_i => wb_ddr_sel_i,
|
||||
stb_i => wb_ddr_stb_i,
|
||||
we_i => wb_ddr_we_i,
|
||||
cti_i => wb_ddr_cti_i,
|
||||
bte_i => wb_ddr_bte_i
|
||||
);
|
||||
|
||||
end Mixed;
|
||||
237
src/wb_ddr_ctrl.vhd
Executable file
237
src/wb_ddr_ctrl.vhd
Executable file
@@ -0,0 +1,237 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/02/2012 06:00:40 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
use work.all;
|
||||
|
||||
entity wb_ddr_ctrl is
|
||||
Port (
|
||||
-- DDR2 control
|
||||
ddr2_clock : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0)
|
||||
);
|
||||
end wb_ddr_ctrl;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl is
|
||||
component wb_ddr_ctrl_ddrwrap is
|
||||
Port (
|
||||
-- DDR2 control
|
||||
ddr2_clock_in : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- DDR2 ctrl to system
|
||||
ctrl_input_data : in std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : in std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : out std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : out std_logic;
|
||||
ctrl_input_address : in std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : in std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : in std_logic;
|
||||
ctrl_auto_ref_req : out std_logic;
|
||||
ctrl_cmd_ack : out std_logic;
|
||||
ctrl_init_done : out std_logic;
|
||||
ctrl_ar_done : out std_logic;
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
|
||||
-- Clock out
|
||||
ddr2_clk0 : out std_ulogic;
|
||||
ddr2_clk90 : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component wb_ddr_ctrl_wb is
|
||||
Port (
|
||||
-- Control signals
|
||||
ddr2_clk0 : in std_ulogic;
|
||||
ddr2_clk90 : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- to DDR2 controller
|
||||
ctrl_input_data : out std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : out std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : in std_logic;
|
||||
ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : out std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : out std_logic;
|
||||
ctrl_auto_ref_req : in std_logic;
|
||||
ctrl_cmd_ack : in std_logic;
|
||||
ctrl_init_done : in std_logic;
|
||||
ctrl_ar_done : in std_logic;
|
||||
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal ddr2_clk0, ddr2_clk90 : std_ulogic;
|
||||
signal ctrl_input_data : std_logic_vector(31 downto 0);
|
||||
signal ctrl_data_mask : std_logic_vector(3 downto 0);
|
||||
signal ctrl_output_data : std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
signal ctrl_data_valid : std_logic;
|
||||
signal ctrl_input_address : std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
signal ctrl_command_register : std_logic_vector(2 downto 0);
|
||||
signal ctrl_burst_done, ctrl_auto_ref_req, ctrl_cmd_ack, ctrl_init_done, ctrl_ar_done : std_logic;
|
||||
|
||||
begin
|
||||
ddr_0 : wb_ddr_ctrl_ddrwrap
|
||||
port map (
|
||||
ddr2_clock_in => ddr2_clock,
|
||||
ddr2_reset => ddr2_reset,
|
||||
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
|
||||
ddr2_clk0 => ddr2_clk0,
|
||||
ddr2_clk90 => ddr2_clk90,
|
||||
|
||||
ctrl_input_data => ctrl_input_data,
|
||||
ctrl_data_mask => ctrl_data_mask,
|
||||
ctrl_output_data => ctrl_output_data,
|
||||
ctrl_data_valid => ctrl_data_valid,
|
||||
ctrl_input_address => ctrl_input_address,
|
||||
ctrl_command_register => ctrl_command_register,
|
||||
ctrl_burst_done => ctrl_burst_done,
|
||||
ctrl_auto_ref_req => ctrl_auto_ref_req,
|
||||
ctrl_cmd_ack => ctrl_cmd_ack,
|
||||
ctrl_init_done => ctrl_init_done,
|
||||
ctrl_ar_done => ctrl_ar_done
|
||||
);
|
||||
|
||||
wb_0 : wb_ddr_ctrl_wb
|
||||
port map (
|
||||
clk_i => clk_i,
|
||||
rst_i => rst_i,
|
||||
|
||||
ddr2_clk0 => ddr2_clk0,
|
||||
ddr2_clk90 => ddr2_clk90,
|
||||
ddr2_reset => ddr2_reset,
|
||||
|
||||
ctrl_input_data => ctrl_input_data,
|
||||
ctrl_data_mask => ctrl_data_mask,
|
||||
ctrl_output_data => ctrl_output_data,
|
||||
ctrl_data_valid => ctrl_data_valid,
|
||||
ctrl_input_address => ctrl_input_address,
|
||||
ctrl_command_register => ctrl_command_register,
|
||||
ctrl_burst_done => ctrl_burst_done,
|
||||
ctrl_auto_ref_req => ctrl_auto_ref_req,
|
||||
ctrl_cmd_ack => ctrl_cmd_ack,
|
||||
ctrl_init_done => ctrl_init_done,
|
||||
ctrl_ar_done => ctrl_ar_done,
|
||||
|
||||
dat_i => dat_i,
|
||||
dat_o => dat_o,
|
||||
ack_o => ack_o,
|
||||
adr_i => adr_i,
|
||||
cyc_i => cyc_i,
|
||||
sel_i => sel_i,
|
||||
stb_i => stb_i,
|
||||
we_i => we_i,
|
||||
cti_i => cti_i,
|
||||
bte_i => bte_i
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
236
src/wb_ddr_ctrl_ddrwrap.vhd
Executable file
236
src/wb_ddr_ctrl_ddrwrap.vhd
Executable file
@@ -0,0 +1,236 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/02/2012 06:12:05 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl_ddrwrap - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity wb_ddr_ctrl_ddrwrap is
|
||||
Port (
|
||||
-- DDR2 control
|
||||
ddr2_clock_in : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- DDR2 ctrl to system
|
||||
ctrl_input_data : in std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : in std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : out std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : out std_logic;
|
||||
ctrl_input_address : in std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : in std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : in std_logic;
|
||||
ctrl_auto_ref_req : out std_logic;
|
||||
ctrl_cmd_ack : out std_logic;
|
||||
ctrl_init_done : out std_logic;
|
||||
ctrl_ar_done : out std_logic;
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
|
||||
-- Clock out
|
||||
ddr2_clk0 : out std_ulogic;
|
||||
ddr2_clk90 : out std_ulogic
|
||||
);
|
||||
end wb_ddr_ctrl_ddrwrap;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl_ddrwrap is
|
||||
component vhdl_bl4_infrastructure_top is
|
||||
port(
|
||||
reset_in_n : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_clkb : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
sys_rst_val : out std_logic;
|
||||
sys_rst90_val : out std_logic;
|
||||
clk_int_val : out std_logic;
|
||||
clk90_int_val : out std_logic;
|
||||
sys_rst180_val : out std_logic;
|
||||
wait_200us : out std_logic;
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_top_0 is
|
||||
port(
|
||||
wait_200us : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
|
||||
downto 0) := (others => 'Z');
|
||||
user_data_valid : out std_logic;
|
||||
user_input_address : in std_logic_vector(((ROW_ADDRESS +
|
||||
COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
|
||||
user_command_register : in std_logic_vector(2 downto 0);
|
||||
burst_done : in std_logic;
|
||||
auto_ref_req : out std_logic;
|
||||
user_cmd_ack : out std_logic;
|
||||
init_done : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
:= (others => 'Z');
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
|
||||
clk_int : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
|
||||
end component;
|
||||
|
||||
signal ddr2_rst0, ddr2_rst90, ddr2_rst180 : std_logic;
|
||||
signal ddr2_clk0_int, ddr2_clk90_int : std_logic;
|
||||
signal wait_200us : std_logic;
|
||||
signal delay_sel : std_logic_vector(4 downto 0);
|
||||
begin
|
||||
|
||||
infrastructure_0 : vhdl_bl4_infrastructure_top
|
||||
port map (
|
||||
reset_in_n => ddr2_reset,
|
||||
sys_clk => '0',
|
||||
sys_clkb => '0',
|
||||
sys_clk_in => ddr2_clock_in,
|
||||
delay_sel_val1_val => delay_sel,
|
||||
sys_rst_val => ddr2_rst0,
|
||||
sys_rst90_val => ddr2_rst90,
|
||||
sys_rst180_val => ddr2_rst180,
|
||||
clk_int_val => ddr2_clk0_int,
|
||||
clk90_int_val => ddr2_clk90_int,
|
||||
wait_200us => wait_200us,
|
||||
-- debug signals
|
||||
dbg_phase_cnt => open,
|
||||
dbg_cnt => open,
|
||||
dbg_trans_onedtct => open,
|
||||
dbg_trans_twodtct => open,
|
||||
dbg_enb_trans_two_dtct => open
|
||||
);
|
||||
|
||||
top_0 : vhdl_bl4_top_0
|
||||
port map (
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
|
||||
clk_int => ddr2_clk0_int,
|
||||
clk90_int => ddr2_clk90_int,
|
||||
delay_sel_val => delay_sel,
|
||||
sys_rst => ddr2_rst0,
|
||||
sys_rst90 => ddr2_rst90,
|
||||
sys_rst180 => ddr2_rst180,
|
||||
wait_200us => wait_200us,
|
||||
|
||||
user_input_data => ctrl_input_data,
|
||||
user_data_mask => ctrl_data_mask,
|
||||
user_output_data => ctrl_output_data,
|
||||
user_data_valid => ctrl_data_valid,
|
||||
user_input_address => ctrl_input_address,
|
||||
user_command_register => ctrl_command_register,
|
||||
burst_done => ctrl_burst_done,
|
||||
auto_ref_req => ctrl_auto_ref_req,
|
||||
user_cmd_ack => ctrl_cmd_ack,
|
||||
init_done => ctrl_init_done,
|
||||
ar_done => ctrl_ar_done,
|
||||
|
||||
dbg_delay_sel => open,
|
||||
dbg_rst_calib => open,
|
||||
dbg_controller => open,
|
||||
vio_out_dqs => (others => '0'),
|
||||
vio_out_dqs_en => '0',
|
||||
vio_out_rst_dqs_div => (others => '0'),
|
||||
vio_out_rst_dqs_div_en => '0'
|
||||
);
|
||||
|
||||
ddr2_clk0 <= ddr2_clk0_int;
|
||||
ddr2_clk90 <= ddr2_clk90_int;
|
||||
|
||||
end Behavioral;
|
||||
270
src/wb_ddr_ctrl_wb.vhd
Executable file
270
src/wb_ddr_ctrl_wb.vhd
Executable file
@@ -0,0 +1,270 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/03/2012 10:51:41 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl_wb - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity wb_ddr_ctrl_wb is
|
||||
Port (
|
||||
-- Control signals
|
||||
ddr2_clk0 : in std_ulogic;
|
||||
ddr2_clk90 : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- to DDR2 controller
|
||||
ctrl_input_data : out std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : out std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : in std_logic;
|
||||
ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : out std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : out std_logic;
|
||||
ctrl_auto_ref_req : in std_logic;
|
||||
ctrl_cmd_ack : in std_logic;
|
||||
ctrl_init_done : in std_logic;
|
||||
ctrl_ar_done : in std_logic;
|
||||
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0)
|
||||
);
|
||||
end wb_ddr_ctrl_wb;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl_wb is
|
||||
component wb_ddr_ctrl_wb_from_ddr IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END component;
|
||||
component wb_ddr_ctrl_wb_to_ddr IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(60 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(60 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END component;
|
||||
component wb_ddr_ctrl_wb_sc is
|
||||
Port (
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0);
|
||||
|
||||
-- To/from ddr clock domain
|
||||
ddr_din : out std_ulogic_vector(31 downto 0);
|
||||
ddr_dout : in std_ulogic_vector(31 downto 0);
|
||||
ddr_adr : out std_ulogic_vector(23 downto 0);
|
||||
ddr_we : out std_ulogic;
|
||||
ddr_be : out std_ulogic_vector(3 downto 0);
|
||||
|
||||
fifo_to_ddr_write : out std_ulogic;
|
||||
fifo_from_ddr_read : out std_ulogic;
|
||||
fifo_to_ddr_full : in std_ulogic;
|
||||
fifo_from_ddr_empty : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
component wb_ddr_ctrl_wb_dc is
|
||||
Port (
|
||||
-- Control signals
|
||||
ddr2_clk0 : in std_ulogic;
|
||||
ddr2_clk180 : in std_ulogic;
|
||||
ddr2_clk90 : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- to DDR2 controller
|
||||
ctrl_input_data : out std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : out std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : in std_logic;
|
||||
ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : out std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : out std_logic;
|
||||
ctrl_auto_ref_req : in std_logic;
|
||||
ctrl_cmd_ack : in std_logic;
|
||||
ctrl_init_done : in std_logic;
|
||||
ctrl_ar_done : in std_logic;
|
||||
|
||||
-- To/from system clock domain
|
||||
din : in std_ulogic_vector(31 downto 0);
|
||||
dout : out std_ulogic_vector(31 downto 0);
|
||||
adr : in std_ulogic_vector(23 downto 0);
|
||||
we : in std_ulogic;
|
||||
be : in std_ulogic_vector(3 downto 0);
|
||||
|
||||
fifo_to_sys_write : out std_ulogic;
|
||||
fifo_from_sys_read : out std_ulogic;
|
||||
fifo_to_sys_full : in std_ulogic;
|
||||
fifo_from_sys_empty : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- FIFO control signals
|
||||
signal s2d_fifo_rd, s2d_fifo_wr, d2s_fifo_rd, d2s_fifo_wr : std_ulogic;
|
||||
signal s2d_fifo_empty, s2d_fifo_full, d2s_fifo_empty, d2s_fifo_full : std_ulogic;
|
||||
|
||||
-- FIFO data signals
|
||||
signal s2d_fifo_din : std_ulogic_vector(60 downto 0);
|
||||
signal d2s_fifo_din : std_ulogic_vector(31 downto 0);
|
||||
signal s2d_fifo_dout : std_logic_vector(60 downto 0);
|
||||
signal d2s_fifo_dout : std_logic_vector(31 downto 0);
|
||||
|
||||
signal ddr2_clk180 : std_ulogic;
|
||||
|
||||
begin
|
||||
|
||||
ddr2_clk180 <= not ddr2_clk0;
|
||||
|
||||
system_cd_inst : wb_ddr_ctrl_wb_sc
|
||||
port map (
|
||||
-- Wishbone slave
|
||||
clk_i => clk_i,
|
||||
rst_i => rst_i,
|
||||
dat_i => dat_i,
|
||||
dat_o => dat_o,
|
||||
ack_o => ack_o,
|
||||
adr_i => adr_i,
|
||||
cyc_i => cyc_i,
|
||||
sel_i => sel_i,
|
||||
stb_i => stb_i,
|
||||
we_i => we_i,
|
||||
cti_i => cti_i,
|
||||
bte_i => bte_i,
|
||||
|
||||
-- To/from ddr clock domain
|
||||
ddr_din => s2d_fifo_din(31 downto 0),
|
||||
ddr_dout => std_ulogic_vector(d2s_fifo_dout),
|
||||
ddr_adr => s2d_fifo_din(55 downto 32),
|
||||
ddr_we => s2d_fifo_din(56),
|
||||
ddr_be => s2d_fifo_din(60 downto 57),
|
||||
|
||||
fifo_to_ddr_write => s2d_fifo_wr,
|
||||
fifo_from_ddr_read => d2s_fifo_rd,
|
||||
fifo_to_ddr_full => s2d_fifo_full,
|
||||
fifo_from_ddr_empty => d2s_fifo_empty
|
||||
);
|
||||
|
||||
s2d_fifo : wb_ddr_ctrl_wb_to_ddr
|
||||
port map (
|
||||
rst => rst_i,
|
||||
wr_clk => clk_i,
|
||||
rd_clk => ddr2_clk180,
|
||||
wr_en => s2d_fifo_wr,
|
||||
rd_en => s2d_fifo_rd,
|
||||
full => s2d_fifo_full,
|
||||
empty => s2d_fifo_empty,
|
||||
|
||||
din => std_logic_vector(s2d_fifo_din),
|
||||
|
||||
dout => s2d_fifo_dout
|
||||
);
|
||||
|
||||
d2s_fifo : wb_ddr_ctrl_wb_from_ddr
|
||||
port map (
|
||||
rst => rst_i,
|
||||
wr_clk => ddr2_clk90,
|
||||
rd_clk => clk_i,
|
||||
wr_en => d2s_fifo_wr,
|
||||
rd_en => d2s_fifo_rd,
|
||||
full => d2s_fifo_full,
|
||||
empty => d2s_fifo_empty,
|
||||
|
||||
din => std_logic_vector(d2s_fifo_din),
|
||||
|
||||
dout => d2s_fifo_dout
|
||||
);
|
||||
|
||||
ddr_cd_inst : wb_ddr_ctrl_wb_dc
|
||||
port map (
|
||||
-- Control signals
|
||||
ddr2_clk0 => ddr2_clk0,
|
||||
ddr2_clk180 => ddr2_clk180,
|
||||
ddr2_clk90 => ddr2_clk90,
|
||||
ddr2_reset => ddr2_reset,
|
||||
|
||||
-- to DDR2 controller
|
||||
ctrl_input_data => ctrl_input_data,
|
||||
ctrl_data_mask => ctrl_data_mask,
|
||||
ctrl_output_data => ctrl_output_data,
|
||||
ctrl_data_valid => ctrl_data_valid,
|
||||
ctrl_input_address => ctrl_input_address,
|
||||
ctrl_command_register => ctrl_command_register,
|
||||
ctrl_burst_done => ctrl_burst_done,
|
||||
ctrl_auto_ref_req => ctrl_auto_ref_req,
|
||||
ctrl_cmd_ack => ctrl_cmd_ack,
|
||||
ctrl_init_done => ctrl_init_done,
|
||||
ctrl_ar_done => ctrl_ar_done,
|
||||
|
||||
-- To/from system clock domain
|
||||
din => std_ulogic_vector(s2d_fifo_dout(31 downto 0)),
|
||||
dout => d2s_fifo_din,
|
||||
adr => std_ulogic_vector(s2d_fifo_dout(55 downto 32)),
|
||||
we => s2d_fifo_dout(56),
|
||||
be => std_ulogic_vector(s2d_fifo_dout(60 downto 57)),
|
||||
|
||||
fifo_to_sys_write => d2s_fifo_wr,
|
||||
fifo_from_sys_read => s2d_fifo_rd,
|
||||
fifo_to_sys_full => d2s_fifo_full,
|
||||
fifo_from_sys_empty => s2d_fifo_empty
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
258
src/wb_ddr_ctrl_wb_dc.vhd
Executable file
258
src/wb_ddr_ctrl_wb_dc.vhd
Executable file
@@ -0,0 +1,258 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/06/2012 03:04:35 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl_wb_dc - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity wb_ddr_ctrl_wb_dc is
|
||||
Port (
|
||||
-- Control signals
|
||||
ddr2_clk0 : in std_ulogic;
|
||||
ddr2_clk180 : in std_ulogic;
|
||||
ddr2_clk90 : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- to DDR2 controller
|
||||
ctrl_input_data : out std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : out std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : in std_logic;
|
||||
ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : out std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : out std_logic;
|
||||
ctrl_auto_ref_req : in std_logic;
|
||||
ctrl_cmd_ack : in std_logic;
|
||||
ctrl_init_done : in std_logic;
|
||||
ctrl_ar_done : in std_logic;
|
||||
|
||||
-- To/from system clock domain
|
||||
din : in std_ulogic_vector(31 downto 0);
|
||||
dout : out std_ulogic_vector(31 downto 0);
|
||||
adr : in std_ulogic_vector(23 downto 0);
|
||||
we : in std_ulogic;
|
||||
be : in std_ulogic_vector(3 downto 0);
|
||||
|
||||
fifo_to_sys_write : out std_ulogic;
|
||||
fifo_from_sys_read : out std_ulogic;
|
||||
fifo_to_sys_full : in std_ulogic;
|
||||
fifo_from_sys_empty : in std_ulogic
|
||||
);
|
||||
end wb_ddr_ctrl_wb_dc;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl_wb_dc is
|
||||
|
||||
-- DDR2 Controller commands
|
||||
constant ctrl_command_nop : std_logic_vector(2 downto 0) := "000";
|
||||
constant ctrl_command_initialize : std_logic_vector(2 downto 0) := "010";
|
||||
constant ctrl_command_write : std_logic_vector(2 downto 0) := "100";
|
||||
constant ctrl_command_read : std_logic_vector(2 downto 0) := "110";
|
||||
|
||||
-- DDR-side FSM
|
||||
type ctrl_states is (S_RESET, S_INITIALIZE, S_WAITINITDONE, S_IDLE, S_REFRESH, S_REQUEST_INIT, S_WRITE1,
|
||||
S_WRITE2, S_WRITE3, S_WRITE4, S_WRITE_END1, S_WRITE_END2, S_READ1, S_READ2,
|
||||
S_READ3, S_READ4, S_READ5, S_READ_END1, S_READ_END2);
|
||||
signal ctrl_state : ctrl_states := S_RESET;
|
||||
signal burst_start_adr : std_ulogic_vector(12 downto 0);
|
||||
|
||||
-- fifo_pending is '1' when a valid, unprocessed request is on the fifo outputs
|
||||
-- the idle state does not cause a fifo read if fifo_pending is '1'
|
||||
signal fifo_from_sys_read_int, fifo_from_sys_valid, fifo_pending : std_ulogic;
|
||||
|
||||
signal ddr_address : std_ulogic_vector(23 downto 0);
|
||||
signal ddr_dout : std_ulogic_vector(31 downto 0);
|
||||
signal ddr_dmask : std_ulogic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- remap address for ddr controller (so column is lowest)
|
||||
ctrl_input_address <= std_logic_vector(ddr_address(21 downto 9) & ddr_address(8 downto 0) & '0' & ddr_address(23 downto 22));
|
||||
|
||||
-- input FIFO control
|
||||
fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or
|
||||
(ctrl_state = S_REQUEST_INIT and we = '1') or
|
||||
(ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or
|
||||
(ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
|
||||
we = '0' or ctrl_auto_ref_req = '1')) or
|
||||
(ctrl_state = S_WRITE4) or
|
||||
(ctrl_state = S_READ2 or ctrl_state = S_READ3) or
|
||||
(ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
|
||||
we = '1' or ctrl_auto_ref_req = '1')) or
|
||||
(ctrl_state = S_READ5)
|
||||
) and fifo_from_sys_empty = '0' else
|
||||
'0';
|
||||
is_fifo_from_sys_valid : process(ddr2_clk0)
|
||||
begin
|
||||
if rising_edge(ddr2_clk0) then
|
||||
fifo_from_sys_valid <= fifo_from_sys_read_int;
|
||||
end if;
|
||||
end process is_fifo_from_sys_valid;
|
||||
|
||||
fifo_from_sys_read <= fifo_from_sys_read_int;
|
||||
|
||||
-- resync data to ddr to ddr2_clk90
|
||||
ddr_dout_resync : process(ddr2_clk90)
|
||||
begin
|
||||
if rising_edge(ddr2_clk90) then
|
||||
ctrl_input_data <= std_logic_vector(ddr_dout);
|
||||
ctrl_data_mask <= std_logic_vector(ddr_dmask);
|
||||
end if;
|
||||
end process ddr_dout_resync;
|
||||
|
||||
-- move data from ddr to fifo
|
||||
dout <= std_ulogic_vector(ctrl_output_data);
|
||||
fifo_to_sys_write <= ctrl_data_valid;
|
||||
|
||||
ctrl_fsm : process(ddr2_clk180)
|
||||
begin
|
||||
if rising_edge(ddr2_clk180) then
|
||||
if ddr2_reset = '0' then
|
||||
ctrl_state <= S_RESET;
|
||||
ddr_dout <= (others => '-');
|
||||
ddr_dmask <= (others => '0');
|
||||
ddr_address <= (others => '-');
|
||||
ctrl_burst_done <= '0';
|
||||
ctrl_command_register <= ctrl_command_nop;
|
||||
|
||||
fifo_pending <= '0';
|
||||
else
|
||||
ctrl_command_register <= ctrl_command_nop;
|
||||
ctrl_burst_done <= '0';
|
||||
|
||||
case ctrl_state is
|
||||
when S_RESET =>
|
||||
ctrl_state <= S_INITIALIZE;
|
||||
when S_INITIALIZE =>
|
||||
ctrl_command_register <= ctrl_command_initialize;
|
||||
ctrl_state <= S_WAITINITDONE;
|
||||
when S_WAITINITDONE =>
|
||||
if ctrl_init_done = '1' then
|
||||
ctrl_state <= S_IDLE;
|
||||
end if;
|
||||
when S_IDLE =>
|
||||
if ctrl_auto_ref_req = '1' then -- DDR controller requests refresh
|
||||
ctrl_state <= S_REFRESH;
|
||||
elsif fifo_from_sys_valid = '1' then -- A request from the system is pending
|
||||
ctrl_state <= S_REQUEST_INIT;
|
||||
end if; -- else do nothing
|
||||
when S_REFRESH =>
|
||||
if ctrl_ar_done = '1' then
|
||||
ctrl_state <= S_IDLE;
|
||||
end if;
|
||||
when S_REQUEST_INIT =>
|
||||
if we = '1' then
|
||||
ctrl_command_register <= ctrl_command_write;
|
||||
ctrl_state <= S_WRITE1;
|
||||
ddr_dout <= din;
|
||||
ddr_dmask <= be;
|
||||
else
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
ctrl_state <= S_READ1;
|
||||
end if;
|
||||
burst_start_adr <= adr(21 downto 9);
|
||||
ddr_address <= adr;
|
||||
|
||||
when S_WRITE1 =>
|
||||
ctrl_command_register <= ctrl_command_write;
|
||||
if ctrl_cmd_ack = '1' then
|
||||
ddr_dout <= din;
|
||||
ddr_dmask <= be;
|
||||
ctrl_state <= S_WRITE2;
|
||||
end if;
|
||||
when S_WRITE2 =>
|
||||
ctrl_command_register <= ctrl_command_write;
|
||||
if fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
|
||||
we = '0' or ctrl_auto_ref_req = '1' then
|
||||
-- next request incompatible with burst type, or auto refresh requested
|
||||
ctrl_burst_done <= '1';
|
||||
fifo_pending <= fifo_from_sys_valid;
|
||||
ctrl_state <= S_WRITE_END1;
|
||||
else
|
||||
ddr_dout <= din;
|
||||
ddr_dmask <= be;
|
||||
ctrl_state <= S_WRITE3;
|
||||
end if;
|
||||
when S_WRITE3 =>
|
||||
ctrl_command_register <= ctrl_command_write;
|
||||
ddr_dout <= din;
|
||||
ddr_dmask <= be;
|
||||
ddr_address <= adr;
|
||||
ctrl_state <= S_WRITE4;
|
||||
when S_WRITE4 =>
|
||||
ctrl_command_register <= ctrl_command_write;
|
||||
ctrl_state <= S_WRITE2;
|
||||
|
||||
when S_WRITE_END1 =>
|
||||
ctrl_burst_done <= '1';
|
||||
ctrl_state <= S_WRITE_END2;
|
||||
when S_WRITE_END2 =>
|
||||
if ctrl_cmd_ack = '0' then
|
||||
ctrl_state <= S_IDLE;
|
||||
end if;
|
||||
|
||||
when S_READ1 =>
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
if ctrl_cmd_ack = '1' then
|
||||
ctrl_state <= S_READ2;
|
||||
end if;
|
||||
when S_READ2 =>
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
ctrl_state <= S_READ3;
|
||||
when S_READ3 =>
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
ctrl_state <= S_READ4;
|
||||
when S_READ4 =>
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
if fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
|
||||
we = '1' or ctrl_auto_ref_req = '1' then
|
||||
-- next request incompatible with burst type, or auto refresh requested
|
||||
fifo_pending <= fifo_from_sys_valid;
|
||||
ctrl_burst_done <= '1';
|
||||
ctrl_state <= S_READ_END1;
|
||||
else
|
||||
ddr_address <= adr;
|
||||
ctrl_state <= S_READ5;
|
||||
end if;
|
||||
when S_READ5 =>
|
||||
ctrl_command_register <= ctrl_command_read;
|
||||
ctrl_state <= S_READ4;
|
||||
|
||||
when S_READ_END1 =>
|
||||
ctrl_burst_done <= '1';
|
||||
ctrl_state <= S_READ_END2;
|
||||
when S_READ_END2 =>
|
||||
if ctrl_cmd_ack = '0' then
|
||||
ctrl_state <= S_IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process ctrl_fsm;
|
||||
|
||||
end Behavioral;
|
||||
166
src/wb_ddr_ctrl_wb_sc.vhd
Executable file
166
src/wb_ddr_ctrl_wb_sc.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/06/2012 03:04:35 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl_wb_sc - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description: Memory controller - system clock domain
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity wb_ddr_ctrl_wb_sc is
|
||||
Port (
|
||||
-- Wishbone slave
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0);
|
||||
|
||||
-- To/from ddr clock domain
|
||||
ddr_din : out std_ulogic_vector(31 downto 0);
|
||||
ddr_dout : in std_ulogic_vector(31 downto 0);
|
||||
ddr_adr : out std_ulogic_vector(23 downto 0);
|
||||
ddr_we : out std_ulogic;
|
||||
ddr_be : out std_ulogic_vector(3 downto 0);
|
||||
|
||||
fifo_to_ddr_write : out std_ulogic;
|
||||
fifo_from_ddr_read : out std_ulogic;
|
||||
fifo_to_ddr_full : in std_ulogic;
|
||||
fifo_from_ddr_empty : in std_ulogic
|
||||
);
|
||||
end wb_ddr_ctrl_wb_sc;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl_wb_sc is
|
||||
type states is (S_IDLE, S_WRITE_CLASSIC1, S_READ_CLASSIC1, S_READ_CLASSIC2, S_READ_CLASSIC3);
|
||||
signal state : states := S_IDLE;
|
||||
|
||||
signal fifo_from_ddr_read_int, fifo_from_ddr_valid : std_ulogic;
|
||||
begin
|
||||
|
||||
fifo_from_ddr_read_int <= '1' when (((state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or
|
||||
(state = S_READ_CLASSIC2) or
|
||||
(state = S_READ_CLASSIC3 and fifo_from_ddr_valid = '0')
|
||||
) and fifo_from_ddr_empty = '0') or rst_i = '1' else
|
||||
'0';
|
||||
|
||||
is_fifo_from_ddr_valid : process(clk_i)
|
||||
begin
|
||||
if falling_edge(clk_i) then
|
||||
fifo_from_ddr_valid <= fifo_from_ddr_read_int;
|
||||
end if;
|
||||
end process is_fifo_from_ddr_valid;
|
||||
|
||||
fifo_from_ddr_read <= fifo_from_ddr_read_int;
|
||||
|
||||
wb_slave : process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
if rst_i = '1' then
|
||||
ddr_din <= (others => '-');
|
||||
ddr_adr <= (others => '-');
|
||||
ddr_we <= '-';
|
||||
ddr_be <= (others => '-');
|
||||
fifo_to_ddr_write <= '0';
|
||||
state <= S_IDLE;
|
||||
else
|
||||
ddr_din <= (others => '-');
|
||||
ddr_adr <= (others => '-');
|
||||
ddr_we <= '-';
|
||||
ddr_be <= (others => '-');
|
||||
fifo_to_ddr_write <= '0';
|
||||
case state is
|
||||
when S_IDLE =>
|
||||
if stb_i = '1' then
|
||||
if we_i = '1' then
|
||||
if cti_i = "010" then -- incrementing burst
|
||||
null;
|
||||
else -- classic cycle or unsupported
|
||||
if fifo_to_ddr_full = '0' then
|
||||
ddr_din <= dat_i;
|
||||
ddr_adr <= adr_i;
|
||||
ddr_we <= '1';
|
||||
ddr_be <= sel_i;
|
||||
fifo_to_ddr_write <= '1';
|
||||
state <= S_WRITE_CLASSIC1;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
if cti_i = "010" then -- incrementing burst
|
||||
null;
|
||||
else -- classic cycle or unsupported
|
||||
if fifo_to_ddr_full = '0' then
|
||||
ddr_adr <= adr_i;
|
||||
ddr_we <= '0';
|
||||
fifo_to_ddr_write <= '1';
|
||||
state <= S_READ_CLASSIC1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when S_WRITE_CLASSIC1 =>
|
||||
if fifo_to_ddr_full = '0' then
|
||||
ddr_din <= (others => '-');
|
||||
ddr_adr <= adr_i;
|
||||
ddr_we <= '1';
|
||||
ddr_be <= (others => '0');
|
||||
fifo_to_ddr_write <= '1';
|
||||
|
||||
ack_o <= '1';
|
||||
state <= S_IDLE;
|
||||
end if;
|
||||
|
||||
when S_READ_CLASSIC1 =>
|
||||
if fifo_to_ddr_full = '0' then
|
||||
ddr_adr <= adr_i;
|
||||
ddr_we <= '0';
|
||||
fifo_to_ddr_write <= '1';
|
||||
state <= S_READ_CLASSIC2;
|
||||
end if;
|
||||
when S_READ_CLASSIC2 =>
|
||||
if fifo_from_ddr_valid = '1' then
|
||||
dat_o <= ddr_dout;
|
||||
state <= S_READ_CLASSIC3;
|
||||
end if;
|
||||
when S_READ_CLASSIC3 =>
|
||||
if fifo_from_ddr_valid = '1' then
|
||||
ack_o <= '1';
|
||||
state <= S_IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process wb_slave;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
206
tb/wb_ddr_ctrl_tb.vhd
Executable file
206
tb/wb_ddr_ctrl_tb.vhd
Executable file
@@ -0,0 +1,206 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : Testbench for design "wb_ddr_ctrl"
|
||||
-- Project :
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : wb_ddr_ctrl_tb.vhd
|
||||
-- Author : Matthias Blankertz <matthias@blankertz.org>
|
||||
-- Company :
|
||||
-- Created : 2013-02-26
|
||||
-- Last update: 2013-02-26
|
||||
-- Platform :
|
||||
-- Standard : VHDL'93
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2013
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2013-02-26 1.0 Matthias Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
entity wb_ddr_ctrl_tb is
|
||||
|
||||
end wb_ddr_ctrl_tb;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
architecture testbench of wb_ddr_ctrl_tb is
|
||||
|
||||
component wb_ddr_ctrl
|
||||
port (
|
||||
ddr2_clock : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
clk_i : in std_ulogic;
|
||||
rst_i : in std_ulogic;
|
||||
dat_i : in std_ulogic_vector(31 downto 0);
|
||||
dat_o : out std_ulogic_vector(31 downto 0);
|
||||
ack_o : out std_ulogic;
|
||||
adr_i : in std_ulogic_vector(25 downto 2);
|
||||
cyc_i : in std_ulogic;
|
||||
sel_i : in std_ulogic_vector(3 downto 0);
|
||||
stb_i : in std_ulogic;
|
||||
we_i : in std_ulogic;
|
||||
cti_i : in std_ulogic_vector(2 downto 0);
|
||||
bte_i : in std_ulogic_vector(1 downto 0));
|
||||
end component;
|
||||
|
||||
component ddr2_model
|
||||
port (
|
||||
ck : in std_logic;
|
||||
ck_n : in std_logic;
|
||||
cke : in std_logic;
|
||||
cs_n : in std_logic;
|
||||
ras_n : in std_logic;
|
||||
cas_n : in std_logic;
|
||||
we_n : in std_logic;
|
||||
dm_rdqs : inout std_logic_vector(1 downto 0);
|
||||
ba : in std_logic_vector(1 downto 0);
|
||||
addr : in std_logic_vector(12 downto 0);
|
||||
dq : inout std_logic_vector(15 downto 0);
|
||||
dqs : inout std_logic_vector(1 downto 0);
|
||||
dqs_n : inout std_logic_vector(1 downto 0);
|
||||
rdqs_n : out std_logic_vector(1 downto 0);
|
||||
odt : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- component ports
|
||||
signal ddr2_clock : std_ulogic := '0';
|
||||
signal ddr2_reset : std_ulogic;
|
||||
signal ddr2_dq : std_logic_vector(15 downto 0);
|
||||
signal ddr2_a : std_logic_vector(12 downto 0);
|
||||
signal ddr2_ba : std_logic_vector(1 downto 0);
|
||||
signal ddr2_cke : std_logic;
|
||||
signal ddr2_cs_n : std_logic;
|
||||
signal ddr2_ras_n : std_logic;
|
||||
signal ddr2_cas_n : std_logic;
|
||||
signal ddr2_we_n : std_logic;
|
||||
signal ddr2_odt : std_logic;
|
||||
signal ddr2_dm : std_logic_vector(1 downto 0);
|
||||
signal rst_dqs_div_in : std_logic;
|
||||
signal rst_dqs_div_out : std_logic;
|
||||
signal ddr2_dqs : std_logic_vector(1 downto 0);
|
||||
signal ddr2_dqs_n : std_logic_vector(1 downto 0);
|
||||
signal ddr2_ck : std_logic_vector(0 downto 0);
|
||||
signal ddr2_ck_n : std_logic_vector(0 downto 0);
|
||||
signal clk_i : std_ulogic := '0';
|
||||
signal rst_i : std_ulogic;
|
||||
signal dat_i : std_ulogic_vector(31 downto 0);
|
||||
signal dat_o : std_ulogic_vector(31 downto 0);
|
||||
signal ack_o : std_ulogic;
|
||||
signal adr_i : std_ulogic_vector(25 downto 2);
|
||||
signal cyc_i : std_ulogic;
|
||||
signal sel_i : std_ulogic_vector(3 downto 0);
|
||||
signal stb_i : std_ulogic;
|
||||
signal we_i : std_ulogic;
|
||||
signal cti_i : std_ulogic_vector(2 downto 0);
|
||||
signal bte_i : std_ulogic_vector(1 downto 0);
|
||||
|
||||
begin -- testbench
|
||||
|
||||
-- component instantiation
|
||||
DUT: wb_ddr_ctrl
|
||||
port map (
|
||||
ddr2_clock => ddr2_clock,
|
||||
ddr2_reset => ddr2_reset,
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
clk_i => clk_i,
|
||||
rst_i => rst_i,
|
||||
dat_i => dat_i,
|
||||
dat_o => dat_o,
|
||||
ack_o => ack_o,
|
||||
adr_i => adr_i,
|
||||
cyc_i => cyc_i,
|
||||
sel_i => sel_i,
|
||||
stb_i => stb_i,
|
||||
we_i => we_i,
|
||||
cti_i => cti_i,
|
||||
bte_i => bte_i);
|
||||
|
||||
ddr2_model_inst : ddr2_model port map (
|
||||
ck => ddr2_ck(0),
|
||||
ck_n => ddr2_ck_n(0),
|
||||
cke => ddr2_cke,
|
||||
cs_n => ddr2_cs_n,
|
||||
ras_n => ddr2_ras_n,
|
||||
cas_n => ddr2_cas_n,
|
||||
we_n => ddr2_we_n,
|
||||
dm_rdqs => ddr2_dm,
|
||||
ba => ddr2_ba,
|
||||
addr => ddr2_a,
|
||||
dq => ddr2_dq,
|
||||
dqs => ddr2_dqs,
|
||||
dqs_n => ddr2_dqs_n,
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt);
|
||||
|
||||
|
||||
-- clock generation
|
||||
ddr2_clock <= not ddr2_clock after 3.7594 ns;
|
||||
clk_i <= not clk_i after 10 ns;
|
||||
|
||||
-- waveform generation
|
||||
WaveGen_Proc: process
|
||||
begin
|
||||
-- insert signal assignments here
|
||||
ddr2_reset <= '0';
|
||||
rst_i <= '1';
|
||||
wait for 20 ns;
|
||||
wait until rising_edge(ddr2_clock);
|
||||
ddr2_reset <= '1' after 1 ns;
|
||||
wait until rising_edge(clk_i);
|
||||
rst_i <= '0' after 2 ns;
|
||||
|
||||
wait;
|
||||
end process WaveGen_Proc;
|
||||
|
||||
|
||||
|
||||
end testbench;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
configuration wb_ddr_ctrl_tb_testbench_cfg of wb_ddr_ctrl_tb is
|
||||
for testbench
|
||||
end for;
|
||||
end wb_ddr_ctrl_tb_testbench_cfg;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
Reference in New Issue
Block a user