matthias/2d_display_engine-new
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

- Seperated control and data path in wb_ddr_ctrl_wb_dc

Browse Source 
- Debugging wb_ddr_ctrl
This commit is contained in:
Matthias Blankertz
2013-02-28 15:54:48 +01:00
parent 70aaa51615
commit 56930a80c3
6 changed files with 854 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

419
Default.wcfg Executable file
View File

@@ -0,0 +1,419 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vhdl_bl4_parameters_0" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vl_types" />
<top_module name="vpkg" />
<top_module name="wb_ddr_ctrl_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="3" />
<wvobject fp_name="group31" type="group">
<obj_property name="label">toplevel</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clock</obj_property>
<obj_property name="ObjectShortName">ddr2_clock</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_a[12:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_a[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ba" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ba[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ba[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cke" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cke</obj_property>
<obj_property name="ObjectShortName">ddr2_cke</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cs_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cs_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cs_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ras_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ras_n</obj_property>
<obj_property name="ObjectShortName">ddr2_ras_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cas_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cas_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cas_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_we_n</obj_property>
<obj_property name="ObjectShortName">ddr2_we_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_odt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_odt</obj_property>
<obj_property name="ObjectShortName">ddr2_odt</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dm" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dm[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_in</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_in</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_out</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_out</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs_n[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck_n[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck_n[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group32" type="group">
<obj_property name="label">ddr_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk0</obj_property>
<obj_property name="ObjectShortName">ddr2_clk0</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk180" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk180</obj_property>
<obj_property name="ObjectShortName">ddr2_clk180</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk90" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk90</obj_property>
<obj_property name="ObjectShortName">ddr2_clk90</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_mask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_mask[3:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_data_mask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_output_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_valid</obj_property>
<obj_property name="ObjectShortName">ctrl_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_auto_ref_req" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_auto_ref_req</obj_property>
<obj_property name="ObjectShortName">ctrl_auto_ref_req</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_cmd_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_cmd_ack</obj_property>
<obj_property name="ObjectShortName">ctrl_cmd_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_init_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_init_done</obj_property>
<obj_property name="ObjectShortName">ctrl_init_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_ar_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_ar_done</obj_property>
<obj_property name="ObjectShortName">ctrl_ar_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">din[31:0]</obj_property>
<obj_property name="ObjectShortName">din[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout[31:0]</obj_property>
<obj_property name="ObjectShortName">dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr[23:0]</obj_property>
<obj_property name="ObjectShortName">adr[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">be[3:0]</obj_property>
<obj_property name="ObjectShortName">be[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address[23:0]</obj_property>
<obj_property name="ObjectShortName">ddr_address[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address_en</obj_property>
<obj_property name="ObjectShortName">ddr_address_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_en</obj_property>
<obj_property name="ObjectShortName">ddr_dout_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dmask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_rst</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_rst</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_en</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register_d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register_d[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register_d[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done_d" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done_d</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done_d</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/ctrl_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_state</obj_property>
<obj_property name="ObjectShortName">ctrl_state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
<obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_pending</obj_property>
<obj_property name="ObjectShortName">fifo_pending</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_valid</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group33" type="group">
<obj_property name="label">system_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[23:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_valid</obj_property>
</wvobject>
</wvobject>
</wave_config>

4
Makefile
View File

@@ -26,8 +26,8 @@ ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
src/toplevel.vhd src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc.vhd src/wb_ddr_ctrl_wb_sc.vhd \
src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
src/wb_ddr_ctrl_wb_sc.vhd
SYN_INFILES=
PSMFILES=
CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr

267
src/wb_ddr_ctrl_wb_dc.vhd
View File

@@ -68,54 +68,99 @@ end wb_ddr_ctrl_wb_dc;
architecture Behavioral of wb_ddr_ctrl_wb_dc is
-- DDR2 Controller commands
constant ctrl_command_nop : std_logic_vector(2 downto 0) := "000";
constant ctrl_command_initialize : std_logic_vector(2 downto 0) := "010";
constant ctrl_command_write : std_logic_vector(2 downto 0) := "100";
constant ctrl_command_read : std_logic_vector(2 downto 0) := "110";
component wb_ddr_ctrl_wb_dc_fsm
port (
ddr2_clk0 : in std_ulogic;
ddr2_clk180 : in std_ulogic;
ddr2_reset : in std_ulogic;
ctrl_data_valid : in std_logic;
ctrl_auto_ref_req : in std_logic;
ctrl_cmd_ack : in std_logic;
ctrl_init_done : in std_logic;
ctrl_ar_done : in std_logic;
fifo_from_sys_empty : in std_ulogic;
we : in std_ulogic;
row_addr : in std_ulogic_vector(12 downto 0);
ddr_address_en : out std_ulogic;
ddr_dout_en : out std_ulogic;
ddr_dmask_rst : out std_ulogic;
ddr_dmask_en : out std_ulogic;
ctrl_command_register_d : out std_logic_vector(2 downto 0);
ctrl_burst_done_d : out std_ulogic;
fifo_from_sys_read : out std_ulogic);
end component;
signal ddr_address : std_ulogic_vector(23 downto 0) := (others => '-');
signal ddr_address_en : std_ulogic := '0';
-- DDR-side FSM
type ctrl_states is (S_RESET, S_INITIALIZE, S_WAITINITDONE, S_IDLE, S_REFRESH, S_REQUEST_INIT, S_WRITE1,
S_WRITE2, S_WRITE3, S_WRITE4, S_WRITE_END1, S_WRITE_END2, S_READ1, S_READ2,
S_READ3, S_READ4, S_READ5, S_READ_END1, S_READ_END2);
signal ctrl_state : ctrl_states := S_RESET;
signal burst_start_adr : std_ulogic_vector(12 downto 0);
signal ddr_dout : std_ulogic_vector(31 downto 0) := (others => '-');
signal ddr_dout_en : std_ulogic := '0';
-- fifo_pending is '1' when a valid, unprocessed request is on the fifo outputs
-- the idle state does not cause a fifo read if fifo_pending is '1'
signal fifo_from_sys_read_int, fifo_from_sys_valid, fifo_pending : std_ulogic;
signal ddr_dmask : std_ulogic_vector(3 downto 0) := (others => '0');
signal ddr_dmask_rst, ddr_dmask_en : std_ulogic := '0';
signal ddr_address : std_ulogic_vector(23 downto 0);
signal ddr_dout : std_ulogic_vector(31 downto 0);
signal ddr_dmask : std_ulogic_vector(3 downto 0);
signal ctrl_command_register_d : std_logic_vector(2 downto 0) := "000";
signal ctrl_burst_done_d : std_ulogic := '0';
begin
wb_ddr_ctrl_wb_dc_fsm_inst: wb_ddr_ctrl_wb_dc_fsm
port map (
ddr2_clk0 => ddr2_clk0,
ddr2_clk180 => ddr2_clk180,
ddr2_reset => ddr2_reset,
ctrl_data_valid => ctrl_data_valid,
ctrl_auto_ref_req => ctrl_auto_ref_req,
ctrl_cmd_ack => ctrl_cmd_ack,
ctrl_init_done => ctrl_init_done,
ctrl_ar_done => ctrl_ar_done,
fifo_from_sys_empty => fifo_from_sys_empty,
we => we,
row_addr => adr(21 downto 9),
ddr_address_en => ddr_address_en,
ddr_dout_en => ddr_dout_en,
ddr_dmask_rst => ddr_dmask_rst,
ddr_dmask_en => ddr_dmask_en,
ctrl_command_register_d => ctrl_command_register_d,
ctrl_burst_done_d => ctrl_burst_done_d,
fifo_from_sys_read => fifo_from_sys_read
);
-- ddr_address register
ddr_address_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr_address_en = '1' then
ddr_address <= adr;
end if;
end if;
end process ddr_address_reg;
-- remap address for ddr controller (so column is lowest)
ctrl_input_address <= std_logic_vector(ddr_address(21 downto 9) & ddr_address(8 downto 0) & '0' & ddr_address(23 downto 22));
-- input FIFO control
fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or
(ctrl_state = S_REQUEST_INIT and we = '1') or
(ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or
(ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_WRITE4) or
(ctrl_state = S_READ2 or ctrl_state = S_READ3) or
(ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_READ5)
) and fifo_from_sys_empty = '0' else
'0';
is_fifo_from_sys_valid : process(ddr2_clk0)
begin
if rising_edge(ddr2_clk0) then
fifo_from_sys_valid <= fifo_from_sys_read_int;
end if;
end process is_fifo_from_sys_valid;
fifo_from_sys_read <= fifo_from_sys_read_int;
-- ddr_dout register
ddr_dout_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr_dout_en = '1' then
ddr_dout <= din;
end if;
end if;
end process ddr_dout_reg;
-- ddr_dmask register
ddr_dmask_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr_dmask_rst = '1' or ddr2_reset = '1' then
ddr_dmask <= (others => '0');
elsif ddr_dmask_en = '1' then
ddr_dmask <= be;
end if;
end if;
end process ddr_dmask_reg;
-- resync data to ddr to ddr2_clk90
ddr_dout_resync : process(ddr2_clk90)
begin
@@ -125,134 +170,24 @@ ddr_dout_resync : process(ddr2_clk90)
end if;
end process ddr_dout_resync;
-- ctrl_command_register register
ctrl_command_register_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
ctrl_command_register <= ctrl_command_register_d;
end if;
end process ctrl_command_register_reg;
-- ctrl_burst_done register
ctrl_burst_done_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
ctrl_burst_done <= ctrl_burst_done_d;
end if;
end process ctrl_burst_done_reg;
-- move data from ddr to fifo
dout <= std_ulogic_vector(ctrl_output_data);
fifo_to_sys_write <= ctrl_data_valid and not ddr2_reset;
ctrl_fsm : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr2_reset = '1' then
ctrl_state <= S_RESET;
ddr_dout <= (others => '-');
ddr_dmask <= (others => '0');
ddr_address <= (others => '-');
ctrl_burst_done <= '0';
ctrl_command_register <= ctrl_command_nop;
fifo_pending <= '0';
else
ctrl_command_register <= ctrl_command_nop;
ctrl_burst_done <= '0';
case ctrl_state is
when S_RESET =>
ctrl_state <= S_INITIALIZE;
when S_INITIALIZE =>
ctrl_command_register <= ctrl_command_initialize;
ctrl_state <= S_WAITINITDONE;
when S_WAITINITDONE =>
if ctrl_init_done = '1' then
ctrl_state <= S_IDLE;
end if;
when S_IDLE =>
if ctrl_auto_ref_req = '1' then -- DDR controller requests refresh
ctrl_state <= S_REFRESH;
elsif fifo_from_sys_valid = '1' then -- A request from the system is pending
ctrl_state <= S_REQUEST_INIT;
end if; -- else do nothing
when S_REFRESH =>
if ctrl_ar_done = '1' then
ctrl_state <= S_IDLE;
end if;
when S_REQUEST_INIT =>
if we = '1' then
ctrl_command_register <= ctrl_command_write;
ctrl_state <= S_WRITE1;
ddr_dout <= din;
ddr_dmask <= be;
else
ctrl_command_register <= ctrl_command_read;
ctrl_state <= S_READ1;
end if;
burst_start_adr <= adr(21 downto 9);
ddr_address <= adr;
when S_WRITE1 =>
ctrl_command_register <= ctrl_command_write;
if ctrl_cmd_ack = '1' then
ddr_dout <= din;
ddr_dmask <= be;
ctrl_state <= S_WRITE2;
end if;
when S_WRITE2 =>
ctrl_command_register <= ctrl_command_write;
if fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
ctrl_burst_done <= '1';
fifo_pending <= fifo_from_sys_valid;
ctrl_state <= S_WRITE_END1;
else
ddr_dout <= din;
ddr_dmask <= be;
ctrl_state <= S_WRITE3;
end if;
when S_WRITE3 =>
ctrl_command_register <= ctrl_command_write;
ddr_dout <= din;
ddr_dmask <= be;
ddr_address <= adr;
ctrl_state <= S_WRITE4;
when S_WRITE4 =>
ctrl_command_register <= ctrl_command_write;
ctrl_state <= S_WRITE2;
when S_WRITE_END1 =>
ctrl_burst_done <= '1';
ctrl_state <= S_WRITE_END2;
when S_WRITE_END2 =>
if ctrl_cmd_ack = '0' then
ctrl_state <= S_IDLE;
end if;
when S_READ1 =>
ctrl_command_register <= ctrl_command_read;
if ctrl_cmd_ack = '1' then
ctrl_state <= S_READ2;
end if;
when S_READ2 =>
ctrl_command_register <= ctrl_command_read;
ctrl_state <= S_READ3;
when S_READ3 =>
ctrl_command_register <= ctrl_command_read;
ctrl_state <= S_READ4;
when S_READ4 =>
ctrl_command_register <= ctrl_command_read;
if fifo_from_sys_valid = '0' or adr(21 downto 9) /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
fifo_pending <= fifo_from_sys_valid;
ctrl_burst_done <= '1';
ctrl_state <= S_READ_END1;
else
ddr_address <= adr;
ctrl_state <= S_READ5;
end if;
when S_READ5 =>
ctrl_command_register <= ctrl_command_read;
ctrl_state <= S_READ4;
when S_READ_END1 =>
ctrl_burst_done <= '1';
ctrl_state <= S_READ_END2;
when S_READ_END2 =>
if ctrl_cmd_ack = '0' then
ctrl_state <= S_IDLE;
end if;
end case;
end if;
end if;
end process ctrl_fsm;
fifo_to_sys_write <= ctrl_data_valid;
end Behavioral;

269
src/wb_ddr_ctrl_wb_dc_fsm.vhd Executable file
View File

@@ -0,0 +1,269 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: wb_ddr_ctrl_wb_dc_fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wb_ddr_ctrl_wb_dc_fsm is
port (
-- Control signals
ddr2_clk0 : in std_ulogic;
ddr2_clk180 : in std_ulogic;
ddr2_reset : in std_ulogic;
-- Inputs
ctrl_data_valid : in std_logic;
ctrl_auto_ref_req : in std_logic;
ctrl_cmd_ack : in std_logic;
ctrl_init_done : in std_logic;
ctrl_ar_done : in std_logic;
fifo_from_sys_empty : in std_ulogic;
we : in std_ulogic;
row_addr : in std_ulogic_vector(12 downto 0);
-- Outputs
ddr_address_en : out std_ulogic;
ddr_dout_en : out std_ulogic;
ddr_dmask_rst : out std_ulogic;
ddr_dmask_en : out std_ulogic;
ctrl_command_register_d : out std_logic_vector(2 downto 0);
ctrl_burst_done_d : out std_ulogic;
fifo_from_sys_read : out std_ulogic
);
end wb_ddr_ctrl_wb_dc_fsm;
architecture Behavioral of wb_ddr_ctrl_wb_dc_fsm is
-- DDR2 Controller commands
constant ctrl_command_nop : std_logic_vector(2 downto 0) := "000";
constant ctrl_command_initialize : std_logic_vector(2 downto 0) := "010";
constant ctrl_command_write : std_logic_vector(2 downto 0) := "100";
constant ctrl_command_read : std_logic_vector(2 downto 0) := "110";
-- DDR-side FSM
type ctrl_states is (S_RESET, S_INITIALIZE, S_WAITINITDONE, S_IDLE, S_REFRESH, S_REQUEST_INIT, S_WRITE1,
S_WRITE2, S_WRITE3, S_WRITE4, S_WRITE_END1, S_WRITE_END2, S_READ1, S_READ2,
S_READ3, S_READ4, S_READ5, S_READ_END1, S_READ_END2);
signal ctrl_state : ctrl_states := S_RESET;
signal burst_start_adr : std_ulogic_vector(12 downto 0) := (others => '-');
signal fifo_pending : std_ulogic := '0';
-- fifo_pending is '1' when a valid, unprocessed request is on the fifo outputs
-- the idle state does not cause a fifo read if fifo_pending is '1'
signal fifo_from_sys_read_int, fifo_from_sys_valid : std_ulogic := '0';
begin
-- input FIFO control
fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or
(ctrl_state = S_REQUEST_INIT and we = '1') or
(ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or
(ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_WRITE4) or
(ctrl_state = S_READ3 or ctrl_state = S_READ5) or
(ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_READ2)
) and fifo_from_sys_empty = '0' else
'0';
is_fifo_from_sys_valid : process(ddr2_clk0)
begin
if rising_edge(ddr2_clk0) then
fifo_from_sys_valid <= fifo_from_sys_read_int;
end if;
end process is_fifo_from_sys_valid;
fifo_from_sys_read <= fifo_from_sys_read_int;
ctrl_fsm_state : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr2_reset = '1' then
ctrl_state <= S_RESET;
fifo_pending <= '0';
else
case ctrl_state is
when S_RESET =>
ctrl_state <= S_INITIALIZE;
when S_INITIALIZE =>
ctrl_state <= S_WAITINITDONE;
when S_WAITINITDONE =>
if ctrl_init_done = '1' then
ctrl_state <= S_IDLE;
end if;
when S_IDLE =>
if ctrl_auto_ref_req = '1' then -- DDR controller requests refresh
ctrl_state <= S_REFRESH;
elsif fifo_from_sys_valid = '1' then -- A request from the system is pending
ctrl_state <= S_REQUEST_INIT;
end if; -- else do nothing
when S_REFRESH =>
if ctrl_ar_done = '1' then
ctrl_state <= S_IDLE;
end if;
when S_REQUEST_INIT =>
if we = '1' then
ctrl_state <= S_WRITE1;
else
ctrl_state <= S_READ1;
end if;
burst_start_adr <= row_addr;
when S_WRITE1 =>
if ctrl_cmd_ack = '1' then
ctrl_state <= S_WRITE2;
end if;
when S_WRITE2 =>
if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
fifo_pending <= fifo_from_sys_valid;
ctrl_state <= S_WRITE_END1;
else
ctrl_state <= S_WRITE3;
end if;
when S_WRITE3 =>
ctrl_state <= S_WRITE4;
when S_WRITE4 =>
ctrl_state <= S_WRITE2;
when S_WRITE_END1 =>
ctrl_state <= S_WRITE_END2;
when S_WRITE_END2 =>
if ctrl_cmd_ack = '0' then
ctrl_state <= S_IDLE;
end if;
when S_READ1 =>
if ctrl_cmd_ack = '1' then
ctrl_state <= S_READ2;
end if;
when S_READ2 =>
ctrl_state <= S_READ3;
when S_READ3 =>
ctrl_state <= S_READ4;
when S_READ4 =>
if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
fifo_pending <= fifo_from_sys_valid;
ctrl_state <= S_READ_END1;
else
ctrl_state <= S_READ5;
end if;
when S_READ5 =>
ctrl_state <= S_READ4;
when S_READ_END1 =>
ctrl_state <= S_READ_END2;
when S_READ_END2 =>
if ctrl_cmd_ack = '0' then
ctrl_state <= S_IDLE;
end if;
end case;
end if;
end if;
end process ctrl_fsm_state;
ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_valid,
row_addr, burst_start_adr, ctrl_auto_ref_req)
begin
ddr_dmask_rst <= '0';
ddr_dmask_en <= '0';
ddr_dout_en <= '0';
ddr_address_en <= '0';
ctrl_burst_done_d <= '0';
ctrl_command_register_d <= ctrl_command_nop;
case ctrl_state is
when S_INITIALIZE =>
ctrl_command_register_d <= ctrl_command_initialize;
when S_REQUEST_INIT =>
if we = '1' then
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ctrl_command_register_d <= ctrl_command_write;
else
ctrl_command_register_d <= ctrl_command_read;
end if;
ddr_address_en <= '1';
when S_WRITE1 =>
if ctrl_cmd_ack = '1' then
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
end if;
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE2 =>
if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
ctrl_burst_done_d <= '1';
else
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
end if;
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE3 =>
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ddr_address_en <= '1';
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE4 =>
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE_END1 =>
ctrl_burst_done_d <= '1';
when S_READ1 =>
ctrl_command_register_d <= ctrl_command_read;
when S_READ2 =>
ctrl_command_register_d <= ctrl_command_read;
when S_READ3 =>
ctrl_command_register_d <= ctrl_command_read;
when S_READ4 =>
if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1' then
-- next request incompatible with burst type, or auto refresh requested
ctrl_burst_done_d <= '1';
else
ddr_address_en <= '1';
end if;
when S_READ5 =>
ctrl_command_register_d <= ctrl_command_read;
when S_READ_END1 =>
ctrl_burst_done_d <= '1';
when others =>
null;
end case;
end process ctrl_fsm_out;
end Behavioral;

57
src/wb_ddr_ctrl_wb_sc.vhd
View File

@@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
@@ -62,15 +62,14 @@ entity wb_ddr_ctrl_wb_sc is
end wb_ddr_ctrl_wb_sc;
architecture Behavioral of wb_ddr_ctrl_wb_sc is
type states is (S_IDLE, S_WRITE_CLASSIC1, S_READ_CLASSIC1, S_READ_CLASSIC2, S_READ_CLASSIC3);
type states is (S_IDLE, S_WRITE_CLASSIC1, S_READ_CLASSIC1, S_READ_CLASSIC2);
signal state : states := S_IDLE;
signal fifo_from_ddr_read_int, fifo_from_ddr_valid : std_ulogic;
begin
fifo_from_ddr_read_int <= '1' when (((state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or
(state = S_READ_CLASSIC2) or
(state = S_READ_CLASSIC3 and fifo_from_ddr_valid = '0')
(state = S_READ_CLASSIC2)
) and fifo_from_ddr_empty = '0') or rst_i = '1' else
'0';
@@ -92,6 +91,7 @@ wb_slave : process(clk_i)
ddr_we <= '-';
ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
ack_o <= '0';
state <= S_IDLE;
else
ddr_din <= (others => '-');
@@ -99,6 +99,7 @@ wb_slave : process(clk_i)
ddr_we <= '-';
ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
ack_o <= '0';
case state is
when S_IDLE =>
if stb_i = '1' then
@@ -110,7 +111,7 @@ wb_slave : process(clk_i)
ddr_din <= dat_i;
ddr_adr <= adr_i;
ddr_we <= '1';
ddr_be <= sel_i;
ddr_be <= not sel_i;
fifo_to_ddr_write <= '1';
state <= S_WRITE_CLASSIC1;
end if;
@@ -128,35 +129,31 @@ wb_slave : process(clk_i)
end if;
end if;
end if;
when S_WRITE_CLASSIC1 =>
if fifo_to_ddr_full = '0' then
ddr_din <= (others => '-');
ddr_adr <= adr_i;
ddr_we <= '1';
ddr_be <= (others => '0');
fifo_to_ddr_write <= '1';
ack_o <= '1';
state <= S_IDLE;
end if;
if fifo_to_ddr_full = '0' then
ddr_din <= (others => '-');
ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1);
ddr_we <= '1';
ddr_be <= (others => '1');
fifo_to_ddr_write <= '1';
ack_o <= '1';
state <= S_IDLE;
end if;
when S_READ_CLASSIC1 =>
if fifo_to_ddr_full = '0' then
ddr_adr <= adr_i;
ddr_we <= '0';
fifo_to_ddr_write <= '1';
state <= S_READ_CLASSIC2;
end if;
if fifo_to_ddr_full = '0' then
ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
state <= S_READ_CLASSIC2;
end if;
when S_READ_CLASSIC2 =>
if fifo_from_ddr_valid = '1' then
dat_o <= ddr_dout;
state <= S_READ_CLASSIC3;
end if;
when S_READ_CLASSIC3 =>
if fifo_from_ddr_valid = '1' then
ack_o <= '1';
state <= S_IDLE;
end if;
if fifo_from_ddr_valid = '1' then
dat_o <= ddr_dout;
ack_o <= '1';
state <= S_IDLE;
end if;
end case;
end if;
end if;

44
tb/wb_ddr_ctrl_tb.vhd
View File

@@ -108,16 +108,16 @@ architecture testbench of wb_ddr_ctrl_tb is
signal ddr2_ck_n : std_logic_vector(0 downto 0);
signal clk_i : std_ulogic := '0';
signal rst_i : std_ulogic;
signal dat_i : std_ulogic_vector(31 downto 0);
signal dat_i : std_ulogic_vector(31 downto 0) := (others => '-');
signal dat_o : std_ulogic_vector(31 downto 0);
signal ack_o : std_ulogic;
signal adr_i : std_ulogic_vector(25 downto 2);
signal cyc_i : std_ulogic;
signal sel_i : std_ulogic_vector(3 downto 0);
signal stb_i : std_ulogic;
signal we_i : std_ulogic;
signal cti_i : std_ulogic_vector(2 downto 0);
signal bte_i : std_ulogic_vector(1 downto 0);
signal adr_i : std_ulogic_vector(25 downto 2) := (others => '-');
signal cyc_i : std_ulogic := '0';
signal sel_i : std_ulogic_vector(3 downto 0) := (others => '0');
signal stb_i : std_ulogic := '0';
signal we_i : std_ulogic := '0';
signal cti_i : std_ulogic_vector(2 downto 0) := (others => '0');
signal bte_i : std_ulogic_vector(1 downto 0) := (others => '0');
begin -- testbench
@@ -191,6 +191,34 @@ begin -- testbench
wait until rising_edge(clk_i);
rst_i <= '0' after 2 ns;
-- simple write cycle
wait until rising_edge(clk_i);
stb_i <= '1' after 2 ns;
we_i <= '1' after 2 ns;
sel_i <= "1111" after 2 ns;
adr_i <= x"000010" after 2 ns;
dat_i <= x"deadbeef" after 2 ns;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- simple read cycle
wait until rising_edge(clk_i);
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
adr_i <= x"000010" after 2 ns;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity failure;
wait until rising_edge(clk_i);
wait;
end process WaveGen_Proc;