matthias/2d_display_engine-new
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34bec7d6c7bd7f2fa42a9241fb1b0a54966534cb
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Matthias Blankertz 34bec7d6c7 - Begun implementing VGA out 
- Integrated wishbone interconnect generator
- Debugging
2013-03-02 21:27:54 +01:00
constr
- Import project
2013-02-26 23:54:37 +01:00
coregen
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
ddr2_sdram/vhdl_bl4/example_design
- Import project
2013-02-26 23:54:37 +01:00
src
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
tb
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
tools
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
.gitignore
- Fixed DDR reset polarity
2013-02-27 12:13:26 +01:00
2d_display_engine.xst
- Import project
2013-02-26 23:54:37 +01:00
Makefile
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
planahead_postsynth.tcl
- Fixed DDR reset polarity
2013-02-27 12:13:26 +01:00
toplevel_tb.wcfg
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
wb_ddr_ctrl_tb.wcfg
- Begun implementing VGA out
2013-03-02 21:27:54 +01:00
Description
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372 KiB
Languages
VHDL 69.1%
Verilog 10.1%
SystemVerilog 8%
Raku 7.9%
C++ 2.6%
Other 2.2%