matthias/2d_display_engine-new
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

- Begun implementing VGA out

Browse Source 
- Integrated wishbone interconnect generator
- Debugging
This commit is contained in:
Matthias Blankertz
2013-03-02 21:27:54 +01:00
parent f65882554d
commit 34bec7d6c7
20 changed files with 4825 additions and 1310 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
Makefile
View File

@@ -25,12 +25,14 @@ ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
src/toplevel.vhd src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
src/wb_interconnect.vhd \
src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
src/wb_ddr_ctrl_wb_sc.vhd
src/wb_ddr_ctrl_wb_sc.vhd src/vga_syncgen.vhd src/vga_pixelgen.vhd \
src/vga_pixelreader.vhd src/vga.vhd src/cpu.vhd src/toplevel.vhd
SYN_INFILES=
PSMFILES=
CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr
CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr vga_pixeldata_fifo
PRJNAME=2d_display_engine
NGCFILE=$(PRJNAME).ngc
XSTFILE=$(PRJNAME).xst
@@ -49,13 +51,13 @@ PAROPTS=-rl high -pl high
BITGENOPTS=
TRACEOPTS=-v -u 100
SIM_INFILES=
SIM_INFILES=src/sim_bmppack.vhd
SIM_INFILES_VLOG=ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
GHDLOPTS=--workdir=ghdl -Pghdl --ieee=synopsys -fexplicit
VLOGCOMPOPTS=-d x512Mb -d sg5E -d x16
VLOGCOMPOPTS=-d x512Mb -d sg5E -d x16 -d MAX_MEM
SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
SIMALLFILES=$(COMMON_INFILES) $(SIM_INFILES)
SIMALLFILES=$(SIM_INFILES) $(COMMON_INFILES)
SIMALLFILESXDB=$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
@@ -72,6 +74,8 @@ VHPCOMP=$(XILPATH)vhpcomp
VLOGCOMP=$(XILPATH)vlogcomp
FUSE=$(XILPATH)fuse
.SECONDARY:
all: $(BITFILE)
synth: $(NGCFILE)
@@ -80,8 +84,11 @@ impl: $(NCDFILE_R)
timing: $(TWRFILE)
%.vhd: %.psm
../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
#%.vhd: %.psm
# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
src/wb_interconnect.vhd: src/wishbone.defines
cd src && ../tools/wishbone.pl -nogui wishbone.defines
$(PRJFILE): Makefile
rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done

1403
coregen/coregen.cgc
View File

File diff suppressed because it is too large Load Diff

213
coregen/vga_pixeldata_fifo.xco Normal file
View File

@@ -0,0 +1,213 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Sat Mar 02 17:01:48 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=vga_pixeldata_fifo
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=496
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=495
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=512
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=16
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 558db809

8
src/clk_reset.vhd
View File

@@ -42,18 +42,18 @@ entity clk_reset is
end clk_reset;
architecture Behavioral of clk_reset is
signal locked_int, rst_int : std_ulogic;
signal locked_int, rst_int : std_ulogic := '0';
signal clkOut50_int : std_ulogic;
constant reset_pulse_width : integer := 3;
signal rstIn_sync_dcm : std_ulogic_vector(2 downto 0) := "000";
signal dcm_in_rst : std_ulogic;
signal dcm_in_rst : std_ulogic := '0';
signal dcm_in_rst_ctr : natural range 0 to reset_pulse_width-1;
signal locked_prev : std_ulogic;
signal locked_prev : std_ulogic := '0';
signal rstIn_sync_sys : std_ulogic_vector(2 downto 0) := "000";
signal sys_in_rst : std_ulogic;
signal sys_in_rst : std_ulogic := '1';
signal sys_in_rst_ctr : natural range 0 to reset_pulse_width-1;
begin

147
src/cpu.vhd Normal file
View File

@@ -0,0 +1,147 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: CPU module
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.intercon_package.all;
-- This is currently a only a simple state machine that initializes the frame
-- buffer and then enables the vga output, for debugging.
entity cpu is
generic (
burst_length : integer := 16
);
port (
clk : in std_logic;
rst : in std_logic;
enable_vga : out std_logic;
cpu_wbm_i : in cpu_wbm_i_type;
cpu_wbm_o : out cpu_wbm_o_type
);
end cpu;
architecture Behavioral of cpu is
type states is (S_INIT, S_WRITE, S_DONE);
signal state : states := S_INIT;
signal enable_vga_i : std_logic := '0';
signal x : integer range 0 to 639 := 0;
signal y : integer range 0 to 480 := 0;
signal adr : integer range 0 to 153600 := 0;
signal burst_ctr : integer range 0 to burst_length := 0;
begin
fill_fb : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
enable_vga_i <= '0';
x <= 0;
y <= 0;
adr <= 0;
cpu_wbm_o.stb_o <= '0';
cpu_wbm_o.cyc_o <= '0';
state <= S_INIT;
else
case state is
when S_INIT =>
cpu_wbm_o.stb_o <= '1';
cpu_wbm_o.cyc_o <= '1';
cpu_wbm_o.cti_o <= "010";
cpu_wbm_o.bte_o <= "00";
cpu_wbm_o.we_o <= '1';
cpu_wbm_o.sel_o <= (others => '1');
cpu_wbm_o.adr_o <= std_logic_vector(to_unsigned(adr*4,cpu_wbm_o.adr_o'length));
-- draw a 1px white border around a black screen
if y = 0 or y = 479 then
cpu_wbm_o.dat_o <= x"ffffffff";
elsif x = 0 then
cpu_wbm_o.dat_o <= x"ffff0000";
elsif x = 639 then
cpu_wbm_o.dat_o <= x"0000ffff";
else
cpu_wbm_o.dat_o <= x"00000000";
end if;
burst_ctr <= 0;
adr <= adr + 1;
x <= x + 1;
state <= S_WRITE;
when S_WRITE =>
if cpu_wbm_i.ack_i = '1' then
if burst_ctr = burst_length-2 then
cpu_wbm_o.cti_o <= "111";
end if;
if burst_ctr = burst_length-1 then
cpu_wbm_o.stb_o <= '0';
cpu_wbm_o.cyc_o <= '0';
if adr = 153600 then
state <= S_DONE;
else
state <= S_INIT;
end if;
else
cpu_wbm_o.adr_o <= std_logic_vector(to_unsigned(adr*4,cpu_wbm_o.adr_o'length));
-- draw a 1px white border around a black screen
if y = 0 or y = 479 then
cpu_wbm_o.dat_o <= x"ffffffff";
elsif x = 0 then
cpu_wbm_o.dat_o <= x"ffff0000";
elsif x = 639 then
cpu_wbm_o.dat_o <= x"0000ffff";
else
cpu_wbm_o.dat_o <= x"00000000";
end if;
adr <= adr + 1;
if x = 639 then
y <= y + 1;
x <= 0;
else
x <= x + 1;
end if;
burst_ctr <= burst_ctr + 1;
end if;
end if;
when S_DONE =>
enable_vga_i <= '1';
end case;
end if;
end if;
end process fill_fb;
enable_vga <= enable_vga_i;
end Behavioral;

234
src/sim_bmppack.vhd Normal file
View File

@@ -0,0 +1,234 @@
-------------------------------------------------------------------------------
-- Title : BMP Package
-- Project :
-------------------------------------------------------------------------------
-- File : sim_bmppack.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2013-03-02
-- Platform : ModelSIM 6.0
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006 by Kest
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
package sim_bmppack is
-- maximale Größe des Speichers
constant cMAX_X : integer := 1300;
constant cMAX_Y : integer := 1300;
constant cBytesPerPixel : integer := 3;
constant cMaxMemSize : integer := cMAX_X * cMAX_Y * cBytesPerPixel;
subtype file_element is std_logic_vector(7 downto 0);
type mem_array is array(cMaxMemSize downto 0) of file_element;
type header_array is array(53 downto 0) of file_element;
procedure ReadFile(FileName : in string);
procedure WriteFile(FileName : in string);
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0));
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0));
function GetWidth(header : in header_array) return integer;
procedure GetWidth(signal width : out integer);
function GetHeigth(header : in header_array) return integer;
procedure GetHeigth(signal height : out integer);
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0));
procedure SetPixel (x : in integer; y : in integer; data : in std_logic_vector(23 downto 0));
end package sim_bmppack;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body sim_bmppack is
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
shared variable memory_in : mem_array;
shared variable memory_out : mem_array;
shared variable header : header_array;
shared variable pImageSize : integer;
shared variable pImageWidth : integer;
shared variable pImageHeight : integer;
-----------------------------------------------------------------------------
-- This code reads a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure ReadFile(FileName : in string) is
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
variable index : integer := 0;
type bit_vector_file is file of bit_vector;
file read_file : bit_vector_file open read_mode is FileName;
begin
report "Read File";
report FileName;
index := 0;
---------------------------------------------------------------------------
-- Header einlesen
---------------------------------------------------------------------------
report "Read Header";
for i in 0 to 53 loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
header(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
index := index + 1;
end if;
end loop;
pImageWidth := GetWidth(header);
pImageHeight := GetHeigth(header);
pImageSize := pImageWidth * pImageHeight;
report "Read Image";
index := 0;
while not endfile(read_file) loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
memory_in(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
memory_out(index) := x"45";
index := index + 1;
end if;
end loop;
report "Okay";
end ReadFile;
-----------------------------------------------------------------------------
-- Read one byte from Memory
-----------------------------------------------------------------------------
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0)) is
begin
data := memory_in(adr);
end ReadByteFromMemory;
-----------------------------------------------------------------------------
-- Pixel Operationen
-----------------------------------------------------------------------------
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
data(23 downto 16) <= memory_in(x*3 + 3*y*GetWidth(header));
data(15 downto 8) <= memory_in(x*3+1 + 3*y*GetWidth(header));
data(7 downto 0) <= memory_in(x*3+2 + 3*y*GetWidth(header));
end if;
end GetPixel;
procedure SetPixel (x : in integer; y : in integer; data : in std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
memory_out(x*3+y*(GetWidth(header)*3)) := data(23 downto 16);
memory_out(x*3+1+y*(GetWidth(header)*3)) := data(15 downto 8);
memory_out(x*3+2+y*(GetWidth(header)*3)) := data(7 downto 0);
end if;
end SetPixel;
-----------------------------------------------------------------------------
-- Write one byte to Memory
-----------------------------------------------------------------------------
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0)) is
begin
memory_out(adr) := data;
end WriteByteToMemory;
-- Get Width of Image
function GetWidth(header : in header_array) return integer is
begin
return conv_integer(header(21) & header(20) & header(19) & header(18));
end function GetWidth;
procedure GetWidth(signal width : out integer) is
begin
width <= pImageWidth;
end GetWidth;
-- Get Height of Image
function GetHeigth(header : in header_array) return integer is
begin
return conv_integer(header(25) & header(24) & header(23) & header(22));
end function GetHeigth;
procedure GetHeigth(signal height : out integer) is
begin
height <= pImageHeight;
end GetHeigth;
-----------------------------------------------------------------------------
-- This code write a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure WriteFile(FileName : in string) is
variable next_vector : character;
variable index : integer := 0;
type char_file is file of character;
file write_file : char_file open write_mode is FileName;
begin
report "Write File...";
report FileName;
report "write Header";
index := 0;
for i in 0 to 53 loop
next_vector := character'val(conv_integer(header(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "write Image";
index := 0;
while index < pImageSize*3 loop
next_vector := character'val(conv_integer(memory_out(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "Okay";
end WriteFile;
end sim_bmppack;

237
src/toplevel.vhd
View File

@@ -31,7 +31,7 @@ use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.all;
use work.intercon_package.all;
entity toplevel is
Port (
@@ -72,68 +72,98 @@ entity toplevel is
end toplevel;
architecture Mixed of toplevel is
component clk_reset is
component clk_reset is
Generic (
reset_dcm_on_ext_reset : BOOLEAN := false
);
reset_dcm_on_ext_reset : BOOLEAN := false
);
Port ( clkIn50 : in STD_ULOGIC;
sysClk50 : out STD_ULOGIC;
rstIn : in STD_ULOGIC;
sysRst50 : out STD_ULOGIC);
end component;
component wb_ddr_ctrl is
end component;
component wb_ddr_ctrl is
Port (
-- DDR2 control
ddr2_clock : in std_ulogic;
ddr2_reset : in std_ulogic;
-- DDR2 SDRAM
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic;
ddr2_cs_n : out std_logic;
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_odt : out std_logic;
ddr2_dm : out std_logic_vector(1 downto 0);
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
ddr2_dqs : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0)
);
end component;
-- DDR2 control
ddr2_clock : in std_ulogic;
ddr2_reset : in std_ulogic;
-- DDR2 SDRAM
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic;
ddr2_cs_n : out std_logic;
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_odt : out std_logic;
ddr2_dm : out std_logic_vector(1 downto 0);
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
ddr2_dqs : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type
);
end component;
component vga
port (
clk_in : in std_ulogic;
rst : in std_ulogic;
enable_vga : in std_logic;
wbm_i : in vga_wbm_i_type;
wbm_o : out vga_wbm_o_type;
red : out std_ulogic_vector(3 downto 0);
green : out std_ulogic_vector(3 downto 0);
blue : out std_ulogic_vector(3 downto 0);
vsync : out std_ulogic;
hsync : out std_ulogic);
end component;
component cpu
generic (
burst_length : integer);
port (
clk : in std_logic;
rst : in std_logic;
enable_vga : out std_logic;
cpu_wbm_i : in cpu_wbm_i_type;
cpu_wbm_o : out cpu_wbm_o_type);
end component;
component intercon
port (
vga_wbm_i : out vga_wbm_i_type;
vga_wbm_o : in vga_wbm_o_type;
cpu_wbm_i : out cpu_wbm_i_type;
cpu_wbm_o : in cpu_wbm_o_type;
sdram_ctrl_wbs_i : out sdram_ctrl_wbs_i_type;
sdram_ctrl_wbs_o : in sdram_ctrl_wbs_o_type;
clk : in std_logic;
reset : in std_logic);
end component;
signal sysClk, sysRst : std_logic;
signal wb_ddr_dat_i : std_ulogic_vector(31 downto 0);
signal wb_ddr_dat_o : std_ulogic_vector(31 downto 0);
signal wb_ddr_ack_o : std_ulogic;
signal wb_ddr_adr_i : std_ulogic_vector(25 downto 2);
signal wb_ddr_cyc_i : std_ulogic;
signal wb_ddr_sel_i : std_ulogic_vector(3 downto 0);
signal wb_ddr_stb_i : std_ulogic;
signal wb_ddr_we_i : std_ulogic;
signal wb_ddr_cti_i : std_ulogic_vector(2 downto 0);
signal wb_ddr_bte_i : std_ulogic_vector(1 downto 0);
signal vga_wbm_i : vga_wbm_i_type;
signal vga_wbm_o : vga_wbm_o_type;
signal cpu_wbm_o : cpu_wbm_o_type;
signal cpu_wbm_i : cpu_wbm_i_type;
signal sdram_ctrl_wbs_i : sdram_ctrl_wbs_i_type;
signal sdram_ctrl_wbs_o : sdram_ctrl_wbs_o_type;
signal enable_vga : std_logic;
begin
sys_clk_rst : clk_reset
port map (
@@ -144,41 +174,70 @@ sys_clk_rst : clk_reset
);
ddr_ctrl0 : wb_ddr_ctrl
port map (
-- DDR2 control
ddr2_clock => clkin_133MHz,
ddr2_reset => reset,
-- DDR2 SDRAM
ddr2_dq => ddr2_dq,
ddr2_a => ddr2_a,
ddr2_ba => ddr2_ba,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_odt => ddr2_odt,
ddr2_dm => ddr2_dm,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n,
clk_i => sysClk,
rst_i => sysRst,
dat_i => wb_ddr_dat_i,
dat_o => wb_ddr_dat_o,
ack_o => wb_ddr_ack_o,
adr_i => wb_ddr_adr_i,
cyc_i => wb_ddr_cyc_i,
sel_i => wb_ddr_sel_i,
stb_i => wb_ddr_stb_i,
we_i => wb_ddr_we_i,
cti_i => wb_ddr_cti_i,
bte_i => wb_ddr_bte_i
);
port map (
-- DDR2 control
ddr2_clock => clkin_133MHz,
ddr2_reset => reset,
-- DDR2 SDRAM
ddr2_dq => ddr2_dq,
ddr2_a => ddr2_a,
ddr2_ba => ddr2_ba,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_odt => ddr2_odt,
ddr2_dm => ddr2_dm,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n,
clk_i => sysClk,
rst_i => sysRst,
wbs_i => sdram_ctrl_wbs_i,
wbs_o => sdram_ctrl_wbs_o
);
vga_inst: vga
port map (
clk_in => sysClk,
rst => sysRst,
enable_vga => enable_vga,
wbm_i => vga_wbm_i,
wbm_o => vga_wbm_o,
red => vga_r,
green => vga_g,
blue => vga_b,
vsync => vga_vsync,
hsync => vga_hsync);
cpu_1: cpu
generic map (
burst_length => 16)
port map (
clk => sysClk,
rst => sysRst,
enable_vga => enable_vga,
cpu_wbm_i => cpu_wbm_i,
cpu_wbm_o => cpu_wbm_o);
intercon_1: intercon
port map (
vga_wbm_i => vga_wbm_i,
vga_wbm_o => vga_wbm_o,
cpu_wbm_i => cpu_wbm_i,
cpu_wbm_o => cpu_wbm_o,
sdram_ctrl_wbs_i => sdram_ctrl_wbs_i,
sdram_ctrl_wbs_o => sdram_ctrl_wbs_o,
clk => sysClk,
reset => sysRst);
end Mixed;

165
src/vga.vhd Normal file
View File

@@ -0,0 +1,165 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: vga - Structural
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: VGA module
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.intercon_package.all;
entity vga is
port (
clk_in : in std_ulogic;
rst : in std_ulogic;
-- temporary, for debugging
enable_vga : in std_logic;
-- Wishbone master
wbm_i : in vga_wbm_i_type;
wbm_o : out vga_wbm_o_type;
-- to vga
red : out std_ulogic_vector(3 downto 0);
green : out std_ulogic_vector(3 downto 0);
blue : out std_ulogic_vector(3 downto 0);
vsync : out std_ulogic;
hsync : out std_ulogic
);
end vga;
architecture Structural of vga is
component vga_pixelreader
port (
clk : in std_ulogic;
rst : in std_ulogic;
pixeldata : out std_logic_vector(31 downto 0);
fifo_write : out std_ulogic;
fifo_full16 : in std_ulogic;
wbm_i : in vga_wbm_i_type;
wbm_o : out vga_wbm_o_type);
end component;
component vga_pixeldata_fifo
port (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC);
end component;
component vga_syncgen
generic (
sync_out_delay : integer);
port (
clk : in std_ulogic;
vsync : out std_ulogic;
hsync : out std_ulogic;
column : out unsigned(9 downto 0);
row : out unsigned(9 downto 0));
end component;
component vga_pixelgen
port (
clk : in std_ulogic;
row : in unsigned(9 downto 0);
column : in unsigned(9 downto 0);
pixeldata : in std_ulogic_vector(15 downto 0);
fifo_read : out std_ulogic;
fifo_empty : in std_ulogic;
red : out std_ulogic_vector(3 downto 0);
green : out std_ulogic_vector(3 downto 0);
blue : out std_ulogic_vector(3 downto 0));
end component;
signal in_pixeldata : std_logic_vector(31 downto 0);
signal out_pixeldata : std_logic_vector(15 downto 0);
signal fifo_write, fifo_read, fifo_empty, fifo_full16 : std_ulogic;
signal column, row : unsigned(9 downto 0);
signal clk : std_logic := '0';
begin
clk <= clk_in when enable_vga = '1' else '0';
vga_pixelreader_inst: vga_pixelreader
port map (
clk => clk,
rst => rst,
pixeldata => in_pixeldata,
fifo_write => fifo_write,
fifo_full16 => fifo_full16,
wbm_i => wbm_i,
wbm_o => wbm_o);
vga_pixeldata_fifo_inst: vga_pixeldata_fifo
port map (
rst => rst,
wr_clk => clk,
rd_clk => clk,
din => in_pixeldata,
wr_en => fifo_write,
rd_en => fifo_read,
dout => out_pixeldata,
full => open,
empty => fifo_empty,
prog_full => fifo_full16);
vga_syncgen_inst: vga_syncgen
generic map (
sync_out_delay => 1)
port map (
clk => clk,
vsync => vsync,
hsync => hsync,
column => column,
row => row);
vga_pixelgen_inst: vga_pixelgen
port map (
clk => clk,
row => row,
column => column,
pixeldata => std_ulogic_vector(out_pixeldata),
fifo_read => fifo_read,
fifo_empty => fifo_empty,
red => red,
green => green,
blue => blue);
end Structural;

85
src/vga_pixelgen.vhd Normal file
View File

@@ -0,0 +1,85 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: vga_pixelgen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: VGA pixel generator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_pixelgen is
port (
clk : in std_ulogic;
-- from syncgen
row : in unsigned(9 downto 0);
column : in unsigned(9 downto 0);
-- from fifo
pixeldata : in std_ulogic_vector(15 downto 0);
fifo_read : out std_ulogic;
fifo_empty : in std_ulogic;
-- to vga
red : out std_ulogic_vector(3 downto 0);
green : out std_ulogic_vector(3 downto 0);
blue : out std_ulogic_vector(3 downto 0)
);
end vga_pixelgen;
architecture Behavioral of vga_pixelgen is
begin
pixelgen : process(clk)
begin
if rising_edge(clk) then
if row <= 479 and column <= 640 then
fifo_read <= '1';
else
fifo_read <= '0';
end if;
if row <= 479 and column > 1 and column <= 641 then
if fifo_empty = '1' then
assert false report "Warning: VGA output FIFO underflow" severity warning;
red <= (others => '0');
green <= (others => '0');
blue <= (others => '0');
else
red <= pixeldata(3 downto 0);
green <= pixeldata(7 downto 4);
blue <= pixeldata(11 downto 8);
end if;
else
red <= (others => '0');
green <= (others => '0');
blue <= (others => '0');
end if;
end if;
end process pixelgen;
end Behavioral;

109
src/vga_pixelreader.vhd Normal file
View File

@@ -0,0 +1,109 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: vga_pixelreader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: VGA pixel reader
-- Read data from RAM into pixeldata FIFO
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.intercon_package.all;
entity vga_pixelreader is
generic (
framebuffer0_base : integer := 0;
burst_length : integer := 16
);
port (
clk : in std_ulogic;
rst : in std_ulogic;
-- from/to fifo
pixeldata : out std_logic_vector(31 downto 0);
fifo_write : out std_ulogic;
fifo_full16 : in std_ulogic; -- FIFO is 16 dwords from full (= 1 burst)
-- Wishbone master
wbm_i : in vga_wbm_i_type;
wbm_o : out vga_wbm_o_type
);
end vga_pixelreader;
architecture Behavioral of vga_pixelreader is
type states is (S_IDLE, S_READ);
signal state : states := S_IDLE;
signal addr_ctr : natural range 0 to 153599 := 0;
signal burst_ctr : natural range 0 to burst_length-1 := 0;
begin
pixelreader : process(clk)
begin
if rising_edge(clk) then
fifo_write <= '0';
case state is
when S_IDLE =>
if fifo_full16 = '0' then -- space in fifo for a burst of data
wbm_o.cyc_o <= '1';
wbm_o.stb_o <= '1';
wbm_o.cti_o <= "010";
wbm_o.bte_o <= "00";
wbm_o.sel_o <= (others => '1');
wbm_o.adr_o <= std_logic_vector(to_unsigned(framebuffer0_base+addr_ctr*4, wbm_o.adr_o'length));
burst_ctr <= 0;
addr_ctr <= addr_ctr + 1;
state <= S_READ;
end if;
when S_READ =>
if wbm_i.ack_i = '1' then
pixeldata <= wbm_i.dat_i;
fifo_write <= '1';
if burst_ctr = burst_length-2 then
wbm_o.cti_o <= "111";
end if;
if burst_ctr = burst_length-1 then
wbm_o.cyc_o <= '0';
wbm_o.stb_o <= '0';
state <= S_IDLE;
else
wbm_o.adr_o <= std_logic_vector(to_unsigned(framebuffer0_base+addr_ctr*4, wbm_o.adr_o'length));
if addr_ctr = 153599 then
addr_ctr <= 0;
else
addr_ctr <= addr_ctr + 1;
end if;
burst_ctr <= burst_ctr + 1;
end if;
end if;
end case;
end if;
end process pixelreader;
end Behavioral;

120
src/vga_syncgen.vhd Normal file
View File

@@ -0,0 +1,120 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name:
-- Module Name: vga_syncgen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: VGA sync generator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_syncgen is
generic (
sync_out_delay : integer := 0 -- delay vsync/hsync this many clk cycles wrt
-- column/row
);
port (
clk : in std_ulogic;
vsync : out std_ulogic := '1';
hsync : out std_ulogic := '1';
column : out unsigned(9 downto 0);
row : out unsigned(9 downto 0)
);
end vga_syncgen;
architecture Behavioral of vga_syncgen is
signal row_i : natural range 0 to 524;
signal column_i : natural range 0 to 799;
signal vsync_i, hsync_i : std_ulogic := '1';
begin
hsync_gen : process(clk)
begin
if rising_edge(clk) then
if column_i = 799 then
column_i <= 0;
else
column_i <= column_i + 1;
end if;
if column_i >= 659 and column_i <= 754 then
hsync_i <= '0';
else
hsync_i <= '1';
end if;
end if;
end process hsync_gen;
vsync_gen : process(clk)
begin
if rising_edge(clk) then
if column_i = 659 then
if row_i = 524 then
row_i <= 0;
else
row_i <= row_i + 1;
end if;
if row_i = 493 then
vsync_i <= '0';
else
vsync_i <= '1';
end if;
end if;
end if;
end process vsync_gen;
column <= to_unsigned(column_i, 10);
row <= to_unsigned(row_i, 10);
no_sync_delay : if sync_out_delay = 0 generate
vsync <= vsync_i;
hsync <= hsync_i;
end generate;
sync_delay_1 : if sync_out_delay = 1 generate
sync_delay_p : process(clk)
begin
if rising_edge(clk) then
vsync <= vsync_i;
hsync <= hsync_i;
end if;
end process sync_delay_p;
end generate;
sync_delay_2 : if sync_out_delay > 1 generate
signal vsync_dly, hsync_dly : std_ulogic_vector(sync_out_delay-1 downto 0) := (others => '1');
begin
sync_delay_p : process(clk)
begin
if rising_edge(clk) then
vsync_dly <= vsync_dly(sync_out_delay-2 downto 0) & vsync_i;
hsync_dly <= hsync_dly(sync_out_delay-2 downto 0) & hsync_i;
vsync <= vsync_dly(sync_out_delay-1);
hsync <= hsync_dly(sync_out_delay-1);
end if;
end process sync_delay_p;
end generate;
end Behavioral;

40
src/wb_ddr_ctrl.vhd
View File

@@ -31,7 +31,9 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
use work.all;
--use work.all;
use work.intercon_package.all;
entity wb_ddr_ctrl is
Port (
@@ -60,16 +62,8 @@ entity wb_ddr_ctrl is
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0)
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type
);
end wb_ddr_ctrl;
@@ -142,16 +136,8 @@ component wb_ddr_ctrl_wb is
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0)
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type
);
end component;
@@ -227,16 +213,8 @@ wb_0 : wb_ddr_ctrl_wb
ctrl_init_done => ctrl_init_done,
ctrl_ar_done => ctrl_ar_done,
dat_i => dat_i,
dat_o => dat_o,
ack_o => ack_o,
adr_i => adr_i,
cyc_i => cyc_i,
sel_i => sel_i,
stb_i => stb_i,
we_i => we_i,
cti_i => cti_i,
bte_i => bte_i
wbs_i => wbs_i,
wbs_o => wbs_o
);
end Behavioral;

52
src/wb_ddr_ctrl_wb.vhd
View File

@@ -31,6 +31,8 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
use work.intercon_package.all;
entity wb_ddr_ctrl_wb is
Port (
-- Control signals
@@ -54,16 +56,8 @@ entity wb_ddr_ctrl_wb is
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0)
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type
);
end wb_ddr_ctrl_wb;
@@ -99,23 +93,15 @@ component wb_ddr_ctrl_wb_sc is
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0);
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type;
-- To/from ddr clock domain
ddr_din : out std_ulogic_vector(63 downto 0);
ddr_dout : in std_ulogic_vector(63 downto 0);
ddr_adr : out std_ulogic_vector(22 downto 0);
ddr_din : out std_logic_vector(63 downto 0);
ddr_dout : in std_logic_vector(63 downto 0);
ddr_adr : out std_logic_vector(22 downto 0);
ddr_we : out std_ulogic;
ddr_be : out std_ulogic_vector(7 downto 0);
ddr_be : out std_logic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic;
@@ -163,7 +149,7 @@ signal s2d_fifo_rd, s2d_fifo_wr, d2s_fifo_rd, d2s_fifo_wr : std_ulogic;
signal s2d_fifo_empty, s2d_fifo_full, d2s_fifo_empty, d2s_fifo_full : std_ulogic;
-- FIFO data signals
signal s2d_fifo_din : std_ulogic_vector(95 downto 0);
signal s2d_fifo_din : std_logic_vector(95 downto 0);
signal d2s_fifo_din : std_ulogic_vector(63 downto 0);
signal s2d_fifo_dout : std_logic_vector(95 downto 0);
signal d2s_fifo_dout : std_logic_vector(63 downto 0);
@@ -179,20 +165,12 @@ system_cd_inst : wb_ddr_ctrl_wb_sc
-- Wishbone slave
clk_i => clk_i,
rst_i => rst_i,
dat_i => dat_i,
dat_o => dat_o,
ack_o => ack_o,
adr_i => adr_i,
cyc_i => cyc_i,
sel_i => sel_i,
stb_i => stb_i,
we_i => we_i,
cti_i => cti_i,
bte_i => bte_i,
wbs_i => wbs_i,
wbs_o => wbs_o,
-- To/from ddr clock domain
ddr_din => s2d_fifo_din(63 downto 0),
ddr_dout => std_ulogic_vector(d2s_fifo_dout),
ddr_dout => d2s_fifo_dout,
ddr_adr => s2d_fifo_din(86 downto 64),
ddr_we => s2d_fifo_din(87),
ddr_be => s2d_fifo_din(95 downto 88),
@@ -213,7 +191,7 @@ s2d_fifo : wb_ddr_ctrl_wb_to_ddr
full => s2d_fifo_full,
empty => s2d_fifo_empty,
din => std_logic_vector(s2d_fifo_din),
din => s2d_fifo_din,
dout => s2d_fifo_dout
);

457
src/wb_ddr_ctrl_wb_sc.vhd
View File

@@ -31,34 +31,32 @@ use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
use work.intercon_package.all;
entity wb_ddr_ctrl_wb_sc is
Port (
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(31 downto 0);
dat_o : out std_ulogic_vector(31 downto 0);
ack_o : out std_ulogic;
adr_i : in std_ulogic_vector(25 downto 2);
cyc_i : in std_ulogic;
sel_i : in std_ulogic_vector(3 downto 0);
stb_i : in std_ulogic;
we_i : in std_ulogic;
cti_i : in std_ulogic_vector(2 downto 0);
bte_i : in std_ulogic_vector(1 downto 0);
-- To/from ddr clock domain
ddr_din : out std_ulogic_vector(63 downto 0);
ddr_dout : in std_ulogic_vector(63 downto 0);
ddr_adr : out std_ulogic_vector(22 downto 0);
ddr_we : out std_ulogic;
ddr_be : out std_ulogic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic;
fifo_to_ddr_full : in std_ulogic;
fifo_from_ddr_empty : in std_ulogic
);
generic (
burst_length : integer := 16 -- Currently only read burst, for write burst
-- arbitrary length is supported
);
port (
-- Wishbone slave
clk_i : in std_ulogic;
rst_i : in std_ulogic;
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type;
-- To/from ddr clock domain
ddr_din : out std_logic_vector(63 downto 0);
ddr_dout : in std_logic_vector(63 downto 0);
ddr_adr : out std_logic_vector(22 downto 0);
ddr_we : out std_ulogic;
ddr_be : out std_logic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic;
fifo_to_ddr_full : in std_ulogic;
fifo_from_ddr_empty : in std_ulogic
);
end wb_ddr_ctrl_wb_sc;
architecture Behavioral of wb_ddr_ctrl_wb_sc is
@@ -66,14 +64,27 @@ type states is (S_IDLE,
S_WRITE_CLASSIC1,
S_WRITE_BURST1, S_WRITE_BURST2, S_WRITE_BURST_WAIT1,
S_WRITE_BURST_WAIT2,
S_READ_CLASSIC1, S_READ_CLASSIC2, S_READ_CLASSIC3);
S_READ_CLASSIC1, S_READ_CLASSIC2,
S_READ_BURST1,S_READ_BURST_NEEDDATA, S_READ_BURST_GOTDATA,
S_READ_BURST_END);
signal state : states := S_IDLE;
signal fifo_from_ddr_read_int, fifo_from_ddr_valid : std_ulogic;
signal burst_ctr : natural range 1 to burst_length;
signal burst_unaligned : std_ulogic;
signal ddr_dout_high, ddr_dout_high_d : std_ulogic;
begin
fifo_from_ddr_read_int <= '1' when ((--(state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or
(state = S_READ_CLASSIC1)
(state = S_READ_CLASSIC1) or
-- (state = S_READ_BURST1 and fifo_to_ddr_full = '0' and
-- ((burst_unaligned = '1' and burst_ctr = burst_length/2) or
-- (burst_unaligned = '0' and burst_ctr = (burst_length/2)-1))) or
(state = S_READ_BURST_NEEDDATA) --or
-- (state = S_READ_BURST4)
) and fifo_from_ddr_empty = '0') or rst_i = '1' else
'0';
@@ -86,163 +97,241 @@ is_fifo_from_ddr_valid : process(clk_i)
fifo_from_ddr_read <= fifo_from_ddr_read_int;
wb_slave : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
ddr_din <= (others => '-');
ddr_adr <= (others => '-');
ddr_we <= '-';
ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
ack_o <= '0';
state <= S_IDLE;
else
--ddr_din <= (others => '-');
--ddr_adr <= (others => '-');
ddr_we <= '-';
--ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
ack_o <= '0';
case state is
when S_IDLE =>
if stb_i = '1' then
if we_i = '1' then
if cti_i = "010" and bte_i = "00" then -- incrementing
-- linear burst
if fifo_to_ddr_full = '0' then
ack_o <= '1';
if adr_i(2) = '0' then -- aligned start
ddr_din <= (others => '-');
ddr_adr <= (others => '-');
ddr_be <= (others => '-');
state <= S_WRITE_BURST2;
else -- unaligned start
ddr_adr <= (others => '-');
ddr_adr <= (others => '-');
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= "1111";
state <= S_WRITE_BURST1;
end if;
end if;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
if adr_i(2) = '0' then
ddr_din(31 downto 0) <= dat_i;
ddr_din(63 downto 32) <= (others => '-');
ddr_be <= "1111" & not sel_i;
else
ddr_din(31 downto 0) <= (others => '-');
ddr_din(63 downto 32) <= dat_i;
ddr_be <= not sel_i & "1111";
end if;
ddr_adr <= adr_i(25 downto 3);
ddr_we <= '1';
fifo_to_ddr_write <= '1';
ack_o <= '1';
state <= S_WRITE_CLASSIC1;
end if;
end if;
else
ddr_din <= (others => '-');
ddr_be <= (others => '-');
if cti_i = "010" then -- incrementing burst
null;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
ddr_adr <= adr_i(25 downto 3);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
state <= S_READ_CLASSIC1;
end if;
end if;
end if;
end if;
when S_WRITE_CLASSIC1 =>
ddr_adr <= (others => '-');
state <= S_IDLE;
wbs_o.dat_o <= ddr_dout(63 downto 32) when ddr_dout_high = '1' else
ddr_dout(31 downto 0);
when S_WRITE_BURST1 => -- high dword, commit
ddr_din(63 downto 32) <= dat_i;
ddr_be(7 downto 4) <= not sel_i;
ddr_adr <= adr_i(25 downto 3);
if fifo_to_ddr_full = '0' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
if cti_i = "111" then -- EOB, aligned end
state <= S_IDLE;
ack_o <= '0';
else
state <= S_WRITE_BURST2;
ack_o <= '1';
end if;
else -- FIFO full
state <= S_WRITE_BURST_WAIT1;
ack_o <= '0';
end if;
when S_WRITE_BURST2 => -- low dword
ddr_adr <= (others => '-');
ddr_din(63 downto 32) <= (others => '-');
ddr_din(31 downto 0) <= dat_i;
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= not sel_i;
if cti_i = "111" then -- EOB, unaligned end
ddr_be(7 downto 4) <= (others => '1');
ddr_adr <= adr_i(25 downto 3);
if fifo_to_ddr_full = '1' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
else
state <= S_WRITE_BURST_WAIT2;
end if;
ack_o <= '0';
else
state <= S_WRITE_BURST1;
ack_o <= '1';
end if;
when S_WRITE_BURST_WAIT1 =>
if fifo_to_ddr_full = '0' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
if cti_i = "111" then
state <= S_IDLE;
ack_o <= '0';
else
state <= S_WRITE_BURST2;
ack_o <= '1';
end if;
end if;
when S_WRITE_BURST_WAIT2 =>
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
when S_READ_CLASSIC1 =>
ddr_adr <= (others => '-');
if fifo_from_ddr_valid = '1' then
state <= S_READ_CLASSIC2;
end if;
when S_READ_CLASSIC2 =>
ddr_adr <= (others => '-');
if adr_i(2) = '0' then
dat_o <= ddr_dout(31 downto 0);
else
dat_o <= ddr_dout(63 downto 32);
end if;
ack_o <= '1';
state <= S_READ_CLASSIC3;
when S_READ_CLASSIC3 =>
ddr_adr <= (others => '-');
state <= S_IDLE;
end case;
ddr_dout_high_d <= wbs_i.adr_i(2) when (state = S_READ_CLASSIC1) else
'1' when (state = S_READ_BURST_NEEDDATA and burst_unaligned = '1' and burst_ctr = 1) else
'1' when (state = S_READ_BURST_GOTDATA) else
'0' when (state = S_READ_BURST_NEEDDATA) else
'-';
ddr_dout_high_reg : process(clk_i)
begin
if rising_edge(clk_i) then
ddr_dout_high <= ddr_dout_high_d;
end if;
end process ddr_dout_high_reg;
wb_slave : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
ddr_din <= (others => '-');
ddr_adr <= (others => '-');
ddr_we <= '-';
ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
wbs_o.ack_o <= '0';
state <= S_IDLE;
else
--ddr_din <= (others => '-');
--ddr_adr <= (others => '-');
ddr_we <= '-';
--ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
wbs_o.ack_o <= '0';
case state is
when S_IDLE =>
if wbs_i.stb_i = '1' then
if wbs_i.we_i = '1' then
if wbs_i.cti_i = "010" and wbs_i.bte_i = "00" then -- incrementing
-- linear burst
if fifo_to_ddr_full = '0' then
wbs_o.ack_o <= '1';
if wbs_i.adr_i(2) = '0' then -- aligned start
ddr_din <= (others => '-');
ddr_adr <= (others => '-');
ddr_be <= (others => '-');
state <= S_WRITE_BURST2;
else -- unaligned start
ddr_adr <= (others => '-');
ddr_adr <= (others => '-');
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= "1111";
state <= S_WRITE_BURST1;
end if;
end if;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
if wbs_i.adr_i(2) = '0' then
ddr_din(31 downto 0) <= wbs_i.dat_i;
ddr_din(63 downto 32) <= (others => '-');
ddr_be <= "1111" & not wbs_i.sel_i;
else
ddr_din(31 downto 0) <= (others => '-');
ddr_din(63 downto 32) <= wbs_i.dat_i;
ddr_be <= not wbs_i.sel_i & "1111";
end if;
ddr_adr <= wbs_i.adr_i(25 downto 3);
ddr_we <= '1';
fifo_to_ddr_write <= '1';
wbs_o.ack_o <= '1';
state <= S_WRITE_CLASSIC1;
end if;
end if;
else
ddr_din <= (others => '-');
ddr_be <= (others => '-');
if wbs_i.cti_i = "010" and wbs_i.bte_i = "00" then -- incrementing
-- linear burst
if fifo_to_ddr_full = '0' then
ddr_din <= (others => '-');
ddr_be <= (others => '-');
ddr_adr <= wbs_i.adr_i(25 downto 3);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
if wbs_i.adr_i(2) = '0' then
burst_unaligned <= '0';
else
burst_unaligned <= '1';
end if;
burst_ctr <= 1;
state <= S_READ_BURST1;
end if;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
ddr_adr <= wbs_i.adr_i(25 downto 3);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
state <= S_READ_CLASSIC1;
end if;
end if;
end if;
end if;
end process wb_slave;
end if;
when S_WRITE_CLASSIC1 =>
ddr_adr <= (others => '-');
state <= S_IDLE;
when S_WRITE_BURST1 => -- high dword, commit
ddr_din(63 downto 32) <= wbs_i.dat_i;
ddr_be(7 downto 4) <= not wbs_i.sel_i;
ddr_adr <= wbs_i.adr_i(25 downto 3);
if fifo_to_ddr_full = '0' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
if wbs_i.cti_i = "111" then -- EOB, aligned end
state <= S_IDLE;
wbs_o.ack_o <= '0';
elsif wbs_i.stb_i = '0' then
assert false report "Unexpected wbs_i.stb_i deassertion during write burst" severity warning;
ddr_be(7 downto 4) <= (others => '1');
state <= S_IDLE;
wbs_o.ack_o <= '0';
else
state <= S_WRITE_BURST2;
wbs_o.ack_o <= '1';
end if;
else -- FIFO full
state <= S_WRITE_BURST_WAIT1;
wbs_o.ack_o <= '0';
end if;
when S_WRITE_BURST2 => -- low dword
ddr_adr <= (others => '-');
ddr_din(63 downto 32) <= (others => '-');
ddr_din(31 downto 0) <= wbs_i.dat_i;
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= not wbs_i.sel_i;
if wbs_i.cti_i = "111" then -- EOB, unaligned end
ddr_be(7 downto 4) <= (others => '1');
ddr_adr <= wbs_i.adr_i(25 downto 3);
if fifo_to_ddr_full = '1' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
else
state <= S_WRITE_BURST_WAIT2;
end if;
wbs_o.ack_o <= '0';
elsif wbs_i.stb_i = '0' then
assert false report "Unexpected stb_i deassertion during write burst" severity warning;
state <= S_IDLE;
wbs_o.ack_o <= '0';
else
state <= S_WRITE_BURST1;
wbs_o.ack_o <= '1';
end if;
when S_WRITE_BURST_WAIT1 =>
if fifo_to_ddr_full = '0' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
if wbs_i.cti_i = "111" then
state <= S_IDLE;
wbs_o.ack_o <= '0';
else
state <= S_WRITE_BURST2;
wbs_o.ack_o <= '1';
end if;
end if;
when S_WRITE_BURST_WAIT2 =>
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
when S_READ_CLASSIC1 =>
ddr_adr <= (others => '-');
if fifo_from_ddr_valid = '1' then
wbs_o.ack_o <= '1';
state <= S_READ_CLASSIC2;
end if;
when S_READ_CLASSIC2 =>
ddr_adr <= (others => '-');
state <= S_IDLE;
when S_READ_BURST1 =>
ddr_din <= (others => '-');
ddr_be <= (others => '-');
if fifo_to_ddr_full = '0' then
ddr_adr <= std_logic_vector(unsigned(wbs_i.adr_i(25 downto 3)) + burst_ctr);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
if (burst_unaligned = '1' and burst_ctr = burst_length/2) or
(burst_unaligned = '0' and burst_ctr = (burst_length/2)-1) then
burst_ctr <= 1;
state <= S_READ_BURST_NEEDDATA;
else
burst_ctr <= burst_ctr + 1;
end if;
end if;
when S_READ_BURST_NEEDDATA =>
ddr_din <= (others => '-');
ddr_be <= (others => '-');
ddr_adr <= (others => '-');
if fifo_from_ddr_valid = '1' then
wbs_o.ack_o <= '1';
if burst_ctr = burst_length then
state <= S_READ_BURST_END;
else
burst_ctr <= burst_ctr + 1;
if burst_unaligned = '1' and burst_ctr = 1 then
state <= S_READ_BURST_NEEDDATA;
else
state <= S_READ_BURST_GOTDATA;
end if;
end if;
end if;
when S_READ_BURST_GOTDATA =>
ddr_din <= (others => '-');
ddr_be <= (others => '-');
ddr_adr <= (others => '-');
wbs_o.ack_o <= '1';
if burst_ctr = burst_length then
state <= S_READ_BURST_END;
else
burst_ctr <= burst_ctr + 1;
state <= S_READ_BURST_NEEDDATA;
end if;
when S_READ_BURST_END =>
state <= S_IDLE;
end case;
end if;
end if;
end process wb_slave;
end Behavioral;

58
src/wishbone.defines Normal file
View File

@@ -0,0 +1,58 @@
# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# Generated Thu Jun 24 14:29:34 2004
filename=wb_interconnect
intercon=intercon
syscon=syscon
target=xilinx
hdl=vhdl
signal_groups=1
tga_bits=2
tgc_bits=3
tgd_bits=0
rename_tga=bte
rename_tgc=cti
rename_tgd=tgd
classic=000
endofburst=111
dat_size=32
adr_size=28
mux_type=andor
interconnect=crossbarswitch
master vga
type=ro
lock_o=0
tga_o=1
tgc_o=1
tgd_o=0
err_i=0
rty_i=0
priority_sdram_ctrl=3
end master vga
master cpu
type=rw
lock_o=0
tga_o=1
tgc_o=1
tgd_o=0
err_i=0
rty_i=0
priority_sdram_ctrl=2
end master cpu
slave sdram_ctrl
type=rw
adr_i_hi=25
adr_i_lo=2
tga_i=1
tgc_i=1
tgd_i=0
lock_i=0
err_o=0
rty_o=0
baseadr=0x00000000
size=0x4000000
end slave sdram_ctrl

214
tb/toplevel_tb.vhd Normal file
View File

@@ -0,0 +1,214 @@
-------------------------------------------------------------------------------
-- Title : Testbench for design "toplevel"
-- Project :
-------------------------------------------------------------------------------
-- File : toplevel_tb.vhd
-- Author : <Matthias@MATTHIAS-PC>
-- Company :
-- Created : 2013-03-02
-- Last update: 2013-03-02
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-02 1.0 Matthias Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sim_bmppack.all;
-------------------------------------------------------------------------------
entity toplevel_tb is
end toplevel_tb;
-------------------------------------------------------------------------------
architecture testbench of toplevel_tb is
component toplevel
port (
clkin_50MHz : IN std_ulogic;
clkin_133MHz : IN std_ulogic;
reset : IN std_ulogic;
vga_r, vga_g, vga_b : OUT std_ulogic_vector(3 downto 0);
vga_vsync, vga_hsync : OUT std_ulogic;
dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic;
dataflash_miso : IN std_ulogic;
led : OUT std_ulogic_vector(7 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic;
ddr2_cs_n : out std_logic;
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_odt : out std_logic;
ddr2_dm : out std_logic_vector(1 downto 0);
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
ddr2_dqs : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0));
end component;
component ddr2_model
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector(1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(12 downto 0);
dq : inout std_logic_vector(15 downto 0);
dqs : inout std_logic_vector(1 downto 0);
dqs_n : inout std_logic_vector(1 downto 0);
rdqs_n : out std_logic_vector(1 downto 0);
odt : in std_logic
);
end component;
-- component ports
signal clkin_50MHz : std_ulogic := '0';
signal clkin_133MHz : std_ulogic := '0';
signal reset : std_ulogic := '0';
signal vga_r, vga_g, vga_b : std_ulogic_vector(3 downto 0);
signal vga_vsync, vga_hsync : std_ulogic;
signal dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : std_ulogic;
signal dataflash_miso : std_ulogic;
signal led : std_ulogic_vector(7 downto 0);
signal ddr2_dq : std_logic_vector(15 downto 0);
signal ddr2_a : std_logic_vector(12 downto 0);
signal ddr2_ba : std_logic_vector(1 downto 0);
signal ddr2_cke : std_logic;
signal ddr2_cs_n : std_logic;
signal ddr2_ras_n : std_logic;
signal ddr2_cas_n : std_logic;
signal ddr2_we_n : std_logic;
signal ddr2_odt : std_logic;
signal ddr2_dm : std_logic_vector(1 downto 0);
signal rst_dqs_div_in : std_logic;
signal rst_dqs_div_out : std_logic;
signal ddr2_dqs : std_logic_vector(1 downto 0);
signal ddr2_dqs_n : std_logic_vector(1 downto 0);
signal ddr2_ck : std_logic_vector(0 downto 0);
signal ddr2_ck_n : std_logic_vector(0 downto 0);
begin -- testbench
-- component instantiation
DUT: toplevel
port map (
clkin_50MHz => clkin_50MHz,
clkin_133MHz => clkin_133MHz,
reset => reset,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b,
vga_vsync => vga_vsync,
vga_hsync => vga_hsync,
dataflash_mosi => dataflash_mosi,
dataflash_sck => dataflash_sck,
dataflash_ss => dataflash_ss,
dataflash_wp => dataflash_wp,
dataflash_rst => dataflash_rst,
dataflash_miso => dataflash_miso,
led => led,
ddr2_dq => ddr2_dq,
ddr2_a => ddr2_a,
ddr2_ba => ddr2_ba,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_odt => ddr2_odt,
ddr2_dm => ddr2_dm,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n);
rst_dqs_div_in <= rst_dqs_div_out after 100 ps;
ddr2_model_inst : ddr2_model port map (
ck => ddr2_ck(0),
ck_n => ddr2_ck_n(0),
cke => ddr2_cke,
cs_n => ddr2_cs_n,
ras_n => ddr2_ras_n,
cas_n => ddr2_cas_n,
we_n => ddr2_we_n,
dm_rdqs => ddr2_dm,
ba => ddr2_ba,
addr => ddr2_a,
dq => ddr2_dq,
dqs => ddr2_dqs,
dqs_n => ddr2_dqs_n,
rdqs_n => open,
odt => ddr2_odt);
-- clock generation
clkin_133MHz <= not clkin_133MHz after 3.7594 ns;
clkin_50MHz <= not clkin_50MHz after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait;
end process WaveGen_Proc;
VGARead: process
variable i: integer := 0;
variable pixeldata : std_logic_vector(23 downto 0);
begin
ReadFile("vga.bmp");
wait for 100 ns; -- wait for uut to stat
wait until rising_edge(vga_vsync); -- wait for vga frame to start (depends
-- on latency of UUT)
while true loop
for y in 479 downto 0 loop
for x in 0 to 639 loop
pixeldata := std_logic_vector(vga_r) & "0000" & std_logic_vector(vga_g) & "0000" & std_logic_vector(vga_b) & "0000";
SetPixel(x, y, pixeldata);
wait for 40 ns;
end loop; -- x
wait for 6400 ns;
end loop; -- x
wait for 1440 us;
WriteFile("vga" & integer'image(i) & ".bmp");
i := i + 1;
end loop;
end process;
end testbench;
-------------------------------------------------------------------------------
configuration toplevel_tb_testbench_cfg of toplevel_tb is
for testbench
end for;
end toplevel_tb_testbench_cfg;
-------------------------------------------------------------------------------

148
tb/wb_ddr_ctrl_tb.vhd
View File

@@ -181,6 +181,7 @@ begin -- testbench
-- waveform generation
WaveGen_Proc: process
variable expected_data : std_ulogic_vector(31 downto 0);
begin
-- insert signal assignments here
ddr2_reset <= '1';
@@ -216,7 +217,7 @@ begin -- testbench
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning;
assert dat_o = x"deadbeef" report "Read failed: unexpected data (expected 0xdeadbeef)" severity warning;
wait until rising_edge(clk_i);
-- simple write cycle
@@ -244,7 +245,7 @@ begin -- testbench
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning;
assert dat_o = x"deadbeef" report "Read failed: unexpected data (expected 0xdeadbeef)" severity warning;
wait until rising_edge(clk_i);
-- simple read cycle
@@ -257,7 +258,7 @@ begin -- testbench
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"1234567" report "Read failed: unexpected data" severity warning;
assert dat_o = x"12345678" report "Read failed: unexpected data (expected 0x12345678)" severity warning;
wait until rising_edge(clk_i);
-- burst write cycle
@@ -267,7 +268,30 @@ begin -- testbench
stb_i <= '1' after 2 ns;
we_i <= '1' after 2 ns;
dat_i <= x"d000000d" after 2 ns;
for i in 0 to 15 loop
for i in 0 to 7 loop
adr_i <= std_ulogic_vector(to_unsigned(256+i,24)) after 2 ns;
dat_i(23 downto 16) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
dat_i(15 downto 8) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
sel_i <= "1111" after 2 ns;
if i = 7 then -- EOB
cti_i <= "111" after 2 ns;
end if;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
end loop; -- i
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- unaligned burst write cycle
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '1' after 2 ns;
dat_i <= x"d000000d" after 2 ns;
for i in 7 to 31 loop
adr_i <= std_ulogic_vector(to_unsigned(256+i,24)) after 2 ns;
dat_i(23 downto 16) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
dat_i(15 downto 8) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
@@ -294,16 +318,124 @@ begin -- testbench
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"d005050d" report "Read failed: unexpected data" severity warning;
assert dat_o = x"d005050d" report "Read failed: unexpected data (expected 0xd005050d)" severity warning;
wait until rising_edge(clk_i);
-- burst read cycle
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
for i in 0 to 15 loop
adr_i <= std_ulogic_vector(to_unsigned(256+i,24)) after 2 ns;
expected_data(31 downto 24) := x"d0";
expected_data(23 downto 16) := std_ulogic_vector(to_unsigned(i,8));
expected_data(15 downto 8) := std_ulogic_vector(to_unsigned(i,8));
expected_data(7 downto 0) := x"0d";
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
assert dat_o = expected_data report "Read failed: unexpected_data" severity warning;
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- burst read cycle
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
for i in 16 to 31 loop
adr_i <= std_ulogic_vector(to_unsigned(256+i,24)) after 2 ns;
expected_data(31 downto 24) := x"d0";
expected_data(23 downto 16) := std_ulogic_vector(to_unsigned(i,8));
expected_data(15 downto 8) := std_ulogic_vector(to_unsigned(i,8));
expected_data(7 downto 0) := x"0d";
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
assert dat_o = expected_data report "Read failed: unexpected_data" severity warning;
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- unaligned burst read cycle
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
for i in 15 to 30 loop
adr_i <= std_ulogic_vector(to_unsigned(256+i,24)) after 2 ns;
expected_data(31 downto 24) := x"d0";
expected_data(23 downto 16) := std_ulogic_vector(to_unsigned(i,8));
expected_data(15 downto 8) := std_ulogic_vector(to_unsigned(i,8));
expected_data(7 downto 0) := x"0d";
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
assert dat_o = expected_data report "Read failed: unexpected_data" severity warning;
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- burst write cycle crossing row boundary
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '1' after 2 ns;
dat_i <= x"d000000d" after 2 ns;
for i in 0 to 15 loop
adr_i <= std_ulogic_vector(to_unsigned(4088+i,24)) after 2 ns;
dat_i(23 downto 16) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
dat_i(15 downto 8) <= std_ulogic_vector(to_unsigned(i,8)) after 2 ns;
sel_i <= "1111" after 2 ns;
if i = 15 then -- EOB
cti_i <= "111" after 2 ns;
end if;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
end loop; -- i
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- burst read cycle crossing row boundary
wait until rising_edge(clk_i);
cti_i <= "010" after 2 ns; -- incrementing burst
bte_i <= "00" after 2 ns; -- linear
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
for i in 0 to 15 loop
adr_i <= std_ulogic_vector(to_unsigned(4088+i,24)) after 2 ns;
expected_data(31 downto 24) := x"d0";
expected_data(23 downto 16) := std_ulogic_vector(to_unsigned(i,8));
expected_data(15 downto 8) := std_ulogic_vector(to_unsigned(i,8));
expected_data(7 downto 0) := x"0d";
if i = 15 then -- EOB
cti_i <= "111" after 2 ns;
end if;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
assert dat_o = expected_data report "Read failed: unexpected_data" severity warning;
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
assert false report "Test complete" severity failure;
wait;
end process WaveGen_Proc;
end testbench;
-------------------------------------------------------------------------------

2032
tools/wishbone.pl Normal file
View File

File diff suppressed because it is too large Load Diff

378
toplevel_tb.wcfg Normal file
View File

@@ -0,0 +1,378 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="intercon_package" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="toplevel_tb" />
<top_module name="vcomponents" />
<top_module name="vhdl_bl4_parameters_0" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vl_types" />
<top_module name="vpkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="40" />
<wvobject fp_name="/toplevel_tb/DUT/clkin_50mhz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clkin_50mhz</obj_property>
<obj_property name="ObjectShortName">clkin_50mhz</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/clkin_133mhz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clkin_133mhz</obj_property>
<obj_property name="ObjectShortName">clkin_133mhz</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_r" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_r[3:0]</obj_property>
<obj_property name="ObjectShortName">vga_r[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_g" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_g[3:0]</obj_property>
<obj_property name="ObjectShortName">vga_g[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_b[3:0]</obj_property>
<obj_property name="ObjectShortName">vga_b[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_vsync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_vsync</obj_property>
<obj_property name="ObjectShortName">vga_vsync</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_hsync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_hsync</obj_property>
<obj_property name="ObjectShortName">vga_hsync</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_mosi</obj_property>
<obj_property name="ObjectShortName">dataflash_mosi</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_sck" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_sck</obj_property>
<obj_property name="ObjectShortName">dataflash_sck</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_ss" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_ss</obj_property>
<obj_property name="ObjectShortName">dataflash_ss</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_wp" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_wp</obj_property>
<obj_property name="ObjectShortName">dataflash_wp</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_rst</obj_property>
<obj_property name="ObjectShortName">dataflash_rst</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/dataflash_miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dataflash_miso</obj_property>
<obj_property name="ObjectShortName">dataflash_miso</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/led" type="array" db_ref_id="1">
<obj_property name="ElementShortName">led[7:0]</obj_property>
<obj_property name="ObjectShortName">led[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_dq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_a[12:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_a[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_ba" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ba[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ba[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_cke" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cke</obj_property>
<obj_property name="ObjectShortName">ddr2_cke</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_cs_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cs_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cs_n</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_ras_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ras_n</obj_property>
<obj_property name="ObjectShortName">ddr2_ras_n</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_cas_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cas_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cas_n</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_we_n</obj_property>
<obj_property name="ObjectShortName">ddr2_we_n</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_odt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_odt</obj_property>
<obj_property name="ObjectShortName">ddr2_odt</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_dm" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dm[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/rst_dqs_div_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_in</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_in</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/rst_dqs_div_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_out</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_out</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_dqs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_dqs_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs_n[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_ck" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr2_ck_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck_n[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck_n[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sysclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sysclk</obj_property>
<obj_property name="ObjectShortName">sysclk</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sysrst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sysrst</obj_property>
<obj_property name="ObjectShortName">sysrst</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_wbm_i</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i.ack_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_i</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i.ack_i</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_wbm_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.sel_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.sel_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.adr_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.adr_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.bte_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.bte_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.bte_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.cti_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.cti_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.cyc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.stb_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_ctrl_wbs_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.we_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.sel_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.adr_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.bte_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.bte_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cti_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.stb_i</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_ctrl_wbs_o</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_o</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_o.ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_o</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_o.ack_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group68" type="group">
<obj_property name="label">cpu_1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/enable_vga" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enable_vga</obj_property>
<obj_property name="ObjectShortName">enable_vga</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_i</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.we_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.we_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.sel_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.sel_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.adr_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.adr_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.bte_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.bte_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.bte_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.cti_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.cti_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.cyc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.stb_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/enable_vga_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enable_vga_i</obj_property>
<obj_property name="ObjectShortName">enable_vga_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/x" type="other" db_ref_id="1">
<obj_property name="ElementShortName">x</obj_property>
<obj_property name="ObjectShortName">x</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/y" type="other" db_ref_id="1">
<obj_property name="ElementShortName">y</obj_property>
<obj_property name="ObjectShortName">y</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/adr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">adr</obj_property>
<obj_property name="ObjectShortName">adr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/burst_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_ctr</obj_property>
<obj_property name="ObjectShortName">burst_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/burst_length" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_length</obj_property>
<obj_property name="ObjectShortName">burst_length</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group86" type="group">
<obj_property name="label">vga_pixelgen_1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/row" type="array" db_ref_id="1">
<obj_property name="ElementShortName">row[9:0]</obj_property>
<obj_property name="ObjectShortName">row[9:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/column" type="array" db_ref_id="1">
<obj_property name="ElementShortName">column[9:0]</obj_property>
<obj_property name="ObjectShortName">column[9:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/pixeldata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pixeldata[15:0]</obj_property>
<obj_property name="ObjectShortName">pixeldata[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/fifo_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_read</obj_property>
<obj_property name="ObjectShortName">fifo_read</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/fifo_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_empty</obj_property>
<obj_property name="ObjectShortName">fifo_empty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/red" type="array" db_ref_id="1">
<obj_property name="ElementShortName">red[3:0]</obj_property>
<obj_property name="ObjectShortName">red[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/green" type="array" db_ref_id="1">
<obj_property name="ElementShortName">green[3:0]</obj_property>
<obj_property name="ObjectShortName">green[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/blue" type="array" db_ref_id="1">
<obj_property name="ElementShortName">blue[3:0]</obj_property>
<obj_property name="ObjectShortName">blue[3:0]</obj_property>
</wvobject>
</wvobject>
</wave_config>

12
Default.wcfg → wb_ddr_ctrl_tb.wcfg
View File

@@ -428,5 +428,17 @@
<obj_property name="ElementShortName">fifo_from_ddr_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_dout_high" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_high</obj_property>
<obj_property name="ObjectShortName">ddr_dout_high</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/burst_unaligned" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">burst_unaligned</obj_property>
<obj_property name="ObjectShortName">burst_unaligned</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/burst_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_ctr</obj_property>
<obj_property name="ObjectShortName">burst_ctr</obj_property>
</wvobject>
</wvobject>
</wave_config>