Files
2d_display_engine-new/planahead_postsynth.tcl
2013-02-27 12:13:26 +01:00

5 lines
308 B
Tcl
Executable File

create_project -force -part xc3s700an-fgg484-4 postsynth planahead
set_property design_mode GateLvl [current_fileset]
import_files 2d_display_engine.ngc coregen/wb_ddr_ctrl_wb_from_ddr.ngc coregen/wb_ddr_ctrl_wb_to_ddr.ngc
import_files -fileset constrs_1 constr/2d_display_engine.ucf constr/vhdl_bl4.ucf