Matthias Blankertz cac9a8a60f - Corrected write timing

2013-03-02 12:29:07 +01:00

constr

- Import project

2013-02-26 23:54:37 +01:00

coregen

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

ddr2_sdram/vhdl_bl4/example_design

- Import project

2013-02-26 23:54:37 +01:00

src

- Corrected write timing

2013-03-02 12:29:07 +01:00

tb

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

.gitignore

- Fixed DDR reset polarity

2013-02-27 12:13:26 +01:00

2d_display_engine.xst

- Import project

2013-02-26 23:54:37 +01:00

Default.wcfg

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

Makefile

- Made build rule for testbenches generic

2013-03-02 12:26:58 +01:00

planahead_postsynth.tcl

- Fixed DDR reset polarity

2013-02-27 12:13:26 +01:00

Description

No description provided

372 KiB

Languages

VHDL 69.1%

Verilog 10.1%

SystemVerilog 8%

Raku 7.9%

C++ 2.6%

Other 2.2%