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• 0080ec255d WIP master Matthias Blankertz 2017-02-01 12:07:10 +01:00
• 6cd60cf263 - WIP: New cache for CPU - sysClk reduced to 45 MHz Matthias Blankertz 2013-06-19 15:01:32 +02:00
• 0a96ce78f0 - New Wishbone master for CPU - WIP: New cache for CPU - Memory controller now supports modulu bursts and different burst lengths - WIP: Timing problems... Matthias Blankertz 2013-06-19 09:16:36 +02:00
• 0bc4815926 - Debugged SPI module - Debugged UART - Firmware support for SPI, UART - Work on SD/MMC support in firmware - Debugged mblite core/WB interface Matthias Blankertz 2013-06-08 11:53:27 +02:00
• fd4e8df556 - Started implementing SPI controller Matthias Blankertz 2013-06-05 15:40:06 +02:00
• 1807fb99b5 - Replaced cache with simpler wishbone-memory bridge - Redesign wishbone interconnect - Changed wb_ddr_ctrl_wb_sc to allow easier addition of ports Matthias Blankertz 2013-06-04 23:18:16 +02:00
• 882ec0a33f - Integrated MBlite CPU - Integrated UART - Various bug fixes Matthias Blankertz 2013-06-03 19:36:51 +02:00
• f501602ad6 - Added LEDs to ucf Matthias Blankertz 2013-06-02 11:56:10 +02:00
• a75ce72129 - Fixed address generation bug for manual cache flush - Made some constants in cpu.vhd more readable - Fixed buffer flipping in cpu.vhd Matthias Blankertz 2013-05-31 16:42:22 +02:00
• 66105bec04 - Rasterizer Matthias Blankertz 2013-03-27 20:21:58 +01:00
• a279c63df6 - Started implementing rasterizer Matthias Blankertz 2013-03-26 17:24:15 +01:00
• 1d71dfc308 - Simulator rasterizer working - Beginning hardware rasterizer implementation Matthias Blankertz 2013-03-22 20:12:20 +01:00
• 922e103f41 - Always convert wishbone.defines to unix line endings so interconnect is correctly build on windows - Removed TK dependency from tools/wishbone.pl Matthias Blankertz 2013-03-21 19:57:49 +01:00
• 19e97ad179 - Added double buffering support to vga controller and cpu - Removed an unused output in wb_ddr_ctrl_wb_dc_fsm Matthias Blankertz 2013-03-21 19:05:22 +01:00
• a6b20d3311 - Fixed wishbone interconnect generator - Fixed accidental latches in wb_ddr_ctrl_wb_sc.vhd - Updated cpu for new manual cache flush Matthias Blankertz 2013-03-21 16:06:53 +01:00
• 37d63b062d - Some optimization - Cache manual flush/invalidate is now whole cache instead of by address Matthias Blankertz 2013-03-19 20:24:28 +01:00
• 973513900d - Work on simulator - Optimized wb_ddr_ctrl_wb_sc_fe and wb_ddr_ctrl_wb_dc[_fsm] Matthias Blankertz 2013-03-18 15:27:18 +01:00
• be7f1337f2 - Work on simulator Matthias Blankertz 2013-03-14 13:06:42 +01:00
• 2cdd255433 - Corrected memory width to 64 bit - Read/WritePipe (without latency modelling) implemented Matthias Blankertz 2013-03-13 18:35:06 +01:00
• 1cb700f0c3 - Simulator for shader core started Matthias Blankertz 2013-03-12 19:43:57 +01:00
• d6c83c5105 - Makefile now generates xst file and has targets to open planahead (planahead_post{synth,impl}) Matthias Blankertz 2013-03-11 21:23:04 +01:00
• 077bef75d3 - System integration & debugging Matthias Blankertz 2013-03-09 14:14:22 +01:00
• 861cd1e00d - Integrated DDR controller with VGA and cache controller - Debugged the above Matthias Blankertz 2013-03-08 21:43:43 +01:00
• 90631f89bd - Reworked VGA - Started changing DDR controller interface to 64 bit bus width - Debugging Matthias Blankertz 2013-03-07 20:55:58 +01:00
• 17835c4f7f - Debugging - Added manual flush/invalidate to cache Matthias Blankertz 2013-03-05 22:49:30 +01:00
• 321ea30ed8 - Added synthesis contraints - Added ZPU processor - Optimized wb_ddr_ctrl_wb_dc* to meet timing - Added cache frontend Matthias Blankertz 2013-03-04 12:55:59 +01:00
• 34bec7d6c7 - Begun implementing VGA out - Integrated wishbone interconnect generator - Debugging Matthias Blankertz 2013-03-02 21:27:54 +01:00
• f65882554d - Debugged write burst Matthias Blankertz 2013-03-02 12:29:47 +01:00
• cac9a8a60f - Corrected write timing Matthias Blankertz 2013-03-02 12:29:07 +01:00
• c04775d4a7 - Made build rule for testbenches generic Matthias Blankertz 2013-03-02 12:26:58 +01:00
• 95aa43b2d5 - Debugging wb_ddr_ctrl - Changed wb_ddr_ctrl_wb FIFO to 64 bit data width - Added write burst support to wb_ddr_ctrl_wb_sc Matthias Blankertz 2013-02-28 21:10:44 +01:00
• 56930a80c3 - Seperated control and data path in wb_ddr_ctrl_wb_dc - Debugging wb_ddr_ctrl Matthias Blankertz 2013-02-28 15:54:48 +01:00
• 70aaa51615 - Fixed DDR reset polarity - Added planAhead script Matthias Blankertz 2013-02-27 12:13:26 +01:00
• dd2c99b93f - Import project - Clean up Matthias Blankertz 2013-02-26 23:54:37 +01:00