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- Started implementing rasterizer

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This commit is contained in:
Matthias Blankertz
2013-03-26 17:24:15 +01:00
parent 1d71dfc308
commit a279c63df6
8 changed files with 1252 additions and 105 deletions
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2
Makefile
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@@ -32,6 +32,8 @@ src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
src/wb_ddr_ctrl_wb_sc_fe_ram.vhd src/wb_ddr_ctrl_wb_sc_fe_fsm.vhd src/wb_ddr_ctrl_wb_sc_fe.vhd \
src/wb_ddr_ctrl_wb_sc.vhd src/vga_syncgen.vhd src/vga_pixelgen.vhd \
src/vga_pixelreader.vhd src/vga.vhd \
src/bresenham_dp.vhd \
src/rasterizer_l_fsm.vhd src/rasterizer_l.vhd \
src/toplevel.vhd
SYN_INFILES=
PSMFILES=

181
bresenham_dp_tb.wcfg Normal file
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@@ -0,0 +1,181 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="bresenham_dp_tb" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="36" />
<wvobject fp_name="/bresenham_dp_tb/DUT/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/x0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x0[15:0]</obj_property>
<obj_property name="ObjectShortName">x0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/x1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x1[15:0]</obj_property>
<obj_property name="ObjectShortName">x1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i0[15:0]</obj_property>
<obj_property name="ObjectShortName">i0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i1[15:0]</obj_property>
<obj_property name="ObjectShortName">i1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/load_dx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load_dx</obj_property>
<obj_property name="ObjectShortName">load_dx</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/load_di" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load_di</obj_property>
<obj_property name="ObjectShortName">load_di</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/init" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">init</obj_property>
<obj_property name="ObjectShortName">init</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/next_x" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_x</obj_property>
<obj_property name="ObjectShortName">next_x</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i[15:0]</obj_property>
<obj_property name="ObjectShortName">i[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/x" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x[15:0]</obj_property>
<obj_property name="ObjectShortName">x[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/neg_dx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">neg_dx[15:0]</obj_property>
<obj_property name="ObjectShortName">neg_dx[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/x1_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x1_int[15:0]</obj_property>
<obj_property name="ObjectShortName">x1_int[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/di" type="array" db_ref_id="1">
<obj_property name="ElementShortName">di[1:0]</obj_property>
<obj_property name="ObjectShortName">di[1:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/si" type="array" db_ref_id="1">
<obj_property name="ElementShortName">si[1:0]</obj_property>
<obj_property name="ObjectShortName">si[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/d_sub_1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_1[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/d_sub_2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_2[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_2[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/d_sub" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/d_sub_abs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_abs[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_abs[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err[1:0]</obj_property>
<obj_property name="ObjectShortName">err[1:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_next[15:0]</obj_property>
<obj_property name="ObjectShortName">err_next[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err_add_1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_add_1[15:0]</obj_property>
<obj_property name="ObjectShortName">err_add_1[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err_add_2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_add_2[15:0]</obj_property>
<obj_property name="ObjectShortName">err_add_2[15:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/looping" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">looping</obj_property>
<obj_property name="ObjectShortName">looping</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err_gt_negdx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">err_gt_negdx</obj_property>
<obj_property name="ObjectShortName">err_gt_negdx</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/err_ge_di" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">err_ge_di</obj_property>
<obj_property name="ObjectShortName">err_ge_di</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_int[1:0]</obj_property>
<obj_property name="ObjectShortName">i_int[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_next[15:0]</obj_property>
<obj_property name="ObjectShortName">i_next[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/i_add" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_add[15:0]</obj_property>
<obj_property name="ObjectShortName">i_add[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/x_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x_int[15:0]</obj_property>
<obj_property name="ObjectShortName">x_int[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/step_done_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">step_done_next[1:0]</obj_property>
<obj_property name="ObjectShortName">step_done_next[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/step_done" type="array" db_ref_id="1">
<obj_property name="ElementShortName">step_done[1:0]</obj_property>
<obj_property name="ObjectShortName">step_done[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/channel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">channel[0:0]</obj_property>
<obj_property name="ObjectShortName">channel[0:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/next_step" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_step</obj_property>
<obj_property name="ObjectShortName">next_step</obj_property>
</wvobject>
<wvobject fp_name="/bresenham_dp_tb/DUT/next_step_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_step_next</obj_property>
<obj_property name="ObjectShortName">next_step_next</obj_property>
</wvobject>
</wave_config>

348
rasterizer_l_tb.wcfg Normal file
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@@ -0,0 +1,348 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="rasterizer_l_tb" />
<top_module name="std_logic_1164" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="39" />
<wvobject fp_name="/rasterizer_l_tb/DUT/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/x0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x0[15:0]</obj_property>
<obj_property name="ObjectShortName">x0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/x1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x1[15:0]</obj_property>
<obj_property name="ObjectShortName">x1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/a0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a0[15:0]</obj_property>
<obj_property name="ObjectShortName">a0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/a1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a1[15:0]</obj_property>
<obj_property name="ObjectShortName">a1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/b0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b0[15:0]</obj_property>
<obj_property name="ObjectShortName">b0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/b1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b1[15:0]</obj_property>
<obj_property name="ObjectShortName">b1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/c0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c0[15:0]</obj_property>
<obj_property name="ObjectShortName">c0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/c1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c1[15:0]</obj_property>
<obj_property name="ObjectShortName">c1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/z0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">z0[15:0]</obj_property>
<obj_property name="ObjectShortName">z0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/z1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">z1[15:0]</obj_property>
<obj_property name="ObjectShortName">z1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/in_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_valid</obj_property>
<obj_property name="ObjectShortName">in_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/in_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_ack</obj_property>
<obj_property name="ObjectShortName">in_ack</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/x" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x[15:0]</obj_property>
<obj_property name="ObjectShortName">x[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[15:0]</obj_property>
<obj_property name="ObjectShortName">a[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b[15:0]</obj_property>
<obj_property name="ObjectShortName">b[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/c" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c[15:0]</obj_property>
<obj_property name="ObjectShortName">c[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/z" type="array" db_ref_id="1">
<obj_property name="ElementShortName">z[15:0]</obj_property>
<obj_property name="ObjectShortName">z[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/x_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">x_valid</obj_property>
<obj_property name="ObjectShortName">x_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/a_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">a_valid</obj_property>
<obj_property name="ObjectShortName">a_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/b_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">b_valid</obj_property>
<obj_property name="ObjectShortName">b_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/c_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">c_valid</obj_property>
<obj_property name="ObjectShortName">c_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/z_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">z_valid</obj_property>
<obj_property name="ObjectShortName">z_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_x" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bh_x[15:0]</obj_property>
<obj_property name="ObjectShortName">bh_x[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bh_i[15:0]</obj_property>
<obj_property name="ObjectShortName">bh_i[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bh_i0[15:0]</obj_property>
<obj_property name="ObjectShortName">bh_i0[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_i1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bh_i1[15:0]</obj_property>
<obj_property name="ObjectShortName">bh_i1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_load_dx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_load_dx</obj_property>
<obj_property name="ObjectShortName">bh_load_dx</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_load_di" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_load_di</obj_property>
<obj_property name="ObjectShortName">bh_load_di</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_init" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_init</obj_property>
<obj_property name="ObjectShortName">bh_init</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_valid</obj_property>
<obj_property name="ObjectShortName">bh_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_next_x" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_next_x</obj_property>
<obj_property name="ObjectShortName">bh_next_x</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_done</obj_property>
<obj_property name="ObjectShortName">bh_done</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_out_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bh_out_en</obj_property>
<obj_property name="ObjectShortName">bh_out_en</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bh_ch" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bh_ch[1:0]</obj_property>
<obj_property name="ObjectShortName">bh_ch[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/load_ch" type="array" db_ref_id="1">
<obj_property name="ElementShortName">load_ch[1:0]</obj_property>
<obj_property name="ObjectShortName">load_ch[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/out_start" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_start</obj_property>
<obj_property name="ObjectShortName">out_start</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/out_end" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_end</obj_property>
<obj_property name="ObjectShortName">out_end</obj_property>
</wvobject>
<wvobject fp_name="group78" type="group">
<obj_property name="label">bresenham_dp</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/x0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x0[15:0]</obj_property>
<obj_property name="ObjectShortName">x0[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/x1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x1[15:0]</obj_property>
<obj_property name="ObjectShortName">x1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i0[15:0]</obj_property>
<obj_property name="ObjectShortName">i0[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i1[15:0]</obj_property>
<obj_property name="ObjectShortName">i1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/load_dx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load_dx</obj_property>
<obj_property name="ObjectShortName">load_dx</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/load_di" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load_di</obj_property>
<obj_property name="ObjectShortName">load_di</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/init" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">init</obj_property>
<obj_property name="ObjectShortName">init</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/next_x" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_x</obj_property>
<obj_property name="ObjectShortName">next_x</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_valid</obj_property>
<obj_property name="ObjectShortName">i_valid</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i[15:0]</obj_property>
<obj_property name="ObjectShortName">i[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/x" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x[15:0]</obj_property>
<obj_property name="ObjectShortName">x[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/ch" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ch[1:0]</obj_property>
<obj_property name="ObjectShortName">ch[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/neg_dx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">neg_dx[15:0]</obj_property>
<obj_property name="ObjectShortName">neg_dx[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/x1_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x1_int[15:0]</obj_property>
<obj_property name="ObjectShortName">x1_int[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/di" type="array" db_ref_id="1">
<obj_property name="ElementShortName">di[3:0]</obj_property>
<obj_property name="ObjectShortName">di[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/si" type="array" db_ref_id="1">
<obj_property name="ElementShortName">si[3:0]</obj_property>
<obj_property name="ObjectShortName">si[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/d_sub_1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_1[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/d_sub_2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_2[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_2[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/d_sub" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/d_sub_abs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d_sub_abs[15:0]</obj_property>
<obj_property name="ObjectShortName">d_sub_abs[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err[3:0]</obj_property>
<obj_property name="ObjectShortName">err[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_next[15:0]</obj_property>
<obj_property name="ObjectShortName">err_next[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err_add_1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_add_1[15:0]</obj_property>
<obj_property name="ObjectShortName">err_add_1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err_add_2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">err_add_2[15:0]</obj_property>
<obj_property name="ObjectShortName">err_add_2[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/looping" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">looping</obj_property>
<obj_property name="ObjectShortName">looping</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err_gt_negdx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">err_gt_negdx</obj_property>
<obj_property name="ObjectShortName">err_gt_negdx</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/err_ge_di" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">err_ge_di</obj_property>
<obj_property name="ObjectShortName">err_ge_di</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_int[3:0]</obj_property>
<obj_property name="ObjectShortName">i_int[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_next[15:0]</obj_property>
<obj_property name="ObjectShortName">i_next[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/i_add" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_add[15:0]</obj_property>
<obj_property name="ObjectShortName">i_add[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/x_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">x_int[15:0]</obj_property>
<obj_property name="ObjectShortName">x_int[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/step_done_next" type="array" db_ref_id="1">
<obj_property name="ElementShortName">step_done_next[3:0]</obj_property>
<obj_property name="ObjectShortName">step_done_next[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/step_done" type="array" db_ref_id="1">
<obj_property name="ElementShortName">step_done[3:0]</obj_property>
<obj_property name="ObjectShortName">step_done[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/channel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">channel[1:0]</obj_property>
<obj_property name="ObjectShortName">channel[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/next_step" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_step</obj_property>
<obj_property name="ObjectShortName">next_step</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/next_step_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">next_step_next</obj_property>
<obj_property name="ObjectShortName">next_step_next</obj_property>
</wvobject>
<wvobject fp_name="/rasterizer_l_tb/DUT/bresenham_dp_1/init_dly" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">init_dly</obj_property>
<obj_property name="ObjectShortName">init_dly</obj_property>
</wvobject>
</wvobject>
</wave_config>

274
src/bresenham_dp.vhd
View File

@@ -32,6 +32,10 @@ use IEEE.NUMERIC_STD.ALL;
--use UNISIM.VComponents.all;
entity bresenham_dp is
generic (
channels : integer := 5;
channels_ln2 : integer := 3;
preinc_x : boolean := true);
port(
clk : in STD_LOGIC;
@@ -42,124 +46,184 @@ entity bresenham_dp is
load_di : in std_logic;
init : in std_logic;
next_x : out std_logic;
i_valid : out std_logic;
done : out std_logic;
i : out unsigned(15 downto 0);
x : out unsigned(15 downto 0));
x : out unsigned(15 downto 0);
ch : out unsigned(channels_ln2-1 downto 0));
end bresenham_dp;
architecture Behavioral of bresenham_dp is
signal neg_dx : signed(15 downto 0) := to_signed(0, 16);
signal x1_int : unsigned(15 downto 0) := to_unsigned(0, 16);
signal di : signed(15 downto 0) := to_signed(0, 16);
signal si : std_logic := '0';
signal neg_dx : signed(15 downto 0) := to_signed(0, 16);
signal x1_int : unsigned(15 downto 0) := to_unsigned(0, 16);
type di_a is array(channels-1 downto 0) of signed(15 downto 0);
signal di : di_a := (others => to_signed(0, 16));
signal si : std_logic_vector(channels-1 downto 0) := (others => '0');
signal d_sub_1, d_sub_2 : unsigned(15 downto 0) := to_unsigned(0, 16);
signal d_sub, d_sub_abs : signed(15 downto 0) := to_signed(0, 16);
signal d_sub_1, d_sub_2 : unsigned(15 downto 0) := to_unsigned(0, 16);
signal d_sub, d_sub_abs : signed(15 downto 0) := to_signed(0, 16);
signal err, err_next : signed(15 downto 0) := to_signed(0, 16);
signal err_add_1, err_add_2 : signed(15 downto 0) := to_signed(0, 16);
signal looping : std_logic := '0';
signal err_gt_negdx, err_ge_di : std_logic := '0';
type err_a is array(channels-1 downto 0) of signed(15 downto 0);
signal err : err_a := (others => to_signed(0, 16));
signal err_next : signed(15 downto 0) := to_signed(0, 16);
signal err_add_1, err_add_2 : signed(15 downto 0) := to_signed(0, 16);
signal looping : std_logic := '0';
signal err_gt_negdx, err_ge_di : std_logic := '0';
signal i_int, i_next, i_add : unsigned(15 downto 0) := to_unsigned(0, 16);
type i_a is array(channels-1 downto 0) of unsigned(15 downto 0);
signal i_int : i_a := (others => to_unsigned(0, 16));
signal i_next, i_add : unsigned(15 downto 0) := to_unsigned(0, 16);
signal x_int : unsigned(15 downto 0) := to_unsigned(0, 16);
signal x_int : unsigned(15 downto 0) := to_unsigned(0, 16);
signal step_done_next, step_done : std_logic_vector(channels-1 downto 0) := (others => '0');
signal channel : unsigned(channels_ln2-1 downto 0) := to_unsigned(0, channels_ln2);
constant channels_1 : std_logic_vector(channels-1 downto 0) := (others => '1');
signal next_step, next_step_next : std_logic := '0';
signal init_dly : std_logic := '0';
begin
x_reg : process(clk)
begin
if rising_edge(clk) then
if load_dx = '1' then
neg_dx <= d_sub;
x1_int <= x1;
end if;
end if;
end process x_reg;
di_reg : process(clk)
begin
if rising_edge(clk) then
if load_di = '1' then
di <= d_sub_abs;
end if;
end if;
end process di_reg;
si_reg : process(clk)
begin
if rising_edge(clk) then
if load_di = '1' then
si <= d_sub(d_sub'left);
end if;
end if;
end process si_reg;
d_sub_1 <= x1 when load_dx = '1' else
i0;
d_sub_2 <= x0 when load_dx = '1' else
i1;
d_sub <= signed(d_sub_1) - signed(d_sub_2);
x_reg : process(clk)
begin
if rising_edge(clk) then
if load_dx = '1' then
neg_dx <= d_sub;
x1_int <= x1;
end if;
end if;
end process x_reg;
di_reg : process(clk)
begin
if rising_edge(clk) then
if load_di = '1' then
di <= di(channels-2 downto 0) & d_sub_abs;
else
di <= di(channels-2 downto 0) & di(channels-1);
end if;
end if;
end process di_reg;
si_reg : process(clk)
begin
if rising_edge(clk) then
if load_di = '1' then
si <= si(channels-2 downto 0) & d_sub(d_sub'left);
else
si <= si(channels-2 downto 0) & si(channels-1);
end if;
end if;
end process si_reg;
d_sub_1 <= x0 when load_dx = '1' else
i1;
d_sub_2 <= x1 when load_dx = '1' else
i0;
d_sub <= signed(d_sub_1) - signed(d_sub_2);
d_sub_abs <= d_sub when d_sub(d_sub'left) = '0' else
-d_sub;
d_sub_abs <= d_sub when d_sub(d_sub'left) = '0' else
-d_sub;
err_reg : process(clk)
begin
if rising_edge(clk) then
err <= err_next;
err_reg : process(clk)
begin
if rising_edge(clk) then
err <= err(channels-2 downto 0) & err_next;
end if;
end process err_reg;
err_add_1 <= neg_dx when looping = '1' or init = '1' else
di(channels-1);
err_add_2 <= di(channels-1) when init = '1' else
err(channels-1);
err_next <= err(channels-1) when step_done(to_integer(channel)) = '1' else
err_add_1 + err_add_2;
err_gt_negdx <= '1' when (err(channels-1) & "0") > neg_dx else
'0';
err_ge_di <= '1' when (err(channels-1) & "0") >= di(channels-1) else
'0';
looping <= err_gt_negdx and err_ge_di;
i_reg : process(clk)
begin
if rising_edge(clk) then
if load_di = '1' or init = '0' then
i_int <= i_int(channels-2 downto 0) & i_next;
end if;
end if;
end process i_reg;
i_add <= i_int(channels-1) + 1 when si(channels-1) = '0' else
i_int(channels-1) - 1;
i_next <= i0 when load_di = '1' else
i_int(channels-1) when step_done(to_integer(channel)) = '1' or looping = '0' else
i_add;
step_done_reg : process(clk)
begin
if rising_edge(clk) then
step_done <= step_done_next;
next_step <= next_step_next;
end if;
end process step_done_reg;
step_done_gen : for i in 0 to channels-1 generate
step_done_next(i) <= '0' when next_step = '1' or init = '1' else
'1' when channel = i and looping = '0' else
step_done(i);
end generate;
next_step_next <= '1' when step_done_next = channels_1 else
'0';
channel_ctr : process(clk)
begin
if rising_edge(clk) then
if init = '1' then
channel <= to_unsigned(0, channels_ln2);
else
channel <= (channel + 1) mod channels;
end if;
end if;
end process channel_ctr;
init_dly_reg : process(clk)
begin
if rising_edge(clk) then
init_dly <= init;
end if;
end process init_dly_reg;
x_ctr : process(clk)
begin
if rising_edge(clk) then
done <= '0';
if load_di = '1' then
x_int <= x0;
elsif next_step = '1' or (preinc_x and init = '1' and init_dly = '0') then
if x_int+1 >= x1_int then
done <= '1';
end if;
end process err_reg;
err_add_1 <= neg_dx when looping = '1' or init = '1' else
di;
err_add_2 <= di when init = '1' else
err;
err_next <= err_add_1 + err_add_2;
err_gt_negdx <= '1' when (err & "0") > neg_dx else
'0';
err_ge_di <= '1' when (err & "0") >= di else
'0';
looping <= err_gt_negdx and err_ge_di;
i_reg : process(clk)
begin
if rising_edge(clk) then
if init = '1' or looping = '1' then
i_int <= i_next;
end if;
end if;
end process i_reg;
i_add <= i_int + 1 when si = '0' else
i_int - 1;
i_next <= i0 when init = '1' else
i_add;
x_ctr : process(clk)
begin
if rising_edge(clk) then
done <= '0';
if load_di = '1' then
x_int <= x0;
elsif looping = '0' or init = '1' then
if x_int = x1_int then
done <= '1';
end if;
x_int <= x_int+1;
end if;
end if;
end process x_ctr;
i <= i_int;
x <= x_int;
next_x <= not looping;
x_int <= x_int+1;
end if;
end if;
end process x_ctr;
i <= i_int(channels-1);
x <= x_int;
i_valid <= not init and not looping and not step_done(to_integer(channel));
next_x <= next_step;
ch <= channel;
end Behavioral;

139
src/rasterizer_l.vhd Normal file
View File

@@ -0,0 +1,139 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/22/2013 05:49:49 PM
-- Design Name:
-- Module Name: rasterizer_l - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rasterizer_l is
generic (
dontcare : std_logic := '-');
port (
clk : in std_logic;
x0, x1 : in unsigned(15 downto 0);
a0, a1 : in unsigned(15 downto 0);
b0, b1 : in unsigned(15 downto 0);
c0, c1 : in unsigned(15 downto 0);
z0, z1 : in unsigned(15 downto 0);
in_valid : in std_logic;
in_ack : out std_logic;
x, a, b,c, z : out unsigned(15 downto 0);
x_valid, a_valid, b_valid, c_valid, z_valid : out std_logic);
end rasterizer_l;
architecture mixed of rasterizer_l is
signal bh_x: unsigned(15 downto 0);
signal bh_i, bh_i0, bh_i1 : unsigned(15 downto 0);
signal bh_load_dx, bh_load_di, bh_init, bh_valid, bh_next_x, bh_done, bh_out_en : std_logic;
signal bh_ch, load_ch : unsigned(1 downto 0);
signal out_start, out_end : std_logic;
begin
bh_i0 <= a0 when load_ch = 0 else
b0 when load_ch = 1 else
c0 when load_ch = 2 else
z0;-- when load_ch = 3
bh_i1 <= a1 when load_ch = 0 else
b1 when load_ch = 1 else
c1 when load_ch = 2 else
z1;-- when load_ch = 3
rasterizer_l_fsm_1: entity work.rasterizer_l_fsm
generic map (
dontcare => dontcare)
port map (
clk => clk,
in_valid => in_valid,
bh_done => bh_done,
bh_load_dx => bh_load_dx,
bh_load_di => bh_load_di,
bh_init => bh_init,
out_start => out_start,
out_end => out_end,
in_ack => in_ack,
bh_out_en => bh_out_en,
load_ch => load_ch);
bresenham_dp_1: entity work.bresenham_dp
generic map (
channels => 4,
channels_ln2 => 2,
preinc_x => false)
port map (
clk => clk,
x0 => x0,
x1 => x1,
i0 => bh_i0,
i1 => bh_i1,
load_dx => bh_load_dx,
load_di => bh_load_di,
init => bh_init,
i_valid => bh_valid,
next_x => bh_next_x,
done => bh_done,
i => bh_i,
x => bh_x,
ch => bh_ch);
x <= x0 when out_start = '1' else
x1 when out_end = '1' else
bh_x;
a <= a0 when out_start = '1' else
a1 when out_end = '1' else
bh_i;
b <= b0 when out_start = '1' else
b1 when out_end = '1' else
bh_i;
c <= c0 when out_start = '1' else
c1 when out_end = '1' else
bh_i;
z <= z0 when out_start = '1' else
z1 when out_end = '1' else
bh_i;
x_valid <= '1' when out_start = '1' or out_end = '1' else
bh_next_x and bh_out_en;
a_valid <= '1' when out_start = '1' or out_end = '1' else
bh_valid and bh_out_en when bh_ch = 0 else
'0';
b_valid <= '1' when out_start = '1' or out_end = '1' else
bh_valid and bh_out_en when bh_ch = 1 else
'0';
c_valid <= '1' when out_start = '1' or out_end = '1' else
bh_valid and bh_out_en when bh_ch = 2 else
'0';
z_valid <= '1' when out_start = '1' or out_end = '1' else
bh_valid and bh_out_en when bh_ch = 3 else
'0';
end mixed;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/22/2013 05:49:49 PM
-- Design Name:
-- Module Name: rasterizer_l - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rasterizer_l_fsm is
generic (
dontcare : std_logic := '-');
port (
clk : in std_logic;
in_valid : in std_logic;
bh_done : in std_logic;
bh_load_dx : out std_logic := '0';
bh_load_di : out std_logic := '0';
bh_init : out std_logic := '0';
out_start : out std_logic := '0';
out_end : out std_logic := '0';
in_ack : out std_logic := '0';
bh_out_en : out std_logic := '0';
load_ch : out unsigned(1 downto 0));
end rasterizer_l_fsm;
architecture behavioral of rasterizer_l_fsm is
type states is (S_IDLE, S_INIT1, S_INIT2, S_INIT3, S_INIT4, S_WORK, S_WAIT);
signal state : states := S_IDLE;
signal ch_ctr : unsigned(1 downto 0) := (others => dontcare);
begin
fsm : process(clk)
begin
if rising_edge(clk) then
bh_load_dx <= '0';
bh_load_di <= '0';
bh_init <= '0';
bh_out_en <= '0';
out_start <= '0';
out_end <= '0';
in_ack <= '0';
ch_ctr <= (others => dontcare);
case state is
when S_IDLE =>
if in_valid = '1' then
bh_load_dx <= '1';
--out_start <= '1';
state <= S_INIT1;
end if;
when S_INIT1 =>
ch_ctr <= to_unsigned(0, 2);
bh_load_di <= '1';
state <= S_INIT2;
when S_INIT2 =>
ch_ctr <= ch_ctr + 1;
bh_load_di <= '1';
if ch_ctr = 2 then
state <= S_INIT3;
end if;
when S_INIT3 =>
ch_ctr <= to_unsigned(0, 2);
bh_init <= '1';
state <= S_INIT4;
when S_INIT4 =>
ch_ctr <= ch_ctr + 1;
bh_init <= '1';
if ch_ctr = 2 then
state <= S_WORK;
end if;
when S_WORK =>
bh_out_en <= '1';
if bh_done = '1' then
bh_out_en <= '0';
out_end <= '1';
in_ack <= '1';
state <= S_WAIT;
end if;
when S_WAIT =>
state <= S_IDLE;
end case;
end if;
end process fsm;
output : process(state)
begin
end process output;
load_ch <= ch_ctr;
end behavioral;

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-------------------------------------------------------------------------------
-- Title : Testbench for design "bresenham_dp"
-- Project :
-------------------------------------------------------------------------------
-- File : bresenham_dp_tb.vhd
-- Author : Matthias Blankertz <matthias@matthias-tp>
-- Company :
-- Created : 2013-03-25
-- Last update: 2013-03-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-25 1.0 matthias Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity bresenham_dp_tb is
end entity bresenham_dp_tb;
-------------------------------------------------------------------------------
architecture testbench of bresenham_dp_tb is
-- component generics
constant channels : integer := 2;
constant channels_ln2 : integer := 1;
-- component ports
signal clk : STD_LOGIC := '0';
signal x0, x1 : unsigned(15 downto 0);
signal i0, i1 : unsigned(15 downto 0);
signal load_dx : std_logic := '0';
signal load_di : std_logic := '0';
signal init : std_logic := '0';
signal next_x : std_logic;
signal done : std_logic;
signal i : unsigned(15 downto 0);
signal x : unsigned(15 downto 0);
begin -- architecture testbench
-- component instantiation
DUT: entity work.bresenham_dp
generic map (
channels => channels,
channels_ln2 => channels_ln2)
port map (
clk => clk,
x0 => x0,
x1 => x1,
i0 => i0,
i1 => i1,
load_dx => load_dx,
load_di => load_di,
init => init,
next_x => next_x,
done => done,
i => i,
x => x);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
x0 <= to_unsigned(1,16);
x1 <= to_unsigned(5,16);
load_dx <= '1';
wait until rising_edge(clk);
load_dx <= '0';
i0 <= to_unsigned(2, 16);
i1 <= to_unsigned(0, 16);
load_di <= '1';
wait until rising_edge(clk);
i0 <= to_unsigned(0, 16);
i1 <= to_unsigned(15,16);
load_di <= '1';
wait until rising_edge(clk);
load_di <= '0';
init <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
init <= '0';
wait until rising_edge(clk);
wait;
end process WaveGen_Proc;
end architecture testbench;
-------------------------------------------------------------------------------
configuration bresenham_dp_tb_testbench_cfg of bresenham_dp_tb is
for testbench
end for;
end bresenham_dp_tb_testbench_cfg;
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
-- Title : Testbench for design "rasterizer_l"
-- Project :
-------------------------------------------------------------------------------
-- File : rasterizer_l_tb.vhd
-- Author : Matthias Blankertz <matthias@matthias-tp>
-- Company :
-- Created : 2013-03-26
-- Last update: 2013-03-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-26 1.0 matthias Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity rasterizer_l_tb is
end entity rasterizer_l_tb;
-------------------------------------------------------------------------------
architecture testbench of rasterizer_l_tb is
-- component generics
constant dontcare : std_logic := '0';
-- component ports
signal clk : std_logic := '1';
signal x0, x1 : unsigned(15 downto 0);
signal a0, a1 : unsigned(15 downto 0);
signal b0, b1 : unsigned(15 downto 0);
signal c0, c1 : unsigned(15 downto 0);
signal z0, z1 : unsigned(15 downto 0);
signal in_valid : std_logic := '0';
signal in_ack : std_logic;
signal x, a, b, c, z : unsigned(15 downto 0);
signal x_valid, a_valid, b_valid, c_valid, z_valid : std_logic;
begin -- architecture testbench
-- component instantiation
DUT: entity work.rasterizer_l
generic map (
dontcare => dontcare)
port map (
clk => clk,
x0 => x0,
x1 => x1,
a0 => a0,
a1 => a1,
b0 => b0,
b1 => b1,
c0 => c0,
c1 => c1,
z0 => z0,
z1 => z1,
in_valid => in_valid,
in_ack => in_ack,
x => x,
a => a,
b => b,
c => c,
z => z,
x_valid => x_valid,
a_valid => a_valid,
b_valid => b_valid,
c_valid => c_valid,
z_valid => z_valid);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait until rising_edge(clk);
x0 <= to_unsigned(23, 16);
x1 <= to_unsigned(42, 16);
a0 <= to_unsigned(0, 16);
a1 <= to_unsigned(255, 16);
b0 <= to_unsigned(255, 16);
b1 <= to_unsigned(0, 16);
c0 <= to_unsigned(1024, 16);
c1 <= to_unsigned(1025, 16);
z0 <= to_unsigned(0, 16);
z1 <= to_unsigned(9000, 16);
in_valid <= '1';
wait until rising_edge(clk);
while in_ack = '0' loop
wait until rising_edge(clk);
end loop;
in_valid <= '0';
wait until rising_edge(clk);
x0 <= to_unsigned(0, 16);
x1 <= to_unsigned(4, 16);
a0 <= to_unsigned(2, 16);
a1 <= to_unsigned(0, 16);
b0 <= to_unsigned(0, 16);
b1 <= to_unsigned(15, 16);
c0 <= to_unsigned(0, 16);
c1 <= to_unsigned(0, 16);
z0 <= to_unsigned(42, 16);
z1 <= to_unsigned(42, 16);
in_valid <= '1';
wait until rising_edge(clk);
wait;
end process WaveGen_Proc;
output : process
variable av, bv, cv, zv : boolean := false;
variable al, bl, cl, zl : unsigned(15 downto 0);
begin
while true loop
wait until rising_edge(clk);
if a_valid = '1' then
assert not av report "Multiple a valid for one x" severity error;
av := true;
al := a;
end if;
if b_valid = '1' then
assert not bv report "Multiple b valid for one x" severity error;
bv := true;
bl := b;
end if;
if c_valid = '1' then
assert not cv report "Multiple c valid for one x" severity error;
cv := true;
cl := c;
end if;
if z_valid = '1' then
assert not zv report "Multiple z valid for one x" severity error;
zv := true;
zl := z;
end if;
if x_valid = '1' then
assert av and bv and cv and zv report "not all variables recieved for x" severity error;
av := false;
bv := false;
cv := false;
zv := false;
report "@" & integer'image(to_integer(x)) & ": " & integer'image(to_integer(al)) & "," &
integer'image(to_integer(bl)) & "," & integer'image(to_integer(cl)) & "," &
integer'image(to_integer(zl));
end if;
end loop;
end process output;
end architecture testbench;
-------------------------------------------------------------------------------
configuration rasterizer_l_tb_testbench_cfg of rasterizer_l_tb is
for testbench
end for;
end rasterizer_l_tb_testbench_cfg;
-------------------------------------------------------------------------------