matthias/2d_display_engine-new
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- Fixed wishbone interconnect generator

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- Fixed accidental latches in wb_ddr_ctrl_wb_sc.vhd
- Updated cpu for new manual cache flush
This commit is contained in:
Matthias Blankertz
2013-03-21 16:06:53 +01:00
parent 37d63b062d
commit a6b20d3311
7 changed files with 342 additions and 307 deletions
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2
Makefile
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@@ -117,7 +117,7 @@ timing: $(TWRFILE)
#%.vhd: %.psm
# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
src/wb_interconnect.vhd: src/wishbone.defines
src/wb_interconnect.vhd: src/wishbone.defines tools/wishbone.pl
cd src && ../tools/wishbone.pl -nogui wishbone.defines
coregen/%.vhd coregen/%.ngc: coregen/%.xco coregen/coregen.cgp

4
planahead_postsynth.tcl
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@@ -1,4 +0,0 @@
create_project -force -part xc3s700an-fgg484-4 postsynth planahead
set_property design_mode GateLvl [current_fileset]
import_files 2d_display_engine.ngc coregen/wb_ddr_ctrl_wb_from_ddr.ngc coregen/wb_ddr_ctrl_wb_to_ddr.ngc coregen/vga_pixeldata_fifo.ngc
import_files -fileset constrs_1 constr/2d_display_engine.ucf constr/vhdl_bl4.ucf

10
src/cpu.vhd
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@@ -110,7 +110,6 @@ fill_fb : process(clk_i)
end if;
state <= S_WRITE1;
else
adr <= 0;
state <= S_FLUSH1;
end if;
end if;
@@ -122,7 +121,7 @@ fill_fb : process(clk_i)
wbm_o.we_o <= '1';
wbm_o.sel_o <= (others => '1');
wbm_o.adr_o <= std_logic_vector(to_unsigned(cc_adr,wbm_o.adr_o'length));
wbm_o.dat_o <= std_logic_vector(to_unsigned(adr*4,32));
wbm_o.dat_o <= x"00000002";
state <= S_FLUSH2;
when S_FLUSH2 =>
@@ -132,12 +131,7 @@ fill_fb : process(clk_i)
if wbm_i.ack_i = '1' then
wbm_o.stb_o <= '0';
wbm_o.cyc_o <= '0';
if adr < 153583 then
adr <= adr + 16;
state <= S_FLUSH1;
else
state <= S_DONE;
end if;
state <= S_DONE;
end if;
when S_DONE =>
null;

6
src/wb_ddr_ctrl_wb_sc.vhd
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@@ -171,7 +171,7 @@ begin
ddr_be <= (others => '0');
ddr_din <= cfe_mem_dat_o;
ddr_adr_int(22 downto 3) <= vga_adr_reg when bus_owner = B_VGA else
cfe_adr_reg when bus_owner = B_CFE;-- else
cfe_adr_reg;-- when bus_owner = B_CFE else
--(others => dontcare);
ddr_adr_int(2 downto 0) <= std_logic_vector(to_unsigned(out_ctr, 3));
ddr_we_int <= '1' when bus_owner = B_CFE and cfe_wrrq_reg = '1' else
@@ -184,10 +184,10 @@ begin
'0';
ddr_adr <= ddr_adr_int when in_read = '1' else
ddr_adr_dly(write_delay-1) when in_write = '1';-- else
ddr_adr_dly(write_delay-1);-- when in_write = '1' else
--(others => dontcare);
ddr_we <= ddr_we_int when in_read = '1' else
ddr_we_dly(write_delay-1) when in_write = '1';-- else
ddr_we_dly(write_delay-1);-- when in_write = '1' else
--dontcare;
fifo_to_ddr_write <= fifo_to_ddr_write_int when in_read = '1' else
fifo_to_ddr_write_dly(write_delay-1) and not fifo_to_ddr_full when in_write = '1' else

26
src/wishbone.defines
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@@ -78,14 +78,14 @@ slave ram
lock_i=0
err_o=0
rty_o=0
baseadr=0x000800
baseadr=0x0000800
size=0x800
end slave ram
# SDRAM controller memory port
slave sdram_ctrl
# SDRAM controller Cache control port
slave sdram_ctrl_cc
type=rw
adr_i_hi=25
adr_i_hi=2
adr_i_lo=2
tga_i=1
tgc_i=1
@@ -93,14 +93,14 @@ slave sdram_ctrl
lock_i=0
err_o=0
rty_o=0
baseadr=0x4000000
size=0x4000000
end slave sdram_ctrl
baseadr=0x8000000
size=0x8
end slave sdram_ctrl_cc
# SDRAM controller Cache control port
slave sdram_ctrl_cc
# SDRAM controller memory port
slave sdram_ctrl
type=rw
adr_i_hi=2
adr_i_hi=25
adr_i_lo=2
tga_i=0
tgc_i=0
@@ -108,6 +108,6 @@ slave sdram_ctrl_cc
lock_i=0
err_o=0
rty_o=0
baseadr=0x8000000
size=0x10
end slave sdram_ctrl_cc
baseadr=0x4000000
size=0x4000000
end slave sdram_ctrl

518
tools/wishbone.pl
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File diff suppressed because it is too large Load Diff

83
toplevel_tb.wcfg
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@@ -176,6 +176,32 @@
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.we_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.we_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.sel_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.sel_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.adr_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.adr_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.cyc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.stb_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_ctrl_wbs_i</obj_property>
@@ -198,14 +224,6 @@
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.adr_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.bte_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.bte_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cti_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_i</obj_property>
<obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cyc_i</obj_property>
@@ -313,6 +331,7 @@
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/pixeldata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pixeldata[63:0]</obj_property>
<obj_property name="ObjectShortName">pixeldata[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/fifo_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_write</obj_property>
@@ -337,6 +356,7 @@
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">mem_adr[19:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_ack</obj_property>
@@ -732,6 +752,10 @@
<obj_property name="ElementShortName">set_dirty</obj_property>
<obj_property name="ObjectShortName">set_dirty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_clean" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_clean</obj_property>
<obj_property name="ObjectShortName">set_clean</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_valid</obj_property>
<obj_property name="ObjectShortName">set_valid</obj_property>
@@ -756,10 +780,6 @@
<obj_property name="ElementShortName">cache_to_mem</obj_property>
<obj_property name="ObjectShortName">cache_to_mem</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc</obj_property>
<obj_property name="ObjectShortName">user_cc</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag_eq_num_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adr_tag_eq_num_dirty</obj_property>
<obj_property name="ObjectShortName">adr_tag_eq_num_dirty</obj_property>
@@ -780,6 +800,31 @@
<obj_property name="ElementShortName">mem_wrrq_int</obj_property>
<obj_property name="ObjectShortName">mem_wrrq_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mfi</obj_property>
<obj_property name="ObjectShortName">mfi</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_index" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mfi_index[4:0]</obj_property>
<obj_property name="ObjectShortName">mfi_index[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mfi_num[0:0]</obj_property>
<obj_property name="ObjectShortName">mfi_num[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_index_ctr_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mfi_index_ctr_en</obj_property>
<obj_property name="ObjectShortName">mfi_index_ctr_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num_ctr_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mfi_num_ctr_en</obj_property>
<obj_property name="ObjectShortName">mfi_num_ctr_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mfi_num_dirty</obj_property>
<obj_property name="ObjectShortName">mfi_num_dirty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_flush" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_req_flush</obj_property>
<obj_property name="ObjectShortName">user_cc_req_flush</obj_property>
@@ -788,9 +833,9 @@
<obj_property name="ElementShortName">user_cc_req_inval</obj_property>
<obj_property name="ObjectShortName">user_cc_req_inval</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_read</obj_property>
<obj_property name="ObjectShortName">user_cc_read</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_none" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_req_none</obj_property>
<obj_property name="ObjectShortName">user_cc_req_none</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wb_ddr_ctrl_wb_sc_fe_fsm_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
@@ -868,6 +913,7 @@
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout[63:0]</obj_property>
<obj_property name="ObjectShortName">dout[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr[22:0]</obj_property>
@@ -905,6 +951,7 @@
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_address[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address_en</obj_property>
@@ -913,6 +960,7 @@
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_en</obj_property>
@@ -945,6 +993,7 @@
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout_low[31:0]</obj_property>
<obj_property name="ObjectShortName">dout_low[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_low_en</obj_property>
@@ -958,10 +1007,6 @@
<obj_property name="ElementShortName">ctrl_state</obj_property>
<obj_property name="ObjectShortName">ctrl_state</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
<obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_pending</obj_property>
<obj_property name="ObjectShortName">fifo_pending</obj_property>