matthias/2d_display_engine-new
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- WIP: New cache for CPU

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- sysClk reduced to 45 MHz
This commit is contained in:
Matthias Blankertz
2013-06-19 15:01:32 +02:00
parent 0a96ce78f0
commit 6cd60cf263
8 changed files with 162 additions and 67 deletions
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2
Makefile
View File

@@ -236,7 +236,7 @@ isim/work/%.vdb: coregen/%.vhd
$(FUSE) work.$(@:.exe=) -o $@ $(FUSEOPTS)
clean:
rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB) xst/
rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB) ; rm -rf xst/
cd firmware && make clean
.PSEUDO=all synth impl timing clean bit impact

11
constr/2d_display_engine.ucf
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@@ -3,13 +3,12 @@ NET "CLKIN_50MHZ" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20.0 ns HIGH 50 %;
# NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%;
TIMEGRP "vga" OFFSET = OUT 10ns AFTER "CLKIN_50MHZ" RISING;
TIMEGRP "vga" OFFSET = OUT 10ns AFTER "vgaClk" RISING;
TIMEGRP "cpu_wbm_adr_o"=FFS("cpu_inst/mblite_wbm_inst/wbm_o.adr_o_*");
NET "uart_inst/ACK_O" TPTHRU = "uart_ack_o" ;
TIMEGRP "allff" = FFS("*");
TIMESPEC TSfalsewb1 = FROM "cpu_wbm_adr_o" THRU "uart_ack_o" TO FFS("*") TS_CLK_50*2;
#TIMEGRP "cpu_wbm_adr_o"=FFS("cpu_inst/mblite_wbm_inst/wbm_o.adr_o_*");
#NET "uart_inst/ACK_O" TPTHRU = "uart_ack_o" ;
#TIMEGRP "allff" = FFS("*");
#TIMESPEC TSfalsewb1 = FROM "cpu_wbm_adr_o" THRU "uart_ack_o" TO FFS("*") TS_CLK_50*2;
# Location and I/O defs
# Clocks

18
mblite_cache_tb.wcfg
View File

@@ -24,7 +24,7 @@
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="82" />
<WVObjectSize size="86" />
<wvobject fp_name="/mblite_cache_tb/DUT/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
@@ -113,6 +113,10 @@
<obj_property name="ElementShortName">instr_reset</obj_property>
<obj_property name="ObjectShortName">instr_reset</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/instr_reset_wait" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">instr_reset_wait</obj_property>
<obj_property name="ObjectShortName">instr_reset_wait</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/reset_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">reset_ctr</obj_property>
<obj_property name="ObjectShortName">reset_ctr</obj_property>
@@ -312,6 +316,10 @@
<obj_property name="ObjectShortName">cpui_adr_o_mux[25:2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/cpui_adr_o2_dly" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpui_adr_o2_dly</obj_property>
<obj_property name="ObjectShortName">cpui_adr_o2_dly</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/cpud_adr_o_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpud_adr_o_reg[25:2]</obj_property>
<obj_property name="ObjectShortName">cpud_adr_o_reg[25:2]</obj_property>
@@ -348,6 +356,10 @@
<obj_property name="ElementShortName">cpud_we_o_mux</obj_property>
<obj_property name="ObjectShortName">cpud_we_o_mux</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/cpud_adr_o2_dly" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpud_adr_o2_dly</obj_property>
<obj_property name="ObjectShortName">cpud_adr_o2_dly</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/data_miss" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_miss</obj_property>
<obj_property name="ObjectShortName">data_miss</obj_property>
@@ -360,6 +372,10 @@
<obj_property name="ElementShortName">eject[0:0]</obj_property>
<obj_property name="ObjectShortName">eject[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/eject_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">eject_reg[0:0]</obj_property>
<obj_property name="ObjectShortName">eject_reg[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/mblite_cache_tb/DUT/eject_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">eject_dirty</obj_property>
<obj_property name="ObjectShortName">eject_dirty</obj_property>

14
src/clk_reset.vhd
View File

@@ -46,7 +46,7 @@ end clk_reset;
architecture Behavioral of clk_reset is
signal locked_int, rst_int : std_logic := '0';
signal clkOut50_int, clkOut25_int : std_logic;
signal clkOut50_int, clkOut25_int, clkOutFX_int : std_logic;
constant reset_pulse_width : integer := 3;
@@ -63,13 +63,17 @@ begin
dcm50 : DCM_SP
generic map (
CLKIN_PERIOD => 20.0,
CLKDV_DIVIDE => 2.0
CLKDV_DIVIDE => 2.0,
-- CLKFX = 45 MHz
CLKFX_DIVIDE => 10,
CLKFX_MULTIPLY => 9
)
port map (
CLKIN => clkIn50,
CLKFB => clkOut50_int,
CLK0 => clkOut50_int,
CLKDV => clkOut25_int,
CLKFX => clkOutFX_int,
LOCKED => locked_int,
RST => rst_int,
@@ -103,7 +107,7 @@ dcm_rst_gen : process(clkIn50)
end if;
end process dcm_rst_gen;
sys_rst_gen : process(clkOut50_int, locked_int)
sys_rst_gen : process(clkOutFX_int, locked_int)
begin
if locked_int = '0' then
-- hold system in reset while DCM is not locked
@@ -111,7 +115,7 @@ sys_rst_gen : process(clkOut50_int, locked_int)
sys_in_rst <= '1';
sys_in_rst_ctr <= reset_pulse_width-1;
rstIn_sync_sys <= (others => '0');
elsif rising_edge(clkOut50_int) then
elsif rising_edge(clkOutFX_int) then
-- sync rstIn to clkOut50 clock
rstIn_sync_sys <= rstIn_sync_sys(rstIn_sync_sys'left-1 downto 0) & rstIn;
@@ -132,6 +136,6 @@ sys_rst_gen : process(clkOut50_int, locked_int)
end if;
end process sys_rst_gen;
sysClk50 <= clkOut50_int;
sysClk50 <= clkOutFX_int;
sysClk25 <= clkOut25_int;
end Behavioral;

134
src/mblite_cache.vhd
View File

@@ -56,6 +56,7 @@ entity mblite_cache is
cpud_ena_o : in std_logic;
cpu_wait : out std_logic;
cpu_waiting : in std_logic;
mem_rdrq : out std_logic;
mem_wrrq : out std_logic;
@@ -109,7 +110,7 @@ architecture Mixed of mblite_cache is
signal cc_valid_dib, cc_valid_doa, cc_valid_dob : std_logic_vector(1 downto 0) := (others => '0');
signal cc_dirty_dib, cc_dirty_dob : std_logic_vector(1 downto 0) := (others => dontcare);
signal cpu_wait_int, instr_wait, data_wait : std_logic := '0';
signal instr_wait, data_wait : std_logic := '0';
signal instr_hit, data_hit : std_logic_vector(1 downto 0);
signal mem_active : std_logic := '0';
@@ -138,10 +139,11 @@ architecture Mixed of mblite_cache is
signal data_miss : std_logic := '0';
type mem_states is (S_IDLE, S_STARTDLY, S_START, S_READMEM);
type mem_states is (S_IDLE, S_START, S_READMEM, S_WRITEMEM);
signal mem_state : mem_states := S_IDLE;
signal eject, eject_reg : unsigned(0 downto 0);
signal eject_dirty : std_logic;
signal eject_tag : std_logic_vector(tag_width-1 downto 0);
signal adr_reg : std_logic_vector(25 downto 2);
signal ctr : integer range 0 to 3;
begin
@@ -222,14 +224,14 @@ begin
instr_regs : process(clk_i)
begin
if rising_edge(clk_i) then
if cpu_wait_int = '0' and cpui_ena_o = '1' then
if cpu_waiting = '0' and cpui_ena_o = '1' then
cpui_adr_o_reg <= cpui_adr_o;
end if;
cpui_adr_o2_dly <= cpui_adr_o_mux(2);
end if;
end process instr_regs;
cpui_adr_o_mux <= cpui_adr_o when cpu_wait_int = '0' else
cpui_adr_o_mux <= cpui_adr_o when cpu_waiting = '0' else
cpui_adr_o_reg;
cc_adra <= unsigned(cpui_adr_o_mux((lines_ln2-1)+line_size_ln2+2 downto line_size_ln2+3));
@@ -260,7 +262,7 @@ begin
instr_wait <= '0';
reset_ctr <= 0;
else
if cpu_wait_int = '0' and cpui_ena_o = '1' and instr_reset = '1' then
if cpu_waiting = '0' and cpui_ena_o = '1' and instr_reset = '1' then
-- Send reset vector to CPU
instr_wait <= '0';
if instr_reset_wait = '1' then
@@ -292,7 +294,7 @@ begin
data_regs : process(clk_i)
begin
if rising_edge(clk_i) then
if cpu_wait_int = '0' and cpud_ena_o = '1' then
if cpu_waiting = '0' and cpud_ena_o = '1' then
cpud_adr_o_reg <= cpud_adr_o;
cpud_dat_o_reg <= cpud_dat_o;
cpud_sel_o_reg <= cpud_sel_o;
@@ -302,13 +304,13 @@ begin
end if;
end process data_regs;
cpud_adr_o_mux <= cpud_adr_o when cpu_wait_int = '0' else
cpud_adr_o_mux <= cpud_adr_o when cpu_waiting = '0' else
cpud_adr_o_reg;
cpud_dat_o_mux <= cpud_dat_o when cpu_wait_int = '0' else
cpud_dat_o_mux <= cpud_dat_o when cpu_waiting = '0' else
cpud_dat_o_reg;
cpud_sel_o_mux <= cpud_sel_o when cpu_wait_int = '0' else
cpud_sel_o_mux <= cpud_sel_o when cpu_waiting = '0' else
cpud_sel_o_reg;
cpud_we_o_mux <= cpud_we_o when cpu_wait_int = '0' else
cpud_we_o_mux <= cpud_we_o when cpu_waiting = '0' else
cpud_we_o_reg;
-- CC ram address
@@ -369,16 +371,40 @@ begin
-------------------------------------------------------------------------------
-- LRU tracker
-------------------------------------------------------------------------------
cc_lru_adr_lc <= cc_adrb_dp when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit /= "00" else
cc_adra;
cc_lru_di <= "1" when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit = "01" else
"0" when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit = "10" else
"1" when cpu_wait_int = '0' and cpui_ena_o = '1' and instr_hit = "01" else
"0" when cpu_wait_int = '0' and cpui_ena_o = '1' and instr_hit = "10" else
cc_lru_do;
cc_lru_we <= ((not cpu_wait_int and cpud_ena_o and (data_hit(0) or data_hit(1))) or
(not cpu_wait_int and cpui_ena_o and (instr_hit(0) or instr_hit(1)))) and
not mem_active;
--cc_lru_adr_lc <= cc_adrb_dp when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit /= "00" else
-- cc_adra;
--cc_lru_di <= "1" when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit = "01" else
-- "0" when cpu_wait_int = '0' and cpud_ena_o = '1' and data_hit = "10" else
-- "1" when cpu_wait_int = '0' and cpui_ena_o = '1' and instr_hit = "01" else
-- "0" when cpu_wait_int = '0' and cpui_ena_o = '1' and instr_hit = "10" else
-- cc_lru_do;
--cc_lru_we <= ((not cpu_wait_int and cpud_ena_o and (data_hit(0) or data_hit(1))) or
-- (not cpu_wait_int and cpui_ena_o and (instr_hit(0) or instr_hit(1)))) and
-- not mem_active;
lru_upd : process(clk_i)
begin
if rising_edge(clk_i) then
if cpu_waiting = '0' and cpud_ena_o = '1' and data_hit /= "00" then
cc_lru_adr_lc <= cc_adrb_dp;
else
cc_lru_adr_lc <= cc_adra;
end if;
if cpu_waiting = '0' and cpud_ena_o = '1' and data_hit = "01" then
cc_lru_di <= "1";
elsif cpu_waiting = '0' and cpud_ena_o = '1' and data_hit = "10" then
cc_lru_di <= "0";
elsif cpu_waiting = '0' and cpui_ena_o = '1' and instr_hit = "01" then
cc_lru_di <= "1";
elsif cpu_waiting = '0' and cpui_ena_o = '1' and instr_hit = "10" then
cc_lru_di <= "0";
else
cc_lru_di <= cc_lru_do;
end if;
cc_lru_we <= ((not cpu_waiting and cpud_ena_o and (data_hit(0) or data_hit(1))) or
(not cpu_waiting and cpui_ena_o and (instr_hit(0) or instr_hit(1)))) and
not mem_active;
end if;
end process lru_upd;
@@ -393,6 +419,10 @@ begin
eject_dirty <= '-' when mem_active = '0' else
cc_dirty_dob(to_integer(eject)) and cc_valid_dob(to_integer(eject));
eject_tag <= (others => dontcare) when mem_active = '0' else
cc_tag_dob(tag_width-1 downto 0) when eject = "0" else
cc_tag_dob(2*tag_width-1 downto tag_width);
mem_active <= '0' when mem_state = S_IDLE else
'1';
@@ -405,24 +435,36 @@ begin
cc_valid_dib_mp <= cc_valid_dob;
cc_dirty_dib_mp <= cc_dirty_dob;
cc_tag_dib_mp <= cc_tag_dob;
if eject = 0 then
cc_valid_dib_mp(0) <= '1';
cc_dirty_dib_mp(0) <= '0';
cc_tag_dib_mp(tag_width-1 downto 0) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
else
cc_valid_dib_mp(1) <= '1';
cc_dirty_dib_mp(1) <= '0';
cc_tag_dib_mp(2*tag_width-1 downto tag_width) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
if mem_state = S_READMEM then
if eject = 0 then
cc_valid_dib_mp(0) <= '1';
cc_dirty_dib_mp(0) <= '0';
cc_tag_dib_mp(tag_width-1 downto 0) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
else
cc_valid_dib_mp(1) <= '1';
cc_dirty_dib_mp(1) <= '0';
cc_tag_dib_mp(2*tag_width-1 downto tag_width) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
end if;
else -- if mem_state = S_WRITEMEM
if eject = 0 then
--cc_valid_dib_mp(0) <= '1';
cc_dirty_dib_mp(0) <= '0';
--cc_tag_dib_mp(tag_width-1 downto 0) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
else
--cc_valid_dib_mp(1) <= '1';
cc_dirty_dib_mp(1) <= '0';
--cc_tag_dib_mp(2*tag_width-1 downto tag_width) <= adr_reg(25 downto (lines_ln2-1)+line_size_ln2+3);
end if;
end if;
end if;
end process cc_upd;
cc_we_mp <= '1' when mem_ack = '1' and ctr = 3 and mem_state = S_READMEM else
cc_we_mp <= '1' when mem_ack = '1' and ctr = 3 and (mem_state = S_READMEM or mem_state = S_WRITEMEM) else
'0';
cram_dib_mp <= mem_dat_i;
cram_bwe_mp <= x"ff" when mem_ack = '1' else
cram_bwe_mp <= x"ff" when mem_ack = '1' and mem_state = S_READMEM else
x"00";
-- Index
cram_adrb_mp(lines_ln2+line_size_ln2-1 downto line_size_ln2+1)
@@ -431,7 +473,11 @@ begin
cram_adrb_mp(line_size_ln2 downto line_size_ln2) <= std_logic_vector(eject_reg);
-- Offset
cram_adrb_mp(line_size_ln2-1 downto 0)
<= std_logic_vector(unsigned(adr_reg(line_size_ln2+2 downto 3))+to_unsigned(ctr, 2));
<= std_logic_vector(unsigned(adr_reg(line_size_ln2+2 downto 3))+to_unsigned(ctr+1, 2))
when mem_state = S_WRITEMEM and mem_ack = '1' else
std_logic_vector(unsigned(adr_reg(line_size_ln2+2 downto 3))+to_unsigned(ctr, 2));
mem_dat_o <= cram_dob;
mem_ctrl : process(clk_i)
begin
@@ -448,20 +494,19 @@ begin
if (cpui_ena_o = '1' or instr_wait = '1') and instr_hit = "00" and instr_reset = '0' then
-- Instruction read miss
adr_reg <= cpui_adr_o_mux;
mem_state <= S_STARTDLY;
mem_state <= S_START;
elsif (cpud_ena_o = '1' or data_miss = '1') and data_hit = "00" then
-- Data miss
adr_reg <= cpud_adr_o_mux;
mem_state <= S_STARTDLY;
mem_state <= S_START;
end if;
when S_STARTDLY =>
mem_state <= S_START;
when S_START =>
if eject_dirty = '1' then
-- Flush line
--mem_wrrq <= '1';
--mem_adr <=
null;
mem_wrrq <= '1';
mem_adr <= eject_tag & adr_reg((lines_ln2-1)+line_size_ln2+2 downto line_size_ln2+1);
ctr <= 0;
mem_state <= S_WRITEMEM;
else
-- Fetch new line
mem_rdrq <= '1';
@@ -478,6 +523,14 @@ begin
ctr <= ctr + 1;
end if;
end if;
when S_WRITEMEM =>
if mem_ack = '1' then
if ctr = 3 then
mem_state <= S_IDLE;
else
ctr <= ctr + 1;
end if;
end if;
end case;
end if;
@@ -487,7 +540,6 @@ begin
end process mem_ctrl;
cpu_wait_int <= instr_wait or data_wait;
cpu_wait <= cpu_wait_int;
cpu_wait <= instr_wait or data_wait;
end Mixed;

20
src/mblite_wbm.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-08
-- Last update: 2013-06-08
-- Last update: 2013-06-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -40,7 +40,8 @@ entity mblite_wbm is
cpu_we_o : in std_logic;
cpu_ena_o : in std_logic;
cpu_wait : out std_logic;
cpu_wait : out std_logic := '0';
cpu_waiting : in std_logic;
wbm_i : in cpu_wbm_i_type;
wbm_o : out cpu_wbm_o_type
@@ -48,12 +49,11 @@ entity mblite_wbm is
end mblite_wbm;
architecture Behavioral of mblite_wbm is
signal wb_in_cyc, cpu_wait_int : std_logic := '0';
signal wb_in_cyc : std_logic := '0';
signal q_adr_o : std_logic_vector(26 downto 0);
signal q_dat_o : std_logic_vector(31 downto 0);
signal q_sel_o : std_logic_vector(3 downto 0);
signal q_we_o : std_logic;
signal queued : std_logic := '0';
begin
wbm : process(clk_i)
@@ -61,17 +61,18 @@ begin
if rising_edge(clk_i) then
if rst_i = '1' then
wb_in_cyc <= '0';
queued <= '0';
cpu_wait <= '0';
else
if wb_in_cyc = '1' and wbm_i.ack_i = '1' then
-- Wishbone cycle complete
wb_in_cyc <= '0';
cpu_wait <= '0';
elsif cpu_ena_o = '1' and wbm_i.ack_i = '1' then
-- CPU request, but WB bus not free
null;
cpu_wait <= '1';
elsif wb_in_cyc = '1' and cpu_ena_o = '1' then
-- back-to-back requests
queued <= '1';
null;
elsif cpu_ena_o = '1' and wb_in_cyc = '0' and wbm_i.ack_i = '0' then
-- new request
wbm_o.adr_o <= cpu_adr_o;
@@ -79,7 +80,7 @@ begin
wbm_o.sel_o <= cpu_sel_o;
wbm_o.dat_o <= cpu_dat_o;
wb_in_cyc <= '1';
queued <= '0';
cpu_wait <= '1';
end if;
end if;
end if;
@@ -88,8 +89,7 @@ begin
wbm_o.cyc_o <= wb_in_cyc or wbm_i.ack_i;
wbm_o.stb_o <= wb_in_cyc;
cpu_wait_int <= (not wb_in_cyc and wbm_i.ack_i and cpu_ena_o) or (wb_in_cyc and not wbm_i.ack_i) or (wb_in_cyc and cpu_ena_o);
cpu_wait <= cpu_wait_int;-- or queued;
--cpu_wait <= (not wb_in_cyc and wbm_i.ack_i and cpu_ena_o) or (wb_in_cyc and not wbm_i.ack_i) or (wb_in_cyc and cpu_ena_o);
cpu_dat_i <= wbm_i.dat_i;

10
src/mblite_wrapper.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-02
-- Last update: 2013-06-08
-- Last update: 2013-06-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -70,6 +70,8 @@ architecture Mixed of mblite_wrapper is
signal wb_cpu_wait, c_cpu_wait : std_logic := '0';
signal mb_adr_o27_dly, mb_iadr_o27_dly : std_logic;
signal cpu_wait : std_logic;
begin
dly : process(clk_i)
begin
@@ -92,9 +94,11 @@ begin
clk_i => clk_i
);
cpu_wait <= not (wb_cpu_wait or c_cpu_wait);
mb_dmem_i.dat_i <= wb_dat_i when mb_adr_o27_dly = '1' else
cd_dat_i;
mb_dmem_i.ena_i <= not (wb_cpu_wait or c_cpu_wait);
mb_dmem_i.ena_i <= cpu_wait;
mb_imem_i.dat_i <= rom_dat_i when mb_iadr_o27_dly = '1' else
ci_dat_i;
@@ -119,6 +123,7 @@ begin
cpud_ena_o => cd_ena_o,
cpu_wait => c_cpu_wait,
cpu_waiting => cpu_wait,
mem_rdrq => mem_rdrq,
mem_wrrq => mem_wrrq,
@@ -156,6 +161,7 @@ begin
cpu_ena_o => wb_ena_o,
cpu_wait => wb_cpu_wait,
cpu_waiting => cpu_wait,
wbm_i => wbm_i,
wbm_o => wbm_o

20
tb/mblite_cache_tb.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-08
-- Last update: 2013-06-08
-- Last update: 2013-06-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -183,6 +183,24 @@ begin -- architecture testbench
while cpu_wait = '1' loop
wait until rising_edge(clk_i);
end loop;
adr := to_unsigned(16#010080#, 24);
cpud_adr_o <= std_logic_vector(adr);
cpud_ena_o <= '1';
while adr < 16#010090# loop
wait until rising_edge(clk_i);
if cpu_wait = '0' then
adr := adr + 1;
end if;
cpud_adr_o <= std_logic_vector(adr);
cpud_ena_o <= '1';
--wait until rising_edge(clk_i);
end loop;
cpud_ena_o <= '0';
while cpu_wait = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
wait;
end process cpu_gen;