341 lines
14 KiB
Makefile
Executable File
341 lines
14 KiB
Makefile
Executable File
COMMON_INFILES=ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
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src/wishbone.vhd \
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src/wb_ram.vhd \
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src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
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src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
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src/wb_ddr_ctrl_wb_sc.vhd src/vga_syncgen.vhd src/vga_pixelgen.vhd \
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src/vga_pixelreader.vhd src/vga.vhd \
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src/bresenham_dp.vhd \
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src/rasterizer_l_fsm.vhd src/rasterizer_l.vhd \
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src/mblite_rom_data.vhd src/mblite_rom.vhd src/mblite_wbm.vhd src/mblite_cache_ram.vhd src/mblite_cache.vhd \
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src/mblite_wrapper.vhd src/pio.vhd \
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src/uart/fifo16x8.vhd src/uart/par2ser.vhd src/uart/pulsegen325.vhd src/uart/readctrl.vhd src/uart/ser2par.vhd \
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src/uart/writectrl.vhd src/uart/uart.vhd src/uart/uart_wbc.vhd \
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src/ram_16x64.vhd src/wb_mem_bridge.vhd \
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src/spi.vhd \
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src/toplevel.vhd
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MBLITE_INFILES=mblite/config_Pkg.vhd mblite/std_Pkg.vhd mblite/core_Pkg.vhd \
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mblite/dsram.vhd mblite/gprf.vhd mblite/fetch.vhd mblite/decode.vhd mblite/execute.vhd mblite/mem.vhd \
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mblite/core.vhd mblite/core_wb_adapter.vhd mblite/core_wb.vhd
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SYN_INFILES=
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PSMFILES=
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CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr vga_pixeldata_fifo
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BMMFILE=mblite_rom.bmm
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BMMFILE_BD=mblite_rom_bd.bmm
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MEMFILE=test.mem
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PRJNAME=2d_display_engine
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NGCFILE=$(PRJNAME).ngc
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XSTFILE=$(PRJNAME).xst
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XCF=constr/$(PRJNAME).xcf
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UCF=constr/$(PRJNAME).ucf constr/vhdl_bl4.ucf
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PCFFILE=$(PRJNAME).pcf
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NGDFILE=$(PRJNAME).ngd
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NCDFILE=$(PRJNAME).ncd
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NCDFILE_R=$(PRJNAME)_routed.ncd
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BITFILE=$(PRJNAME).bit
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FWBITFILE=$(PRJNAME)_bd.bit
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TWRFILE=$(PRJNAME).twr
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TWXFILE=$(PRJNAME).twx
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PRJFILE=$(PRJNAME).prj
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PART=xc3s700an-fgg484-4
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XSTOPTS="-ifn $(PRJFILE) \
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-ifmt mixed \
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-top toplevel \
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-ofn $(NGCFILE) \
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-ofmt NGC \
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-p $(PART) \
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-opt_mode Area \
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-opt_level 2 \
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-fsm_encoding auto \
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-sd coregen/ \
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-read_cores yes \
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-rtlview no \
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-iob auto \
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-keep_hierarchy soft \
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-register_balancing yes \
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-auto_bram_packing yes \
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$(addprefix -uc ,$(XCF))"
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NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
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MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on -xe n -detail
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PAROPTS=-ol high -xe n
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BITGENOPTS=
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TRACEOPTS=-v -u 10
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SIM_INFILES=src/sim_bmppack.vhd
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SIM_INFILES_VLOG=ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
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GHDLOPTS=--workdir=ghdl -Pghdl --ieee=synopsys -fexplicit
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VLOGCOMPOPTS=-d x512Mb -d sg5E -d x16 -d MAX_MEM
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VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental
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FUSEOPTS=-L ieee_proposed=isim/ieee_proposed
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SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
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SIMALLFILES=$(SIM_INFILES) $(COMMON_INFILES)
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#SIMALLFILESXDB=isim/ieee_proposed/std_logic_1164_additions.vdb \
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$(addprefis isim/mblite/,$(notdir $(MBLITE_INFILES:.vhd=.vdb))) \
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$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
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$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
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CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
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CORESNGC=$(addprefix coregen/,$(addsuffix .ngc,$(CORES)))
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XILPATH=
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COREGEN=$(XILPATH)coregen
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XST=$(XILPATH)xst
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NGDBUILD=$(XILPATH)ngdbuild
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MAP=$(XILPATH)map
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PAR=$(XILPATH)par
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BITGEN=$(XILPATH)bitgen
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TRCE=$(XILPATH)trce
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VHPCOMP=$(XILPATH)vhpcomp
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VLOGCOMP=$(XILPATH)vlogcomp
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FUSE=$(XILPATH)fuse
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DATA2MEM=$(XILPATH)data2mem
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FWFILE=firmware/fw.elf
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.SECONDARY:
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all: $(FWBITFILE)
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synth: $(NGCFILE)
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impl: $(NCDFILE_R)
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timing: $(TWRFILE)
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firmware/fw.elf:
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cd firmware && make fw.elf
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bit: $(BITFILE)
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impact: $(FWBITFILE) impact.cmd
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impact -batch impact.cmd
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#%.vhd: %.psm
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# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
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src/wb_interconnect.vhd: src/wishbone.defines tools/wishbone.pl
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cd src && dos2unix wishbone.defines && ../tools/wishbone.pl -nogui wishbone.defines
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src/mblite_rom_data.vhd: $(BMMFILE) # $(FWFILE)
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$(DATA2MEM) -bm $(BMMFILE) -bd $(FWFILE) -o h $@
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coregen/%.vhd coregen/%.ngc: coregen/%.xco coregen/coregen.cgp
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$(COREGEN) -p coregen/coregen.cgp -b $< -r
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planahead_postsynth.tcl: Makefile
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rm -f $@; echo -e "create_project -force -part $(PART) postsynth planahead\n\
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set_property design_mode GateLvl [current_fileset]\n\
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import_files $(NGCFILE) $(CORESNGC)\n\
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import_files -fileset constrs_1 $(UCF)" > $@
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planahead_postimpl.tcl: Makefile
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rm -f $@; echo -e "create_project -force -part $(PART) postimpl planahead\n\
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set_property design_mode GateLvl [current_fileset]\n\
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add_files $(NGCFILE) $(CORESNGC)\n\
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import_files -fileset constrs_1 $(UCF)\n\
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import_as_run -run impl_1 -twx $(TWXFILE) $(NCDFILE_R)" > $@
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planahead_postsynth: planahead_postsynth.tcl $(NGCFILE) $(UCF)
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planAhead -source planahead_postsynth.tcl
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planahead_postimpl: planahead_postimpl.tcl $(NCDFILE) $(UCF) $(NCDFILE_R) $(TWXFILE)
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planAhead -source planahead_postimpl.tcl
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$(PRJFILE): Makefile
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rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done;
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for i in $(MBLITE_INFILES); do echo "vhdl mblite" $$i >> $(PRJFILE); done;
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$(XSTFILE): Makefile
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rm -f $@; echo "run $(XSTOPTS)" > $@
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$(NGCFILE): $(SYNALLFILES) $(MBLITE_INFILES) $(PRJFILE) $(XSTFILE) $(XCF) $(CORESNGC)
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$(XST) -ifn $(XSTFILE)
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$(NGDFILE): $(NGCFILE) $(UCF) $(CORESNGC) $(BMMFILE)
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$(NGDBUILD) $(NGDOPTS) -bm $(BMMFILE) $(NGCFILE) $(NGDFILE)
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$(PCFFILE) $(NCDFILE) : $(NGDFILE)
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$(MAP) $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
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$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
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$(PAR) -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
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$(BITFILE) $(BMMFILE_BD): $(NCDFILE_R) $(PCFFILE)
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$(BITGEN) -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
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$(FWBITFILE): $(BITFILE) $(BMMFILE_BD) $(FWFILE)
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$(DATA2MEM) -bm $(BMMFILE_BD) -bt $(BITFILE) -bd $(FWFILE) -o b $@
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$(TWRFILE) $(TWXFILE): $(NCDFILE_R) $(PCFFILE)
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$(TRCE) $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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isim/ieee_proposed/std_logic_1164_additions.vdb: tools/std_logic_1164_additions.vhdl
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$(VHPCOMP) --work ieee_proposed=isim/ieee_proposed $< $(VHPCOMPOPTS)
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isim/mblite/%.vdb: mblite/%.vhd
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$(VHPCOMP) --work mblite=isim/mblite $< $(VHPCOMPOPTS)
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isim/work/intercon_package.vdb isim/work/interconnect.vdb: src/wishbone.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/vhdl_bl4_dqs_delay.vdb: ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/mblite_rom_data_pkg_mblite_rom.vdb: src/mblite_rom_data.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: src/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: src/uart/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: zy2000/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: ddr2_sdram/vhdl_bl4/example_design/rtl/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.sdb: ddr2_sdram/vhdl_bl4/example_design/sim/%.v
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$(VLOGCOMP) $< $(VLOGCOMPOPTS)
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isim/work/%.vdb: tb/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: coregen/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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%.exe: $(CORESVDB) isim/work/%.vdb #$(SIMALLFILESXDB)
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$(FUSE) work.$(@:.exe=) -o $@ $(FUSEOPTS)
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clean:
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rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB) ; rm -rf xst/
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cd firmware && make clean
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.PSEUDO=all synth impl timing clean bit impact
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isim/work/toplevel_tb.vdb: isim/work/sim_bmppack.vdb isim/work/toplevel.vdb
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isim/work/wb_ddr_ctrl_wb_sc_tb.vdb: isim/work/wb_ddr_ctrl_wb_sc.vdb
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isim/work/spi_tb.vdb: isim/work/intercon_package.vdb isim/work/spi.vdb
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isim/work/wb_mem_bridge_tb.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_wb_sc.vdb isim/work/wb_mem_bridge.vdb
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isim/work/mblite_cache_tb.vdb: isim/mblite/core_Pkg.vdb isim/work/intercon_package.vdb isim/work/mblite_cache.vdb
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isim/work/toplevel.vdb: isim/work/mblite_wrapper.vdb isim/work/intercon_package.vdb isim/work/interconnect.vdb isim/work/clk_reset.vdb isim/work/wb_ddr_ctrl.vdb isim/work/vga.vdb isim/work/wb_ram.vdb isim/work/pio.vdb isim/work/uart_wbc.vdb isim/work/wb_mem_bridge.vdb isim/work/spi.vdb
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isim/work/mblite_wrapper.vdb: isim/work/intercon_package.vdb isim/mblite/core_Pkg.vdb isim/work/mblite_rom.vdb isim/work/mblite_wbm.vdb isim/mblite/core.vdb isim/work/mblite_cache.vdb
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isim/work/mblite_cache.vdb: isim/work/intercon_package.vdb isim/mblite/core_Pkg.vdb isim/work/mblite_cache_ram.vdb
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isim/work/mblite_rom.vdb: isim/work/intercon_package.vdb isim/work/mblite_rom_data_pkg_mblite_rom.vdb
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isim/mblite/core_wb.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb isim/mblite/core_wb_adapter.vdb isim/mblite/core.vdb
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isim/mblite/core_Pkg.vdb: isim/mblite/config_Pkg.vdb isim/mblite/std_Pkg.vdb
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isim/mblite/core_wb_adapter.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb
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isim/mblite/core.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/fetch.vdb isim/mblite/decode.vdb isim/mblite/execute.vdb isim/mblite/mem.vdb
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isim/mblite/fetch.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb
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isim/mblite/decode.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb isim/mblite/gprf.vdb
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isim/mblite/gprf.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb isim/mblite/dsram.vdb
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isim/mblite/dsram.vdb: isim/mblite/std_Pkg.vdb
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isim/mblite/execute.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb
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isim/mblite/mem.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb
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isim/work/mblite_wbm.vdb: isim/work/intercon_package.vdb isim/mblite/core_Pkg.vdb
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isim/work/wb_ddr_ctrl.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_ddrwrap.vdb isim/work/wb_ddr_ctrl_wb.vdb
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isim/work/wb_ddr_ctrl_ddrwrap.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_infrastructure_top.vdb isim/work/vhdl_bl4_top_0.vdb
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isim/work/vhdl_bl4_infrastructure_top.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_clk_dcm.vdb isim/work/vhdl_bl4_cal_top.vdb
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isim/work/vhdl_bl4_cal_top.vdb: isim/work/vhdl_bl4_cal_ctl.vdb isim/work/vhdl_bl4_tap_dly.vdb
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isim/work/vhdl_bl4_top_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_controller_0.vdb isim/work/vhdl_bl4_data_path_0.vdb isim/work/vhdl_bl4_infrastructure.vdb isim/work/vhdl_bl4_iobs_0.vdb
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isim/work/vhdl_bl4_controller_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_data_path_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_data_read_0.vdb isim/work/vhdl_bl4_data_read_controller_0.vdb isim/work/vhdl_bl4_data_write_0.vdb
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isim/work/vhdl_bl4_data_read_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_rd_gray_cntr.vdb isim/work/vhdl_bl4_ram8d_0.vdb isim/work/vhdl_bl4_ram8d_1.vdb
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isim/work/vhdl_bl4_ram8d_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_ram8d_1.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_data_read_controller_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_dqs_delay.vdb isim/work/vhdl_bl4_wr_gray_cntr.vdb isim/work/vhdl_bl4_fifo_0_wr_en_0.vdb isim/work/vhdl_bl4_fifo_1_wr_en_0.vdb
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isim/work/vhdl_bl4_data_write_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_iobs_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_infrastructure_iobs_0.vdb isim/work/vhdl_bl4_controller_iobs_0.vdb isim/work/vhdl_bl4_data_path_iobs_0.vdb
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isim/work/vhdl_bl4_infrastructure_iobs_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_controller_iobs_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb
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isim/work/vhdl_bl4_data_path_iobs_0.vdb: isim/work/vhdl_bl4_parameters_0.vdb isim/work/vhdl_bl4_s3_dqs_iob.vdb isim/work/vhdl_bl4_s3_dq_iob.vdb isim/work/vhdl_bl4_s3_dm_iob.vdb
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isim/work/wb_ddr_ctrl_wb.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_wb_from_ddr.vdb isim/work/wb_ddr_ctrl_wb_to_ddr.vdb isim/work/wb_ddr_ctrl_wb_sc.vdb isim/work/wb_ddr_ctrl_wb_dc.vdb
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#isim/work/wb_ddr_ctrl_wb_sc.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_wb_sc_fe.vdb
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#isim/work/wb_ddr_ctrl_wb_sc_fe.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_wb_sc_fe_fsm.vdb isim/work/wb_ddr_ctrl_wb_sc_fe_ram.vdb
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#isim/work/wb_ddr_ctrl_wb_sc_fe_fsm.vdb: isim/work/intercon_package.vdb
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isim/work/wb_ddr_ctrl_wb_dc.vdb: isim/work/wb_ddr_ctrl_wb_dc_fsm.vdb
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isim/work/vga.vdb: isim/work/intercon_package.vdb isim/work/vga_pixelreader.vdb isim/work/vga_pixeldata_fifo.vdb isim/work/vga_syncgen.vdb isim/work/vga_pixelgen.vdb
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isim/work/vga_pixelreader.vdb: isim/work/intercon_package.vdb
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isim/work/wb_ram.vdb: isim/work/intercon_package.vdb
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isim/work/pio.vdb: isim/work/intercon_package.vdb
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isim/work/uart_wbc.vdb: isim/work/uart.vdb
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isim/work/uart.vdb: isim/work/ser2par.vdb isim/work/readctrl.vdb isim/work/fifo16x8.vdb isim/work/pulsegen325.vdb isim/work/par2ser.vdb isim/work/writectrl.vdb
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isim/work/wb_mem_bridge.vdb: isim/work/intercon_package.vdb isim/work/ram_16x64.vdb
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isim/work/spi.vdb: isim/work/fifo16x8.vdb
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