Matthias Blankertz
0a96ce78f0
- WIP: New cache for CPU - Memory controller now supports modulu bursts and different burst lengths - WIP: Timing problems...
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
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#include <stdbool.h>
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#include "uart.h"
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static volatile unsigned char *_uart_sreg = (unsigned char *)0x08010021;
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static volatile unsigned char *_uart_dreg = (unsigned char *)0x08010020;
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static bool _uart_writefull() {
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return ((*_uart_sreg&0x2)==0x2);
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}
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static bool _uart_readempty() {
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return ((*_uart_sreg&0x4)==0x4);
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}
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void uart_writeb(unsigned char b) {
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while(_uart_writefull()) {}
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*_uart_dreg = b;
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}
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void uart_writes(const char *str) {
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while(*str)
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uart_writeb(*str++);
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}
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unsigned char uart_readb() {
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while(_uart_readempty()) {}
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return *_uart_dreg;
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}
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// Read from uart until a newline is recvd. The recvd line is written into buf
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// as a 0-terminated string. If more than max bytes are read, the bytes already
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// read are returned in buf and the function returns false.
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bool uart_readline(char *buf, int max) {
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int i = 0;
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while(i < max-1) {
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buf[i] = uart_readb();
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if(buf[i] == '\n') {
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buf[i] = '\0';
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return true;
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}
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++i;
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}
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buf[i] = '\0';
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return false;
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}
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