Matthias Blankertz 0a96ce78f0 - New Wishbone master for CPU ...

- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...

2013-06-19 09:16:36 +02:00

..

objs

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

.gitignore

- Debugged SPI module

2013-06-08 11:53:27 +02:00

kcrt0.s

- Debugged SPI module

2013-06-08 11:53:27 +02:00

main.c

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

Makefile

- Debugged SPI module

2013-06-08 11:53:27 +02:00

sd.c

- Debugged SPI module

2013-06-08 11:53:27 +02:00

sd.h

- Debugged SPI module

2013-06-08 11:53:27 +02:00

spi.c

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

spi.h

- Debugged SPI module

2013-06-08 11:53:27 +02:00

standalone.ld

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

test.s

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

uart.c

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

uart.h

- Debugged SPI module

2013-06-08 11:53:27 +02:00

util.c

- Debugged SPI module

2013-06-08 11:53:27 +02:00

util.h

- Debugged SPI module

2013-06-08 11:53:27 +02:00