157 lines
4.3 KiB
VHDL
157 lines
4.3 KiB
VHDL
----------------------------------------------------------------------------------------------
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--
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-- Input file : core.vhd
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-- Design name : core
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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--
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-- Description : Top level entity of the integer unit
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--
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mblite;
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use mblite.config_Pkg.all;
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use mblite.core_Pkg.all;
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entity core is generic
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(
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G_INTERRUPT : boolean := CFG_INTERRUPT;
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_BARREL : boolean := CFG_USE_BARREL;
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G_DEBUG : boolean := CFG_DEBUG
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);
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port
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(
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imem_o : out imem_out_type;
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dmem_o : out dmem_out_type;
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imem_i : in imem_in_type;
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dmem_i : in dmem_in_type;
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int_i : in std_logic;
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rst_i : in std_logic;
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clk_i : in std_logic
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);
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end core;
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architecture arch of core is
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signal fetch_i : fetch_in_type;
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signal fetch_o : fetch_out_type;
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signal decode_i : decode_in_type;
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signal decode_o : decode_out_type;
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signal gprf_o : gprf_out_type;
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signal exec_i : execute_in_type;
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signal exec_o : execute_out_type;
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signal mem_i : mem_in_type;
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signal mem_o : mem_out_type;
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signal ena_i : std_logic;
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begin
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ena_i <= dmem_i.ena_i;
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fetch_i.hazard <= decode_o.hazard;
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fetch_i.branch <= exec_o.branch;
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fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 downto 0);
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fetch0 : fetch port map
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(
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fetch_o => fetch_o,
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imem_o => imem_o,
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fetch_i => fetch_i,
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rst_i => rst_i,
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ena_i => ena_i,
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clk_i => clk_i
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);
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decode_i.program_counter <= fetch_o.program_counter;
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decode_i.instruction <= imem_i.dat_i;
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decode_i.ctrl_wrb <= mem_o.ctrl_wrb;
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decode_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
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decode_i.mem_result <= dmem_i.dat_i;
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decode_i.alu_result <= mem_o.alu_result;
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decode_i.interrupt <= int_i;
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decode_i.flush_id <= exec_o.flush_id;
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decode0: decode generic map
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(
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G_INTERRUPT => G_INTERRUPT,
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G_USE_HW_MUL => G_USE_HW_MUL,
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G_USE_BARREL => G_USE_BARREL,
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G_DEBUG => G_DEBUG
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)
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port map
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(
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decode_o => decode_o,
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decode_i => decode_i,
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gprf_o => gprf_o,
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ena_i => ena_i,
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rst_i => rst_i,
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clk_i => clk_i
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);
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exec_i.fwd_dec <= decode_o.fwd_dec;
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exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
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exec_i.dat_a <= gprf_o.dat_a_o;
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exec_i.dat_b <= gprf_o.dat_b_o;
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exec_i.dat_d <= gprf_o.dat_d_o;
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exec_i.reg_a <= decode_o.reg_a;
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exec_i.reg_b <= decode_o.reg_b;
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exec_i.imm <= decode_o.imm;
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exec_i.program_counter <= decode_o.program_counter;
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exec_i.ctrl_wrb <= decode_o.ctrl_wrb;
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exec_i.ctrl_mem <= decode_o.ctrl_mem;
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exec_i.ctrl_ex <= decode_o.ctrl_ex;
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exec_i.fwd_mem <= mem_o.ctrl_wrb;
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exec_i.mem_result <= dmem_i.dat_i;
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exec_i.alu_result <= mem_o.alu_result;
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exec_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
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execute0 : execute generic map
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(
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G_USE_HW_MUL => G_USE_HW_MUL,
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G_USE_BARREL => G_USE_BARREL
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)
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port map
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(
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exec_o => exec_o,
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exec_i => exec_i,
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ena_i => ena_i,
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rst_i => rst_i,
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clk_i => clk_i
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);
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mem_i.alu_result <= exec_o.alu_result;
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mem_i.program_counter <= exec_o.program_counter;
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mem_i.branch <= exec_o.branch;
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mem_i.dat_d <= exec_o.dat_d;
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mem_i.ctrl_wrb <= exec_o.ctrl_wrb;
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mem_i.ctrl_mem <= exec_o.ctrl_mem;
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mem_i.mem_result <= dmem_i.dat_i;
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mem0 : mem port map
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(
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mem_o => mem_o,
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dmem_o => dmem_o,
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mem_i => mem_i,
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ena_i => ena_i,
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rst_i => rst_i,
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clk_i => clk_i
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);
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end arch;
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