Matthias Blankertz 0a96ce78f0 - New Wishbone master for CPU ...

- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...

2013-06-19 09:16:36 +02:00

..

config_Pkg.vhd

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

core_Pkg.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

core_wb_adapter.vhd

- Debugged SPI module

2013-06-08 11:53:27 +02:00

core_wb.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

core.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

decode.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

dsram.vhd

- Replaced cache with simpler wishbone-memory bridge

2013-06-04 23:18:16 +02:00

execute.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

fetch.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

gprf.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

mem.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00

std_Pkg.vhd

- Integrated MBlite CPU

2013-06-03 19:36:51 +02:00