73 lines
2.2 KiB
VHDL
73 lines
2.2 KiB
VHDL
----------------------------------------------------------------------------------------------
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--
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-- Input file : fetch.vhd
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-- Design name : fetch
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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--
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-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
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-- uses a single port Random Access Memory component which holds
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-- the instructions. The next instruction is computed in the decode
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-- stage.
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mblite;
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use mblite.config_Pkg.all;
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use mblite.core_Pkg.all;
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use mblite.std_Pkg.all;
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entity fetch is port
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(
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fetch_o : out fetch_out_type;
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imem_o : out imem_out_type;
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fetch_i : in fetch_in_type;
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rst_i : in std_logic;
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ena_i : in std_logic;
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clk_i : in std_logic
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);
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end fetch;
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architecture arch of fetch is
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signal r, rin : fetch_out_type;
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begin
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fetch_o.program_counter <= r.program_counter;
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imem_o.adr_o <= rin.program_counter;
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imem_o.ena_o <= ena_i;
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fetch_comb: process(fetch_i, r, rst_i)
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variable v : fetch_out_type;
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begin
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v := r;
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if rst_i = '1' then
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v.program_counter := (OTHERS => '0');
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elsif fetch_i.hazard = '1' then
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v.program_counter := r.program_counter;
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elsif fetch_i.branch = '1' then
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v.program_counter := fetch_i.branch_target;
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else
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v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
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end if;
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rin <= v;
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end process;
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fetch_seq: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if rst_i = '1' then
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r.program_counter <= (others => '0');
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elsif ena_i = '1' then
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r <= rin;
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end if;
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end if;
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end process;
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end arch;
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