500 lines
18 KiB
VHDL
500 lines
18 KiB
VHDL
----------------------------------------------------------------------------------------------
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--
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-- Input file : decode.vhd
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-- Design name : decode
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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--
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-- Description : This combined register file and decoder uses three Dual Port
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-- read after write Random Access Memory components. Every clock
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-- cycle three data values can be read (ra, rb and rd) and one value
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-- can be stored.
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mblite;
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use mblite.config_Pkg.all;
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use mblite.core_Pkg.all;
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use mblite.std_Pkg.all;
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entity decode is generic
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(
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G_INTERRUPT : boolean := CFG_INTERRUPT;
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_BARREL : boolean := CFG_USE_BARREL;
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G_DEBUG : boolean := CFG_DEBUG
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);
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port
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(
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decode_o : out decode_out_type;
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gprf_o : out gprf_out_type;
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decode_i : in decode_in_type;
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ena_i : in std_logic;
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rst_i : in std_logic;
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clk_i : in std_logic
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);
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end decode;
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architecture arch of decode is
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type decode_reg_type is record
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instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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immediate : std_logic_vector(15 downto 0);
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is_immediate : std_logic;
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msr_interrupt_enable : std_logic;
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interrupt : std_logic;
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delay_interrupt : std_logic;
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end record;
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signal r, rin : decode_out_type;
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signal reg, regin : decode_reg_type;
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signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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begin
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decode_o.imm <= r.imm;
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decode_o.ctrl_ex <= r.ctrl_ex;
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decode_o.ctrl_mem <= r.ctrl_mem;
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decode_o.ctrl_wrb <= r.ctrl_wrb;
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decode_o.reg_a <= r.reg_a;
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decode_o.reg_b <= r.reg_b;
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decode_o.hazard <= r.hazard;
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decode_o.program_counter <= r.program_counter;
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decode_o.fwd_dec_result <= r.fwd_dec_result;
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decode_o.fwd_dec <= r.fwd_dec;
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decode_comb: process(decode_i,decode_i.ctrl_wrb,
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decode_i.ctrl_mem_wrb,
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decode_i.instruction,
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decode_i.ctrl_mem_wrb.transfer_size,
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r,r.ctrl_ex,r.ctrl_mem,
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r.ctrl_mem.transfer_size,r.ctrl_wrb,
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r.ctrl_wrb.reg_d,
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r.fwd_dec,reg)
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variable v : decode_out_type;
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variable v_reg : decode_reg_type;
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variable opcode : std_logic_vector(5 downto 0);
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variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
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variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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begin
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v := r;
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v_reg := reg;
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-- Default register values (NOP)
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v_reg.immediate := (others => '0');
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v_reg.is_immediate := '0';
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v_reg.program_counter := decode_i.program_counter;
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v_reg.instruction := decode_i.instruction;
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if decode_i.ctrl_mem_wrb.mem_read = '1' then
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mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
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else
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mem_result := decode_i.alu_result;
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end if;
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wb_dat_d <= mem_result;
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if G_INTERRUPT = true then
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v_reg.delay_interrupt := '0';
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end if;
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if CFG_REG_FWD_WRB = true then
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v.fwd_dec_result := mem_result;
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v.fwd_dec := decode_i.ctrl_wrb;
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else
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v.fwd_dec_result := (others => '0');
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v.fwd_dec.reg_d := (others => '0');
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v.fwd_dec.reg_write := '0';
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end if;
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if (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
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-- A hazard occurred on register a or b
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-- set current instruction and program counter to 0
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instruction := (others => '0');
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program_counter := (others => '0');
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v.hazard := '1';
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elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
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-- A hazard occurred on register d
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-- set current instruction and program counter to 0
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instruction := (others => '0');
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program_counter := (others => '0');
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v.hazard := '1';
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elsif r.hazard = '1' then
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-- Recover from hazard. Insert latched instruction
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instruction := reg.instruction;
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program_counter := reg.program_counter;
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v.hazard := '0';
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else
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instruction := decode_i.instruction;
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program_counter := decode_i.program_counter;
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v.hazard := '0';
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end if;
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v.program_counter := program_counter;
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opcode := instruction(31 downto 26);
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v.ctrl_wrb.reg_d := instruction(25 downto 21);
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v.reg_a := instruction(20 downto 16);
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v.reg_b := instruction(15 downto 11);
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-- SET IMM value
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if reg.is_immediate = '1' then
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v.imm := reg.immediate & instruction(15 downto 0);
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else
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v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
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end if;
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-- Register if an interrupt occurs
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if G_INTERRUPT = true then
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if v_reg.msr_interrupt_enable = '1' and decode_i.interrupt = '1' then
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v_reg.interrupt := '1';
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v_reg.msr_interrupt_enable := '0';
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end if;
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end if;
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v.ctrl_ex.alu_op := ALU_ADD;
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v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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v.ctrl_ex.operation := '0';
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v.ctrl_ex.carry := CARRY_ZERO;
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v.ctrl_ex.carry_keep := CARRY_KEEP;
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v.ctrl_ex.delay := '0';
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v.ctrl_ex.branch_cond := NOP;
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v.ctrl_mem.mem_write := '0';
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v.ctrl_mem.transfer_size := WORD;
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v.ctrl_mem.mem_read := '0';
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v.ctrl_wrb.reg_write := '0';
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if G_INTERRUPT = true and (v_reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
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-- IF an interrupt occured
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-- AND the current instruction is not a branch or return instruction,
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-- AND the current instruction is not in a delay slot,
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-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
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v_reg.msr_interrupt_enable := '0';
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v_reg.interrupt := '0';
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v.reg_a := (others => '0');
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v.reg_b := (others => '0');
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v.imm := X"00000010";
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v.ctrl_wrb.reg_d := "01110";
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v.ctrl_ex.branch_cond := BNC;
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v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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v.ctrl_wrb.reg_write := '1';
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elsif (decode_i.flush_id or v.hazard) = '1' then
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-- clearing these registers is not necessary, but facilitates debugging.
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-- On the other hand performance improves when disabled.
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if G_DEBUG = true then
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v.program_counter := (others => '0');
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v.ctrl_wrb.reg_d := (others => '0');
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v.reg_a := (others => '0');
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v.reg_b := (others => '0');
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v.imm := (others => '0');
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end if;
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elsif is_zero(opcode(5 downto 4)) = '1' then
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-- ADD, SUBTRACT OR COMPARE
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-- Alu operation
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v.ctrl_ex.alu_op := ALU_ADD;
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-- Source operand A
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if opcode(0) = '1' then
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v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
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else
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v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
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end if;
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-- Source operand B
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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if (compare(opcode, "000101") and instruction(1)) = '1' then
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v.ctrl_ex.operation := '1';
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end if;
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-- Carry
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case opcode(1 downto 0) is
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when "00" => v.ctrl_ex.carry := CARRY_ZERO;
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when "01" => v.ctrl_ex.carry := CARRY_ONE;
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when others => v.ctrl_ex.carry := CARRY_ALU;
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end case;
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-- Carry keep
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if opcode(2) = '1' then
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v.ctrl_ex.carry_keep := CARRY_KEEP;
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else
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v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
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end if;
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-- Flag writeback if reg_d != 0
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
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-- OR, AND, XOR, ANDN
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-- ORI, ANDI, XORI, ANDNI
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case opcode(1 downto 0) is
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when "00" => v.ctrl_ex.alu_op := ALU_OR;
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when "10" => v.ctrl_ex.alu_op := ALU_XOR;
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when others => v.ctrl_ex.alu_op := ALU_AND;
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end case;
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if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
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elsif opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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-- Flag writeback if reg_d != 0
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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elsif compare(opcode, "101100") = '1' then
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-- IMM instruction
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v_reg.immediate := instruction(15 downto 0);
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v_reg.is_immediate := '1';
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elsif compare(opcode, "100100") = '1' then
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-- SHIFT, SIGN EXTEND
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if compare(instruction(6 downto 5), "11") = '1' then
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if instruction(0) = '1' then
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v.ctrl_ex.alu_op:= ALU_SEXT16;
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else
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v.ctrl_ex.alu_op:= ALU_SEXT8;
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end if;
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else
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v.ctrl_ex.alu_op:= ALU_SHIFT;
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v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
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case instruction(6 downto 5) is
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when "10" => v.ctrl_ex.carry := CARRY_ZERO;
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when "01" => v.ctrl_ex.carry := CARRY_ALU;
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when others => v.ctrl_ex.carry := CARRY_ARITH;
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end case;
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end if;
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-- Flag writeback if reg_d != 0
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
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-- BRANCH UNCONDITIONAL
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v.ctrl_ex.branch_cond := BNC;
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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-- WRITE THE RESULT ALSO TO REGISTER D
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if v.reg_a(2) = '1' then
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-- Flag writeback if reg_d != 0
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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end if;
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if v.reg_a(3) = '1' then
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v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
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else
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v.ctrl_ex.alu_src_a := ALU_SRC_PC;
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end if;
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if G_INTERRUPT = true then
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v_reg.delay_interrupt := '1';
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end if;
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v.ctrl_ex.delay := v.reg_a(4);
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elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
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-- BRANCH CONDITIONAL
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v.ctrl_ex.alu_op := ALU_ADD;
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v.ctrl_ex.alu_src_a := ALU_SRC_PC;
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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case v.ctrl_wrb.reg_d(2 downto 0) is
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when "000" => v.ctrl_ex.branch_cond := BEQ;
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when "001" => v.ctrl_ex.branch_cond := BNE;
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when "010" => v.ctrl_ex.branch_cond := BLT;
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when "011" => v.ctrl_ex.branch_cond := BLE;
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when "100" => v.ctrl_ex.branch_cond := BGT;
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when others => v.ctrl_ex.branch_cond := BGE;
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end case;
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if G_INTERRUPT = true then
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v_reg.delay_interrupt := '1';
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end if;
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v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
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elsif compare(opcode, "101101") = '1' then
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-- RETURN
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v.ctrl_ex.branch_cond := BNC;
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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v.ctrl_ex.delay := '1';
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if G_INTERRUPT = true then
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if v.ctrl_wrb.reg_d(0) = '1' then
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v_reg.msr_interrupt_enable := '1';
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end if;
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v_reg.delay_interrupt := '1';
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end if;
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elsif compare(opcode(5 downto 4), "11") = '1' then
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-- SW, LW
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v.ctrl_ex.alu_op := ALU_ADD;
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v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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v.ctrl_ex.carry := CARRY_ZERO;
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if opcode(2) = '1' then
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-- Store
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v.ctrl_mem.mem_write := '1';
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v.ctrl_mem.mem_read := '0';
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v.ctrl_wrb.reg_write := '0';
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else
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-- Load
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v.ctrl_mem.mem_write := '0';
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v.ctrl_mem.mem_read := '1';
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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end if;
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case opcode(1 downto 0) is
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when "00" => v.ctrl_mem.transfer_size := BYTE;
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when "01" => v.ctrl_mem.transfer_size := HALFWORD;
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when others => v.ctrl_mem.transfer_size := WORD;
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end case;
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v.ctrl_ex.delay := '0';
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elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
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v.ctrl_ex.alu_op := ALU_MUL;
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
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v.ctrl_ex.alu_op := ALU_BS;
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if opcode(3) = '1' then
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v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
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else
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v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
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end if;
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v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
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else
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-- UNKNOWN OPCODE
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null;
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end if;
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rin <= v;
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regin <= v_reg;
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end process;
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decode_seq: process(clk_i)
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procedure proc_reset_decode is
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begin
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r.reg_a <= (others => '0');
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r.reg_b <= (others => '0');
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r.imm <= (others => '0');
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r.program_counter <= (others => '0');
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r.hazard <= '0';
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r.ctrl_ex.alu_op <= ALU_ADD;
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r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
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r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
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r.ctrl_ex.operation <= '0';
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r.ctrl_ex.carry <= CARRY_ZERO;
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r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
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r.ctrl_ex.delay <= '0';
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r.ctrl_ex.branch_cond <= NOP;
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|
r.ctrl_mem.mem_write <= '0';
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r.ctrl_mem.transfer_size <= WORD;
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|
r.ctrl_mem.mem_read <= '0';
|
|
r.ctrl_wrb.reg_d <= (others => '0');
|
|
r.ctrl_wrb.reg_write <= '0';
|
|
r.fwd_dec_result <= (others => '0');
|
|
r.fwd_dec.reg_d <= (others => '0');
|
|
r.fwd_dec.reg_write <= '0';
|
|
reg.instruction <= (others => '0');
|
|
reg.program_counter <= (others => '0');
|
|
reg.immediate <= (others => '0');
|
|
reg.is_immediate <= '0';
|
|
reg.msr_interrupt_enable <= '1';
|
|
reg.interrupt <= '0';
|
|
reg.delay_interrupt <= '0';
|
|
end procedure proc_reset_decode;
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if rst_i = '1' then
|
|
proc_reset_decode;
|
|
elsif ena_i = '1' then
|
|
r <= rin;
|
|
reg <= regin;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
gprf0 : gprf port map
|
|
(
|
|
gprf_o => gprf_o,
|
|
gprf_i.adr_a_i => rin.reg_a,
|
|
gprf_i.adr_b_i => rin.reg_b,
|
|
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
|
|
gprf_i.dat_w_i => wb_dat_d,
|
|
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
|
|
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
|
|
ena_i => ena_i,
|
|
clk_i => clk_i
|
|
);
|
|
end arch;
|