Files
2d_display_engine-new/firmware/main.c
Matthias Blankertz 0a96ce78f0 - New Wishbone master for CPU
- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...
2013-06-19 09:16:36 +02:00

149 lines
2.5 KiB
C

// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#include "util.h"
#include "uart.h"
#include "spi.h"
#include "sd.h"
static unsigned int * const pio = (unsigned int *)0x08010000;
void main() {
*pio = 0x000000a5u;
uart_writes("Hello, World!\n");
/* unsigned foo = 0xdeadbeef; */
/* const char *s = utox(foo); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb('\n'); */
*pio = 0x1u;
unsigned char tmp;
int i;
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
// Set SPI clock to ~400kHz
spi_setclk(63u);
*pio = 0x2u;
sd_por();
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
*pio = 0x3u;
// Send CMD0
spi_set_ss(true);
tmp = sd_cmd(0, 0);
//spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD0)\n");
return;
}
*pio = 0x4u;
unsigned rsp;
spi_set_ss(true);
tmp = sd_cmd_r7(8, 0x000001AA, &rsp);
//spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD8)\n");
return;
}
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
unsigned char s_tmp = tmp;
*pio = 0x5u;
spi_set_ss(true);
tmp = sd_cmd_r7(58, 0x0, &rsp);
//spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD58)\n");
return;
}
const char *s;
s = utox(rsp);
uart_writes("0x");
uart_writes(s);
uart_writeb('\n');
*pio = 0x5u;
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
spi_set_ss(true);
tmp = sd_cmd_r7(58, 0x0, &rsp);
//spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD58)\n");
return;
}
s = utox(rsp);
uart_writes("0x");
uart_writes(s);
uart_writeb('\n');
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
*pio = 0x6u;
if(s_tmp&0x4) { // Illegal command, not SDCv2
tmp = 0xff;
while(tmp&0x1) {
spi_set_ss(true);
tmp = sd_cmd(55, 0);
tmp = sd_cmd(41, 0);
//spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (ACMD41)\n");
return;
}
uart_writeb('\n');
if(tmp != 0x1)
return;
}
if(tmp&0x4) { // Illegal command, not SDCv1
uart_writes("MMC\n");
} else {
uart_writes("SDCv1\n");
}
} else {
uart_writes("SDCv2\n");
}
*pio = 0x7u;
/* const char *s = utox(tmp); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb(' '); */
/* s = utox(rsp); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb('\n'); */
// Echo on uart
char c;
while(1) {
c = uart_readb();
if(c == '\r')
uart_writeb('\n');
uart_writeb(c);
}
}