matthias/2d_display_engine-new
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0a96ce78f03a7b69facd040910c91fd1f5ac5f6e
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Matthias Blankertz 0a96ce78f0 - New Wishbone master for CPU 
- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...
2013-06-19 09:16:36 +02:00
constr
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
coregen
- Debugged SPI module
2013-06-08 11:53:27 +02:00
ddr2_sdram/vhdl_bl4/example_design
- System integration & debugging
2013-03-09 14:14:22 +01:00
firmware
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
mblite
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
sim
- Simulator rasterizer working
2013-03-22 20:12:20 +01:00
src
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
tb
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
tools
- Always convert wishbone.defines to unix line endings so interconnect is
2013-03-21 19:57:49 +01:00
.gitignore
- Debugged SPI module
2013-06-08 11:53:27 +02:00
bresenham_dp_tb.wcfg
- Started implementing rasterizer
2013-03-26 17:24:15 +01:00
impact.cmd
- Replaced cache with simpler wishbone-memory bridge
2013-06-04 23:18:16 +02:00
Makefile
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
mblite_cache_tb.wcfg
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
mblite_rom.bmm
- Debugged SPI module
2013-06-08 11:53:27 +02:00
rasterizer_l_tb.wcfg
- Rasterizer
2013-03-27 20:21:58 +01:00
spi_tb.wcfg
- Debugged SPI module
2013-06-08 11:53:27 +02:00
toplevel_tb.wcfg
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
vga_tb.wcfg
- Reworked VGA
2013-03-07 20:55:58 +01:00
vga.bmp
- Added synthesis contraints
2013-03-04 12:55:59 +01:00
wb_ddr_ctrl_tb.wcfg
- Added synthesis contraints
2013-03-04 12:55:59 +01:00
wb_ddr_ctrl_wb_sc_fe_tb.wcfg
- Some optimization
2013-03-19 20:24:28 +01:00
wb_ddr_ctrl_wb_sc_tb.wcfg
- New Wishbone master for CPU
2013-06-19 09:16:36 +02:00
wb_mem_bridge_tb.wcfg
- Replaced cache with simpler wishbone-memory bridge
2013-06-04 23:18:16 +02:00
Description
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372 KiB
Languages
VHDL 69.1%
Verilog 10.1%
SystemVerilog 8%
Raku 7.9%
C++ 2.6%
Other 2.2%