Matthias Blankertz
0bc4815926
- Debugged UART - Firmware support for SPI, UART - Work on SD/MMC support in firmware - Debugged mblite core/WB interface
248 lines
11 KiB
VHDL
248 lines
11 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Testbench for design "toplevel"
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-- Project :
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-------------------------------------------------------------------------------
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-- File : toplevel_tb.vhd
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-- Author : <Matthias@MATTHIAS-PC>
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-- Company :
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-- Created : 2013-03-02
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-- Last update: 2013-06-07
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2013
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-03-02 1.0 Matthias Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.sim_bmppack.all;
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-------------------------------------------------------------------------------
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entity toplevel_tb is
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end toplevel_tb;
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-------------------------------------------------------------------------------
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architecture testbench of toplevel_tb is
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component toplevel
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generic (
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dontcare : std_logic
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);
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port (
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clkin_50MHz : IN std_ulogic;
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clkin_133MHz : IN std_ulogic;
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reset : IN std_ulogic;
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vga_r, vga_g, vga_b : OUT std_logic_vector(3 downto 0);
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vga_vsync, vga_hsync : OUT std_ulogic;
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dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic;
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dataflash_miso : IN std_ulogic;
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-- led : OUT std_ulogic_vector(7 downto 0);
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ddr2_dq : inout std_logic_vector(15 downto 0);
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ddr2_a : out std_logic_vector(12 downto 0);
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ddr2_ba : out std_logic_vector(1 downto 0);
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ddr2_cke : out std_logic;
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ddr2_cs_n : out std_logic;
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ddr2_ras_n : out std_logic;
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ddr2_cas_n : out std_logic;
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ddr2_we_n : out std_logic;
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ddr2_odt : out std_logic;
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ddr2_dm : out std_logic_vector(1 downto 0);
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rst_dqs_div_in : in std_logic;
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rst_dqs_div_out : out std_logic;
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ddr2_dqs : inout std_logic_vector(1 downto 0);
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ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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ddr2_ck : out std_logic_vector(0 downto 0);
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ddr2_ck_n : out std_logic_vector(0 downto 0);
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rs232_txd : out std_logic;
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rs232_rxd : in std_logic;
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sd_miso : in std_logic;
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sd_mosi : out std_logic;
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sd_cs : out std_logic;
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sd_sck : out std_logic
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);
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end component;
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component ddr2_model
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port (
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ck : in std_logic;
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ck_n : in std_logic;
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cke : in std_logic;
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cs_n : in std_logic;
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ras_n : in std_logic;
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cas_n : in std_logic;
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we_n : in std_logic;
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dm_rdqs : inout std_logic_vector(1 downto 0);
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ba : in std_logic_vector(1 downto 0);
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addr : in std_logic_vector(12 downto 0);
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dq : inout std_logic_vector(15 downto 0);
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dqs : inout std_logic_vector(1 downto 0);
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dqs_n : inout std_logic_vector(1 downto 0);
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rdqs_n : out std_logic_vector(1 downto 0);
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odt : in std_logic
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);
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end component;
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constant dontcare : std_logic := '0';
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-- component ports
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signal clkin_50MHz : std_ulogic := '0';
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signal clkin_133MHz : std_ulogic := '0';
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signal reset : std_ulogic := '0';
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signal vga_r, vga_g, vga_b : std_logic_vector(3 downto 0);
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signal vga_vsync, vga_hsync : std_ulogic;
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signal dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : std_ulogic;
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signal dataflash_miso : std_ulogic;
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signal led : std_ulogic_vector(7 downto 0);
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signal ddr2_dq : std_logic_vector(15 downto 0);
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signal ddr2_a : std_logic_vector(12 downto 0);
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signal ddr2_ba : std_logic_vector(1 downto 0);
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signal ddr2_cke : std_logic;
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signal ddr2_cs_n : std_logic;
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signal ddr2_ras_n : std_logic;
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signal ddr2_cas_n : std_logic;
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signal ddr2_we_n : std_logic;
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signal ddr2_odt : std_logic;
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signal ddr2_dm : std_logic_vector(1 downto 0);
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signal rst_dqs_div_in : std_logic;
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signal rst_dqs_div_out : std_logic;
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signal ddr2_dqs : std_logic_vector(1 downto 0);
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signal ddr2_dqs_n : std_logic_vector(1 downto 0);
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signal ddr2_ck : std_logic_vector(0 downto 0);
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signal ddr2_ck_n : std_logic_vector(0 downto 0);
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signal rs232_txd, rs232_rxd : std_logic := '1';
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signal sd_mosi, sd_miso, sd_cs, sd_sck : std_logic := '0';
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signal sim_done : boolean := false;
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begin -- testbench
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-- component instantiation
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DUT: toplevel
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generic map (
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dontcare => dontcare
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)
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port map (
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clkin_50MHz => clkin_50MHz,
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clkin_133MHz => clkin_133MHz,
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reset => reset,
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vga_r => vga_r,
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vga_g => vga_g,
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vga_b => vga_b,
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vga_vsync => vga_vsync,
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vga_hsync => vga_hsync,
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dataflash_mosi => dataflash_mosi,
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dataflash_sck => dataflash_sck,
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dataflash_ss => dataflash_ss,
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dataflash_wp => dataflash_wp,
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dataflash_rst => dataflash_rst,
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dataflash_miso => dataflash_miso,
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-- led => led,
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ddr2_dq => ddr2_dq,
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ddr2_a => ddr2_a,
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ddr2_ba => ddr2_ba,
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ddr2_cke => ddr2_cke,
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ddr2_cs_n => ddr2_cs_n,
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ddr2_ras_n => ddr2_ras_n,
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ddr2_cas_n => ddr2_cas_n,
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ddr2_we_n => ddr2_we_n,
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ddr2_odt => ddr2_odt,
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ddr2_dm => ddr2_dm,
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rst_dqs_div_in => rst_dqs_div_in,
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rst_dqs_div_out => rst_dqs_div_out,
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ddr2_dqs => ddr2_dqs,
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ddr2_dqs_n => ddr2_dqs_n,
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ddr2_ck => ddr2_ck,
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ddr2_ck_n => ddr2_ck_n,
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rs232_txd => rs232_txd,
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rs232_rxd => rs232_rxd,
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sd_mosi => sd_mosi,
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sd_miso => sd_miso,
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sd_cs => sd_cs,
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sd_sck => sd_sck);
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rst_dqs_div_in <= rst_dqs_div_out after 100 ps;
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rs232_rxd <= rs232_txd;
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ddr2_model_inst : ddr2_model port map (
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ck => ddr2_ck(0),
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ck_n => ddr2_ck_n(0),
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cke => ddr2_cke,
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cs_n => ddr2_cs_n,
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ras_n => ddr2_ras_n,
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cas_n => ddr2_cas_n,
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we_n => ddr2_we_n,
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dm_rdqs => ddr2_dm,
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ba => ddr2_ba,
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addr => ddr2_a,
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dq => ddr2_dq,
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dqs => ddr2_dqs,
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dqs_n => ddr2_dqs_n,
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rdqs_n => open,
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odt => ddr2_odt);
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-- clock generation
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clkin_133MHz <= not clkin_133MHz after 3.7594 ns when sim_done = false else
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'0';
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clkin_50MHz <= not clkin_50MHz after 10 ns when sim_done = false else
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'0';
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait;
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end process WaveGen_Proc;
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VGARead: process
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variable i: integer := 0;
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variable pixeldata : std_logic_vector(23 downto 0);
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begin
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ReadFile("vga.bmp");
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wait for 100 ns; -- wait for uut to stat
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wait until rising_edge(vga_vsync); -- wait for vga frame to start (depends
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-- on latency of UUT)
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wait for 1061.76 us;
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while true loop
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for y in 479 downto 0 loop
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for x in 0 to 639 loop
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pixeldata := std_logic_vector(vga_r) & "0000" & std_logic_vector(vga_g) & "0000" & std_logic_vector(vga_b) & "0000";
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SetPixel(x, y, pixeldata);
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wait for 40 ns;
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end loop; -- x
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wait for 6400 ns;
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end loop; -- x
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wait for 1440 us;
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WriteFile("vga" & integer'image(i) & ".bmp");
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i := i + 1;
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if i = 4 then
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sim_done <= true;
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wait;
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end if;
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end loop;
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end process;
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end testbench;
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-------------------------------------------------------------------------------
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configuration toplevel_tb_testbench_cfg of toplevel_tb is
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for testbench
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end for;
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end toplevel_tb_testbench_cfg;
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-------------------------------------------------------------------------------
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