Matthias Blankertz
1807fb99b5
- Redesign wishbone interconnect - Changed wb_ddr_ctrl_wb_sc to allow easier addition of ports
73 lines
1.2 KiB
ArmAsm
73 lines
1.2 KiB
ArmAsm
.global main
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main:
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lbui r3, r0, testdata+1
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swi r3, r0, 0x4000
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addi r19, r0, helloworld
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main_loop:
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lbu r5, r19, r0
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beqi r5, fill
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brlid r15, send_byte
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addi r19, r19, 1 # delay slot
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bri main_loop
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fill:
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# Clear screen
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addi r3, r0, 0x8000000 # r3 = address, load with FB base
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addi r4, r0, 0 # r4 = y ctr
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addi r7, r0, 0x0f000f00 # Upper/lower border
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addi r8, r0, 0x0000000f # Left border
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addi r9, r0, 0x00f00000 # Right border
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fill_line:
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addi r5, r0, 0 # r5 = x ctr
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fill_loop:
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beqi r4, border
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addi r6, r4, -479
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beqi r6, border
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beqi r5, lborder
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addi r6, r5, -638
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beqi r6, rborder
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brid fill_loop_end
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sw r0, r3, r0
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border:
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brid fill_loop_end
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sw r7, r3, r0
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lborder:
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brid fill_loop_end
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sw r8, r3, r0
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rborder:
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sw r9, r3, r0
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fill_loop_end:
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addi r3, r3, 4
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addi r6, r5, -638
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beqi r6, fill_loop_nextline
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brid fill_loop
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addi r5, r5, 2
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fill_loop_nextline:
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addi r6, r4, -479
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beqi r6, done
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brid fill_line
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addi r4, r4, 1
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done:
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swi r0, r0, 0x0BFFFFFF # Force mem_bridge buffer flush
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idle:
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bri idle
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send_byte:
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lbui r3, r0, 0x4021
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andi r3, r3, 0x2 # writefull
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bnei r3, send_byte
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rtsd r15, 8
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sbi r5, r0, 0x4020 # delay slot
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.rodata
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helloworld:
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.asciz "Hello, World!(2)"
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.data
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testdata:
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.word 0xdeadbeef
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