2 Commits

Author	SHA1	Message	Date
Matthias Blankertz	1807fb99b5	- Replaced cache with simpler wishbone-memory bridge ... - Redesign wishbone interconnect - Changed wb_ddr_ctrl_wb_sc to allow easier addition of ports	2013-06-04 23:18:16 +02:00
Matthias Blankertz	882ec0a33f	- Integrated MBlite CPU ... - Integrated UART - Various bug fixes	2013-06-03 19:36:51 +02:00