- Work on ddr to wishbone bridge
This commit is contained in:
@@ -164,6 +164,32 @@
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<Attr Name="UsedInSimulation" Val="1"/>
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</File>
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<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl_wb_dc.vhd">
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<File Path="$PSRCDIR/sources_1/ip/fifo_generator_v9_3_1/wb_ddr_ctrl_wb_from_ddr.xci">
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<File Path="$PSRCDIR/sources_1/ip/fifo_generator_v9_3_0/wb_ddr_ctrl_wb_to_ddr.xci">
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<Attr Name="UsedInSimulation" Val="1"/>
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<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl_wb.vhd">
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<FileInfo>
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<Attr Name="UsedInSynthesis" Val="1"/>
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@@ -0,0 +1,12 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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||||
changes made to this file may result in unpredictable
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||||
behavior or data corruption. It is strongly advised that
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||||
users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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</messages>
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@@ -0,0 +1,943 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">69</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">69</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">spartan3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
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|
||||
<xilinx:device>xc3s700an</xilinx:device>
|
||||
<xilinx:deviceFamily>spartan3a</xilinx:deviceFamily>
|
||||
<xilinx:package>fgg484</xilinx:package>
|
||||
<xilinx:speedGrade>-4</xilinx:speedGrade>
|
||||
</xilinx:part>
|
||||
<xilinx:flowOptions>
|
||||
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
|
||||
<xilinx:designEntry>VHDL</xilinx:designEntry>
|
||||
<xilinx:asySymbol>true</xilinx:asySymbol>
|
||||
<xilinx:flowVendor>Other</xilinx:flowVendor>
|
||||
<xilinx:addPads>false</xilinx:addPads>
|
||||
<xilinx:removeRPMs>false</xilinx:removeRPMs>
|
||||
<xilinx:createNDF>false</xilinx:createNDF>
|
||||
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
|
||||
<xilinx:formalVerification>false</xilinx:formalVerification>
|
||||
</xilinx:flowOptions>
|
||||
<xilinx:simulationOptions>
|
||||
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
|
||||
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
|
||||
<xilinx:foundationSym>false</xilinx:foundationSym>
|
||||
</xilinx:simulationOptions>
|
||||
</xilinx:instanceProperties>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:design>
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
# Date: Tue Nov 6 15:56:51 2012
|
||||
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
SET workingdirectory = ./tmp/
|
||||
|
||||
# CRC: e0289cf1
|
||||
@@ -0,0 +1,5 @@
|
||||
INFO:sim:172 - Generating IP...
|
||||
Applying current project options...
|
||||
Finished applying current project options.
|
||||
Cancelled executing Tcl generator.
|
||||
Saved CGP file for project 'coregen'.
|
||||
@@ -0,0 +1,108 @@
|
||||
<?xml version="1.0"?>
|
||||
<BillOfMaterials Version="1" Minor="2">
|
||||
<IPInstance name="wb_ddr_ctrl_wb_to_ddr">
|
||||
<FileSets>
|
||||
<FileSet generator="apply_current_project_options_generator">
|
||||
<File name="./apply_current_project_options_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="model_parameter_resolution_generator">
|
||||
<File name="./model_parameter_resolution_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ip_xco_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.xco" type="xco" timestamp="Tue Nov 06 15:54:37 GMT 2012" checksum="0xEC9F82AC"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="associated_files_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html" type="ignore" timestamp="Sat Oct 13 03:01:40 GMT 2012" checksum="0x5A766369"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/fifo_generator_v9_3_readme.txt" type="ignore" timestamp="Sat Oct 13 03:01:40 GMT 2012" checksum="0xD700FB89"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ejava_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xB547BB7D"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x1E2F8E9C"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.xdc" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x77D89547"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/implement.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x618F0487"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/implement.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x41A64983"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xADC01C64"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x0D228AAD"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.bat" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xB9AD0E43"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.sh" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xA94EC195"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.tcl" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xEB8CDEED"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/xst.prj" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x8D205C47"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/implement/xst.scr" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x22741F1E"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x1F7F07BB"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x38E533B0"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x0C3CDB0C"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.do" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x98C3788B"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x5FDBD750"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_ncsim.sh" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x27AF2605"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_vcs.sh" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xC26A70F5"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/ucli_commands.key" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x32508805"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/vcs_session.tcl" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xC160568F"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_isim.tcl" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x546AFE24"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_mti.do" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xE1168216"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_ncsim.sv" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x7F129823"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x0E99F9F4"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xC342CFF2"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.bat" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x0C3CDB0C"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.do" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xD9164D7B"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.sh" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x5FDBD750"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_ncsim.sh" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x885E0CCA"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_vcs.sh" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x0AC98A7E"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/ucli_commands.key" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x32508805"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/vcs_session.tcl" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xF61C74F1"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_isim.tcl" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x546AFE24"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_mti.do" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0xE1168216"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_ncsim.sv" type="ignore" timestamp="Tue Nov 06 15:54:39 GMT 2012" checksum="0x7F129823"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dgen.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xA74A0617"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dverif.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xEB31B197"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pctrl.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x87DAAA4D"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pkg.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x27932D94"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_rng.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x408CD90A"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_synth.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0xF16CD2C0"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_tb.vhd" type="ignore" timestamp="Tue Nov 06 15:54:38 GMT 2012" checksum="0x66F9B6DA"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ngc_netlist_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.ngc" type="ngc" timestamp="Tue Nov 06 15:56:34 GMT 2012" checksum="0x39FBE183"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="obfuscate_netlist_generator">
|
||||
<File name="./obfuscate_netlist_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="padded_implementation_netlist_generator">
|
||||
<File name="./padded_implementation_netlist_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="instantiation_template_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.vho" type="vho" timestamp="Tue Nov 06 15:56:34 GMT 2012" checksum="0x2C64A742"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="structural_simulation_model_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.vhd" type="vhdl" timestamp="Tue Nov 06 15:56:34 GMT 2012" checksum="0x4DC0534C"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="all_documents_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt" type="ignore" timestamp="Tue Nov 06 15:56:35 GMT 2012" checksum="0xD700FB89"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html" type="ignore" timestamp="Tue Nov 06 15:56:35 GMT 2012" checksum="0x5A766369"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr/doc/pg057-fifo-generator.pdf" type="ignore" timestamp="Tue Nov 06 15:56:35 GMT 2012" checksum="0x90F23916"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="readme_documents_generator">
|
||||
<File name="./readme_documents_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="asy_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.asy" type="asy" timestamp="Tue Nov 06 15:56:39 GMT 2012" checksum="0x221D61F9"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="xmdf_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr_xmdf.tcl" type="tclXmdf" timestamp="Tue Nov 06 15:56:39 GMT 2012" checksum="0x8A876748"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="synthesis_ise_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.gise" type="ignore" timestamp="Tue Nov 06 15:56:45 GMT 2012" checksum="0x92BF8E11"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.xise" type="ignore" timestamp="Tue Nov 06 15:56:45 GMT 2012" checksum="0xAF6E9100"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ise_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.gise" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xA30A284B"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr.xise" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xD3F364ED"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="deliver_readme_generator">
|
||||
<File name="./deliver_readme_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="flist_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_to_ddr_flist.txt" type="ignore" timestamp="Tue Nov 06 15:56:51 GMT 2012" checksum="0xB430E71D"></File>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
</IPInstance>
|
||||
</BillOfMaterials>
|
||||
@@ -0,0 +1,29 @@
|
||||
# Tcl script generated by PlanAhead
|
||||
|
||||
set reloadAllCoreGenRepositories false
|
||||
|
||||
set tclUtilsPath "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
|
||||
|
||||
set repoPaths ""
|
||||
|
||||
set cgProjectPath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/coregen.cgc"
|
||||
|
||||
set ipFile "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/wb_ddr_ctrl_wb_to_ddr.xco"
|
||||
|
||||
set ipName "wb_ddr_ctrl_wb_to_ddr"
|
||||
|
||||
set hdlType "VHDL"
|
||||
|
||||
set cgPartSpec "xc3s700an-4fgg484"
|
||||
|
||||
set chains "GENERATE_CURRENT_CHAIN"
|
||||
|
||||
set params ""
|
||||
|
||||
set bomFilePath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/pa_cg_bom.xml"
|
||||
|
||||
# generate the IP
|
||||
set result [source "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_gen_out_prods.tcl"]
|
||||
|
||||
exit $result
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
# Tcl script generated by PlanAhead
|
||||
|
||||
set reloadAllCoreGenRepositories false
|
||||
|
||||
set tclUtilsPath "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
|
||||
|
||||
set repoPaths ""
|
||||
|
||||
set cgProjectPath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/coregen.cgc"
|
||||
|
||||
set ipFile "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/wb_ddr_ctrl_wb_to_ddr.xco"
|
||||
|
||||
set ipName "wb_ddr_ctrl_wb_to_ddr"
|
||||
|
||||
set chains "CUSTOMIZE_CURRENT_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
|
||||
|
||||
set bomFilePath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/pa_cg_bom.xml"
|
||||
|
||||
set cgPartSpec "xc3s700an-4fgg484"
|
||||
|
||||
set hdlType "VHDL"
|
||||
|
||||
# generate the IP
|
||||
set result [source "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_reconfig_core.tcl"]
|
||||
|
||||
exit $result
|
||||
|
||||
@@ -0,0 +1,370 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE INTERACTIVE
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan3a
|
||||
SET_PREFERENCE device xc3s700an
|
||||
SET_PREFERENCE speedgrade -4
|
||||
SET_PREFERENCE package fgg484
|
||||
SET_PREFERENCE verilogsim false
|
||||
SET_PREFERENCE vhdlsim true
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory /home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/
|
||||
SET_PREFERENCE workingdirectory /home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/tmp/
|
||||
SET_PREFERENCE subworkingdirectory /home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory /home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry VHDL
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name wb_ddr_ctrl_wb_to_ddr
|
||||
SET_PARAMETER Fifo_Implementation Independent_Clocks_Distributed_RAM
|
||||
SET_PARAMETER synchronization_stages 2
|
||||
SET_PARAMETER synchronization_stages_axi 2
|
||||
SET_PARAMETER Interface_Type Native
|
||||
SET_PARAMETER Performance_Options Standard_FIFO
|
||||
SET_PARAMETER Input_Data_Width 69
|
||||
SET_PARAMETER Input_Depth 16
|
||||
SET_PARAMETER Output_Data_Width 69
|
||||
SET_PARAMETER Output_Depth 16
|
||||
SET_PARAMETER Enable_ECC false
|
||||
SET_PARAMETER Use_Embedded_Registers false
|
||||
SET_PARAMETER Reset_Pin true
|
||||
SET_PARAMETER Enable_Reset_Synchronization true
|
||||
SET_PARAMETER Reset_Type Asynchronous_Reset
|
||||
SET_PARAMETER Full_Flags_Reset_Value 1
|
||||
SET_PARAMETER Use_Dout_Reset true
|
||||
SET_PARAMETER Dout_Reset_Value 0
|
||||
SET_PARAMETER Almost_Full_Flag false
|
||||
SET_PARAMETER Almost_Empty_Flag false
|
||||
SET_PARAMETER Valid_Flag false
|
||||
SET_PARAMETER Valid_Sense Active_High
|
||||
SET_PARAMETER Underflow_Flag false
|
||||
SET_PARAMETER Underflow_Sense Active_High
|
||||
SET_PARAMETER Write_Acknowledge_Flag false
|
||||
SET_PARAMETER Write_Acknowledge_Sense Active_High
|
||||
SET_PARAMETER Overflow_Flag false
|
||||
SET_PARAMETER Overflow_Sense Active_High
|
||||
SET_PARAMETER Inject_Sbit_Error false
|
||||
SET_PARAMETER Inject_Dbit_Error false
|
||||
SET_PARAMETER Use_Extra_Logic false
|
||||
SET_PARAMETER Data_Count false
|
||||
SET_PARAMETER Data_Count_Width 4
|
||||
SET_PARAMETER Write_Data_Count false
|
||||
SET_PARAMETER Write_Data_Count_Width 4
|
||||
SET_PARAMETER Read_Data_Count false
|
||||
SET_PARAMETER Read_Data_Count_Width 4
|
||||
SET_PARAMETER Disable_Timing_Violations true
|
||||
SET_PARAMETER Read_Clock_Frequency 1
|
||||
SET_PARAMETER Write_Clock_Frequency 1
|
||||
SET_PARAMETER Programmable_Full_Type No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value 13
|
||||
SET_PARAMETER Full_Threshold_Negate_Value 12
|
||||
SET_PARAMETER Programmable_Empty_Type No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value 2
|
||||
SET_PARAMETER Empty_Threshold_Negate_Value 3
|
||||
SET_PARAMETER AXI_Type AXI4_Stream
|
||||
SET_PARAMETER Clock_Type_AXI Common_Clock
|
||||
SET_PARAMETER Use_Clock_Enable false
|
||||
SET_PARAMETER Clock_Enable_Type Slave_Interface_Clock_Enable
|
||||
SET_PARAMETER Enable_Write_Channel false
|
||||
SET_PARAMETER Enable_Read_Channel false
|
||||
SET_PARAMETER ID_Width 4
|
||||
SET_PARAMETER AXI_Address_Width 32
|
||||
SET_PARAMETER AXI_Data_Width 64
|
||||
SET_PARAMETER Enable_AWUSER false
|
||||
SET_PARAMETER AWUSER_Width 1
|
||||
SET_PARAMETER Enable_WUSER false
|
||||
SET_PARAMETER WUSER_Width 1
|
||||
SET_PARAMETER Enable_BUSER false
|
||||
SET_PARAMETER BUSER_Width 1
|
||||
SET_PARAMETER Enable_ARUSER false
|
||||
SET_PARAMETER ARUSER_Width 1
|
||||
SET_PARAMETER Enable_RUSER false
|
||||
SET_PARAMETER RUSER_Width 1
|
||||
SET_PARAMETER Enable_TDATA false
|
||||
SET_PARAMETER TDATA_Width 64
|
||||
SET_PARAMETER Enable_TID false
|
||||
SET_PARAMETER TID_Width 8
|
||||
SET_PARAMETER Enable_TDEST false
|
||||
SET_PARAMETER TDEST_Width 4
|
||||
SET_PARAMETER Enable_TUSER false
|
||||
SET_PARAMETER TUSER_Width 4
|
||||
SET_PARAMETER Enable_TREADY true
|
||||
SET_PARAMETER Enable_TLAST false
|
||||
SET_PARAMETER Enable_TSTROBE false
|
||||
SET_PARAMETER TSTRB_Width 4
|
||||
SET_PARAMETER Enable_TKEEP false
|
||||
SET_PARAMETER TKEEP_Width 4
|
||||
SET_PARAMETER wach_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_wach Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_wach Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_wach false
|
||||
SET_PARAMETER Inject_Sbit_Error_wach false
|
||||
SET_PARAMETER Inject_Dbit_Error_wach false
|
||||
SET_PARAMETER Input_Depth_wach 16
|
||||
SET_PARAMETER Enable_Data_Counts_wach false
|
||||
SET_PARAMETER Programmable_Full_Type_wach No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_wach 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_wach No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_wach 1022
|
||||
SET_PARAMETER wdch_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_wdch Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_wdch Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_wdch false
|
||||
SET_PARAMETER Inject_Sbit_Error_wdch false
|
||||
SET_PARAMETER Inject_Dbit_Error_wdch false
|
||||
SET_PARAMETER Input_Depth_wdch 1024
|
||||
SET_PARAMETER Enable_Data_Counts_wdch false
|
||||
SET_PARAMETER Programmable_Full_Type_wdch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_wdch 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_wdch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_wdch 1022
|
||||
SET_PARAMETER wrch_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_wrch Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_wrch Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_wrch false
|
||||
SET_PARAMETER Inject_Sbit_Error_wrch false
|
||||
SET_PARAMETER Inject_Dbit_Error_wrch false
|
||||
SET_PARAMETER Input_Depth_wrch 16
|
||||
SET_PARAMETER Enable_Data_Counts_wrch false
|
||||
SET_PARAMETER Programmable_Full_Type_wrch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_wrch 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_wrch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_wrch 1022
|
||||
SET_PARAMETER rach_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_rach Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_rach Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_rach false
|
||||
SET_PARAMETER Inject_Sbit_Error_rach false
|
||||
SET_PARAMETER Inject_Dbit_Error_rach false
|
||||
SET_PARAMETER Input_Depth_rach 16
|
||||
SET_PARAMETER Enable_Data_Counts_rach false
|
||||
SET_PARAMETER Programmable_Full_Type_rach No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_rach 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_rach No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_rach 1022
|
||||
SET_PARAMETER rdch_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_rdch Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_rdch Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_rdch false
|
||||
SET_PARAMETER Inject_Sbit_Error_rdch false
|
||||
SET_PARAMETER Inject_Dbit_Error_rdch false
|
||||
SET_PARAMETER Input_Depth_rdch 1024
|
||||
SET_PARAMETER Enable_Data_Counts_rdch false
|
||||
SET_PARAMETER Programmable_Full_Type_rdch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_rdch 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_rdch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_rdch 1022
|
||||
SET_PARAMETER axis_type FIFO
|
||||
SET_PARAMETER FIFO_Implementation_axis Common_Clock_Block_RAM
|
||||
SET_PARAMETER FIFO_Application_Type_axis Data_FIFO
|
||||
SET_PARAMETER Enable_ECC_axis false
|
||||
SET_PARAMETER Inject_Sbit_Error_axis false
|
||||
SET_PARAMETER Inject_Dbit_Error_axis false
|
||||
SET_PARAMETER Input_Depth_axis 1024
|
||||
SET_PARAMETER Enable_Data_Counts_axis false
|
||||
SET_PARAMETER Programmable_Full_Type_axis No_Programmable_Full_Threshold
|
||||
SET_PARAMETER Full_Threshold_Assert_Value_axis 1023
|
||||
SET_PARAMETER Programmable_Empty_Type_axis No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER Empty_Threshold_Assert_Value_axis 1022
|
||||
SET_PARAMETER Register_Slice_Mode_wach Fully_Registered
|
||||
SET_PARAMETER Register_Slice_Mode_wdch Fully_Registered
|
||||
SET_PARAMETER Register_Slice_Mode_wrch Fully_Registered
|
||||
SET_PARAMETER Register_Slice_Mode_rach Fully_Registered
|
||||
SET_PARAMETER Register_Slice_Mode_rdch Fully_Registered
|
||||
SET_PARAMETER Register_Slice_Mode_axis Fully_Registered
|
||||
SET_PARAMETER Underflow_Flag_AXI false
|
||||
SET_PARAMETER Underflow_Sense_AXI Active_High
|
||||
SET_PARAMETER Overflow_Flag_AXI false
|
||||
SET_PARAMETER Overflow_Sense_AXI Active_High
|
||||
SET_PARAMETER Disable_Timing_Violations_AXI false
|
||||
SET_PARAMETER Add_NGC_Constraint_AXI false
|
||||
SET_PARAMETER Enable_Common_Underflow false
|
||||
SET_PARAMETER Enable_Common_Overflow false
|
||||
SET_PARAMETER enable_read_pointer_increment_by2 false
|
||||
SET_SIM_PARAMETER c_common_clock 0
|
||||
SET_SIM_PARAMETER c_data_count_width 4
|
||||
SET_SIM_PARAMETER c_din_width 69
|
||||
SET_SIM_PARAMETER c_dout_rst_val 0
|
||||
SET_SIM_PARAMETER c_dout_width 69
|
||||
SET_SIM_PARAMETER c_family spartan3
|
||||
SET_SIM_PARAMETER c_full_flags_rst_val 1
|
||||
SET_SIM_PARAMETER c_has_almost_empty 0
|
||||
SET_SIM_PARAMETER c_has_almost_full 0
|
||||
SET_SIM_PARAMETER c_has_data_count 0
|
||||
SET_SIM_PARAMETER c_has_int_clk 0
|
||||
SET_SIM_PARAMETER c_has_overflow 0
|
||||
SET_SIM_PARAMETER c_has_rd_data_count 0
|
||||
SET_SIM_PARAMETER c_has_rst 1
|
||||
SET_SIM_PARAMETER c_has_srst 0
|
||||
SET_SIM_PARAMETER c_has_underflow 0
|
||||
SET_SIM_PARAMETER c_has_valid 0
|
||||
SET_SIM_PARAMETER c_has_wr_ack 0
|
||||
SET_SIM_PARAMETER c_has_wr_data_count 0
|
||||
SET_SIM_PARAMETER c_implementation_type 2
|
||||
SET_SIM_PARAMETER c_memory_type 2
|
||||
SET_SIM_PARAMETER c_overflow_low 0
|
||||
SET_SIM_PARAMETER c_preload_latency 1
|
||||
SET_SIM_PARAMETER c_preload_regs 0
|
||||
SET_SIM_PARAMETER c_prim_fifo_type 512x72
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val 2
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_negate_val 3
|
||||
SET_SIM_PARAMETER c_prog_empty_type 0
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val 13
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_negate_val 12
|
||||
SET_SIM_PARAMETER c_prog_full_type 0
|
||||
SET_SIM_PARAMETER c_rd_data_count_width 4
|
||||
SET_SIM_PARAMETER c_rd_depth 16
|
||||
SET_SIM_PARAMETER c_rd_freq 1
|
||||
SET_SIM_PARAMETER c_rd_pntr_width 4
|
||||
SET_SIM_PARAMETER c_underflow_low 0
|
||||
SET_SIM_PARAMETER c_use_dout_rst 1
|
||||
SET_SIM_PARAMETER c_use_ecc 0
|
||||
SET_SIM_PARAMETER c_use_embedded_reg 0
|
||||
SET_SIM_PARAMETER c_use_fwft_data_count 0
|
||||
SET_SIM_PARAMETER c_valid_low 0
|
||||
SET_SIM_PARAMETER c_wr_ack_low 0
|
||||
SET_SIM_PARAMETER c_wr_data_count_width 4
|
||||
SET_SIM_PARAMETER c_wr_depth 16
|
||||
SET_SIM_PARAMETER c_wr_freq 1
|
||||
SET_SIM_PARAMETER c_wr_pntr_width 4
|
||||
SET_SIM_PARAMETER c_msgon_val 0
|
||||
SET_SIM_PARAMETER c_enable_rst_sync 1
|
||||
SET_SIM_PARAMETER c_error_injection_type 0
|
||||
SET_SIM_PARAMETER c_synchronizer_stage 2
|
||||
SET_SIM_PARAMETER c_interface_type 0
|
||||
SET_SIM_PARAMETER c_axi_type 0
|
||||
SET_SIM_PARAMETER c_has_axi_wr_channel 0
|
||||
SET_SIM_PARAMETER c_has_axi_rd_channel 0
|
||||
SET_SIM_PARAMETER c_has_slave_ce 0
|
||||
SET_SIM_PARAMETER c_has_master_ce 0
|
||||
SET_SIM_PARAMETER c_add_ngc_constraint 0
|
||||
SET_SIM_PARAMETER c_use_common_overflow 0
|
||||
SET_SIM_PARAMETER c_use_common_underflow 0
|
||||
SET_SIM_PARAMETER c_axi_id_width 4
|
||||
SET_SIM_PARAMETER c_axi_addr_width 32
|
||||
SET_SIM_PARAMETER c_axi_data_width 64
|
||||
SET_SIM_PARAMETER c_has_axi_awuser 0
|
||||
SET_SIM_PARAMETER c_has_axi_wuser 0
|
||||
SET_SIM_PARAMETER c_has_axi_buser 0
|
||||
SET_SIM_PARAMETER c_has_axi_aruser 0
|
||||
SET_SIM_PARAMETER c_has_axi_ruser 0
|
||||
SET_SIM_PARAMETER c_axi_aruser_width 1
|
||||
SET_SIM_PARAMETER c_axi_awuser_width 1
|
||||
SET_SIM_PARAMETER c_axi_wuser_width 1
|
||||
SET_SIM_PARAMETER c_axi_buser_width 1
|
||||
SET_SIM_PARAMETER c_axi_ruser_width 1
|
||||
SET_SIM_PARAMETER c_has_axis_tdata 0
|
||||
SET_SIM_PARAMETER c_has_axis_tid 0
|
||||
SET_SIM_PARAMETER c_has_axis_tdest 0
|
||||
SET_SIM_PARAMETER c_has_axis_tuser 0
|
||||
SET_SIM_PARAMETER c_has_axis_tready 1
|
||||
SET_SIM_PARAMETER c_has_axis_tlast 0
|
||||
SET_SIM_PARAMETER c_has_axis_tstrb 0
|
||||
SET_SIM_PARAMETER c_has_axis_tkeep 0
|
||||
SET_SIM_PARAMETER c_axis_tdata_width 64
|
||||
SET_SIM_PARAMETER c_axis_tid_width 8
|
||||
SET_SIM_PARAMETER c_axis_tdest_width 4
|
||||
SET_SIM_PARAMETER c_axis_tuser_width 4
|
||||
SET_SIM_PARAMETER c_axis_tstrb_width 4
|
||||
SET_SIM_PARAMETER c_axis_tkeep_width 4
|
||||
SET_SIM_PARAMETER c_wach_type 0
|
||||
SET_SIM_PARAMETER c_wdch_type 0
|
||||
SET_SIM_PARAMETER c_wrch_type 0
|
||||
SET_SIM_PARAMETER c_rach_type 0
|
||||
SET_SIM_PARAMETER c_rdch_type 0
|
||||
SET_SIM_PARAMETER c_axis_type 0
|
||||
SET_SIM_PARAMETER c_implementation_type_wach 1
|
||||
SET_SIM_PARAMETER c_implementation_type_wdch 1
|
||||
SET_SIM_PARAMETER c_implementation_type_wrch 1
|
||||
SET_SIM_PARAMETER c_implementation_type_rach 1
|
||||
SET_SIM_PARAMETER c_implementation_type_rdch 1
|
||||
SET_SIM_PARAMETER c_implementation_type_axis 1
|
||||
SET_SIM_PARAMETER c_application_type_wach 0
|
||||
SET_SIM_PARAMETER c_application_type_wdch 0
|
||||
SET_SIM_PARAMETER c_application_type_wrch 0
|
||||
SET_SIM_PARAMETER c_application_type_rach 0
|
||||
SET_SIM_PARAMETER c_application_type_rdch 0
|
||||
SET_SIM_PARAMETER c_application_type_axis 0
|
||||
SET_SIM_PARAMETER c_use_ecc_wach 0
|
||||
SET_SIM_PARAMETER c_use_ecc_wdch 0
|
||||
SET_SIM_PARAMETER c_use_ecc_wrch 0
|
||||
SET_SIM_PARAMETER c_use_ecc_rach 0
|
||||
SET_SIM_PARAMETER c_use_ecc_rdch 0
|
||||
SET_SIM_PARAMETER c_use_ecc_axis 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_wach 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_wdch 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_wrch 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_rach 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_rdch 0
|
||||
SET_SIM_PARAMETER c_error_injection_type_axis 0
|
||||
SET_SIM_PARAMETER c_din_width_wach 32
|
||||
SET_SIM_PARAMETER c_din_width_wdch 64
|
||||
SET_SIM_PARAMETER c_din_width_wrch 2
|
||||
SET_SIM_PARAMETER c_din_width_rach 32
|
||||
SET_SIM_PARAMETER c_din_width_rdch 64
|
||||
SET_SIM_PARAMETER c_din_width_axis 1
|
||||
SET_SIM_PARAMETER c_wr_depth_wach 16
|
||||
SET_SIM_PARAMETER c_wr_depth_wdch 1024
|
||||
SET_SIM_PARAMETER c_wr_depth_wrch 16
|
||||
SET_SIM_PARAMETER c_wr_depth_rach 16
|
||||
SET_SIM_PARAMETER c_wr_depth_rdch 1024
|
||||
SET_SIM_PARAMETER c_wr_depth_axis 1024
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_wach 4
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_wdch 10
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_wrch 4
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_rach 4
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_rdch 10
|
||||
SET_SIM_PARAMETER c_wr_pntr_width_axis 10
|
||||
SET_SIM_PARAMETER c_has_data_counts_wach 0
|
||||
SET_SIM_PARAMETER c_has_data_counts_wdch 0
|
||||
SET_SIM_PARAMETER c_has_data_counts_wrch 0
|
||||
SET_SIM_PARAMETER c_has_data_counts_rach 0
|
||||
SET_SIM_PARAMETER c_has_data_counts_rdch 0
|
||||
SET_SIM_PARAMETER c_has_data_counts_axis 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_wach 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_wdch 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_wrch 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_rach 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_rdch 0
|
||||
SET_SIM_PARAMETER c_prog_full_type_axis 0
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_wach 1023
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_wdch 1023
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_wrch 1023
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_rach 1023
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_rdch 1023
|
||||
SET_SIM_PARAMETER c_prog_full_thresh_assert_val_axis 1023
|
||||
SET_SIM_PARAMETER c_prog_empty_type_wach 0
|
||||
SET_SIM_PARAMETER c_prog_empty_type_wdch 0
|
||||
SET_SIM_PARAMETER c_prog_empty_type_wrch 0
|
||||
SET_SIM_PARAMETER c_prog_empty_type_rach 0
|
||||
SET_SIM_PARAMETER c_prog_empty_type_rdch 0
|
||||
SET_SIM_PARAMETER c_prog_empty_type_axis 0
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_wach 1022
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_wdch 1022
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_wrch 1022
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_rach 1022
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_rdch 1022
|
||||
SET_SIM_PARAMETER c_prog_empty_thresh_assert_val_axis 1022
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_wach 0
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_wdch 0
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_wrch 0
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_rach 0
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_rdch 0
|
||||
SET_SIM_PARAMETER c_reg_slice_mode_axis 0
|
||||
SET_CORE_NAME FIFO Generator
|
||||
SET_CORE_VERSION 9.3
|
||||
SET_CORE_VLNV xilinx.com:ip:fifo_generator:9.3
|
||||
SET_CORE_CLASS com.xilinx.ip.fifo_generator_v9_3.fifo_generator_v9_3
|
||||
SET_CORE_PATH /opt/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3
|
||||
SET_CORE_GUIPATH /opt/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3/gui/fifo_generator_v9_3.tcl
|
||||
ADD_CORE_DOCUMENT </opt/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3/doc/fifo_generator_v9_3_vinfo.html><fifo_generator_v9_3_vinfo.html>
|
||||
ADD_CORE_DOCUMENT </opt/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3/doc/fifo_generator_v9_3_readme.txt><fifo_generator_v9_3_readme.txt>
|
||||
ADD_CORE_DOCUMENT </opt/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3/doc/pg057-fifo-generator.pdf><pg057-fifo-generator.pdf>
|
||||
@@ -0,0 +1,169 @@
|
||||
SET_PARAMETER underflow_sense_axi Active_High
|
||||
SET_PARAMETER programmable_empty_type_wdch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER register_slice_mode_axis Fully_Registered
|
||||
SET_PARAMETER output_depth 16
|
||||
SET_PARAMETER enable_data_counts_wdch false
|
||||
SET_PARAMETER programmable_full_type No_Programmable_Full_Threshold
|
||||
SET_PARAMETER inject_dbit_error_wrch false
|
||||
SET_PARAMETER fifo_application_type_wdch Data_FIFO
|
||||
SET_PARAMETER input_data_width 69
|
||||
SET_PARAMETER programmable_full_type_axis No_Programmable_Full_Threshold
|
||||
SET_PARAMETER enable_tkeep false
|
||||
SET_PARAMETER register_slice_mode_wach Fully_Registered
|
||||
SET_PARAMETER enable_buser false
|
||||
SET_PARAMETER enable_read_channel false
|
||||
SET_PARAMETER enable_tid false
|
||||
SET_PARAMETER enable_wuser false
|
||||
SET_PARAMETER enable_awuser false
|
||||
SET_PARAMETER fifo_implementation_axis Common_Clock_Block_RAM
|
||||
SET_PARAMETER wuser_width 1
|
||||
SET_PARAMETER programmable_full_type_wach No_Programmable_Full_Threshold
|
||||
SET_PARAMETER enable_ecc_axis false
|
||||
SET_PARAMETER inject_sbit_error_axis false
|
||||
SET_PARAMETER tstrb_width 4
|
||||
SET_PARAMETER input_depth_axis 1024
|
||||
SET_PARAMETER dout_reset_value 0
|
||||
SET_PARAMETER write_acknowledge_flag false
|
||||
SET_PARAMETER id_width 4
|
||||
SET_PARAMETER fifo_implementation_wach Common_Clock_Block_RAM
|
||||
SET_PARAMETER buser_width 1
|
||||
SET_PARAMETER full_flags_reset_value 1
|
||||
SET_PARAMETER axis_type FIFO
|
||||
SET_PARAMETER full_threshold_assert_value_wdch 1023
|
||||
SET_PARAMETER tdata_width 64
|
||||
SET_PARAMETER enable_ecc_wach false
|
||||
SET_PARAMETER inject_sbit_error_wach false
|
||||
SET_PARAMETER input_depth_wach 16
|
||||
SET_PARAMETER write_clock_frequency 1
|
||||
SET_PARAMETER programmable_empty_type No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER register_slice_mode_rdch Fully_Registered
|
||||
SET_PARAMETER inject_dbit_error_wdch false
|
||||
SET_PARAMETER input_depth 16
|
||||
SET_PARAMETER overflow_sense_axi Active_High
|
||||
SET_PARAMETER tkeep_width 4
|
||||
SET_PARAMETER valid_flag false
|
||||
SET_PARAMETER empty_threshold_assert_value_rach 1022
|
||||
SET_PARAMETER enable_common_overflow false
|
||||
SET_PARAMETER programmable_full_type_rdch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER wach_type FIFO
|
||||
SET_PARAMETER register_slice_mode_wrch Fully_Registered
|
||||
SET_PARAMETER fifo_implementation_rdch Common_Clock_Block_RAM
|
||||
SET_PARAMETER programmable_full_type_wrch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER enable_common_underflow false
|
||||
SET_PARAMETER overflow_sense Active_High
|
||||
SET_PARAMETER clock_type_axi Common_Clock
|
||||
SET_PARAMETER inject_dbit_error false
|
||||
SET_PARAMETER enable_tdata false
|
||||
SET_PARAMETER enable_ecc_rdch false
|
||||
SET_PARAMETER inject_sbit_error_rdch false
|
||||
SET_PARAMETER data_count_width 4
|
||||
SET_PARAMETER input_depth_rdch 1024
|
||||
SET_PARAMETER clock_enable_type Slave_Interface_Clock_Enable
|
||||
SET_PARAMETER awuser_width 1
|
||||
SET_PARAMETER fifo_implementation_wrch Common_Clock_Block_RAM
|
||||
SET_PARAMETER valid_sense Active_High
|
||||
SET_PARAMETER enable_tuser false
|
||||
SET_PARAMETER output_data_width 69
|
||||
SET_PARAMETER enable_ecc_wrch false
|
||||
SET_PARAMETER inject_sbit_error_wrch false
|
||||
SET_PARAMETER programmable_empty_type_rach No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER input_depth_wrch 16
|
||||
SET_PARAMETER enable_data_counts_rach false
|
||||
SET_PARAMETER full_threshold_assert_value 13
|
||||
SET_PARAMETER fifo_application_type_rach Data_FIFO
|
||||
SET_PARAMETER add_ngc_constraint_axi false
|
||||
SET_PARAMETER write_data_count_width 4
|
||||
SET_PARAMETER overflow_flag false
|
||||
SET_PARAMETER disable_timing_violations_axi false
|
||||
SET_PARAMETER empty_threshold_assert_value_axis 1022
|
||||
SET_PARAMETER tdest_width 4
|
||||
SET_PARAMETER rach_type FIFO
|
||||
SET_PARAMETER disable_timing_violations true
|
||||
SET_PARAMETER register_slice_mode_wdch Fully_Registered
|
||||
SET_PARAMETER overflow_flag_axi false
|
||||
SET_PARAMETER synchronization_stages 2
|
||||
SET_PARAMETER reset_pin true
|
||||
SET_PARAMETER fifo_implementation Independent_Clocks_Distributed_RAM
|
||||
SET_PARAMETER empty_threshold_assert_value_wach 1022
|
||||
SET_PARAMETER programmable_full_type_wdch No_Programmable_Full_Threshold
|
||||
SET_PARAMETER enable_tstrobe false
|
||||
SET_PARAMETER full_threshold_assert_value_rach 1023
|
||||
SET_PARAMETER fifo_implementation_wdch Common_Clock_Block_RAM
|
||||
SET_PARAMETER enable_ecc_wdch false
|
||||
SET_PARAMETER programmable_empty_type_axis No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER empty_threshold_assert_value 2
|
||||
SET_PARAMETER inject_sbit_error_wdch false
|
||||
SET_PARAMETER data_count false
|
||||
SET_PARAMETER enable_data_counts_axis false
|
||||
SET_PARAMETER input_depth_wdch 1024
|
||||
SET_PARAMETER enable_tlast false
|
||||
SET_PARAMETER inject_dbit_error_rach false
|
||||
SET_PARAMETER fifo_application_type_axis Data_FIFO
|
||||
SET_PARAMETER inject_sbit_error false
|
||||
SET_PARAMETER use_extra_logic false
|
||||
SET_PARAMETER underflow_flag_axi false
|
||||
SET_PARAMETER programmable_empty_type_wach No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER enable_data_counts_wach false
|
||||
SET_PARAMETER component_name wb_ddr_ctrl_wb_to_ddr
|
||||
SET_PARAMETER underflow_sense Active_High
|
||||
SET_PARAMETER empty_threshold_assert_value_rdch 1022
|
||||
SET_PARAMETER enable_write_channel false
|
||||
SET_PARAMETER wdch_type FIFO
|
||||
SET_PARAMETER ruser_width 1
|
||||
SET_PARAMETER fifo_application_type_wach Data_FIFO
|
||||
SET_PARAMETER enable_read_pointer_increment_by2 false
|
||||
SET_PARAMETER read_clock_frequency 1
|
||||
SET_PARAMETER full_threshold_negate_value 12
|
||||
SET_PARAMETER empty_threshold_assert_value_wrch 1022
|
||||
SET_PARAMETER almost_empty_flag false
|
||||
SET_PARAMETER underflow_flag false
|
||||
SET_PARAMETER full_threshold_assert_value_axis 1023
|
||||
SET_PARAMETER interface_type Native
|
||||
SET_PARAMETER reset_type Asynchronous_Reset
|
||||
SET_PARAMETER wrch_type FIFO
|
||||
SET_PARAMETER use_dout_reset true
|
||||
SET_PARAMETER read_data_count_width 4
|
||||
SET_PARAMETER read_data_count false
|
||||
SET_PARAMETER inject_dbit_error_axis false
|
||||
SET_PARAMETER programmable_empty_type_rdch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER full_threshold_assert_value_wach 1023
|
||||
SET_PARAMETER enable_data_counts_rdch false
|
||||
SET_PARAMETER axi_data_width 64
|
||||
SET_PARAMETER fifo_application_type_rdch Data_FIFO
|
||||
SET_PARAMETER write_data_count false
|
||||
SET_PARAMETER almost_full_flag false
|
||||
SET_PARAMETER write_acknowledge_sense Active_High
|
||||
SET_PARAMETER programmable_empty_type_wrch No_Programmable_Empty_Threshold
|
||||
SET_PARAMETER inject_dbit_error_wach false
|
||||
SET_PARAMETER register_slice_mode_rach Fully_Registered
|
||||
SET_PARAMETER rdch_type FIFO
|
||||
SET_PARAMETER tuser_width 4
|
||||
SET_PARAMETER enable_data_counts_wrch false
|
||||
SET_PARAMETER empty_threshold_negate_value 3
|
||||
SET_PARAMETER fifo_application_type_wrch Data_FIFO
|
||||
SET_PARAMETER enable_tready true
|
||||
SET_PARAMETER programmable_full_type_rach No_Programmable_Full_Threshold
|
||||
SET_PARAMETER use_clock_enable false
|
||||
SET_PARAMETER empty_threshold_assert_value_wdch 1022
|
||||
SET_PARAMETER aruser_width 1
|
||||
SET_PARAMETER enable_ruser false
|
||||
SET_PARAMETER use_embedded_registers false
|
||||
SET_PARAMETER performance_options Standard_FIFO
|
||||
SET_PARAMETER axi_type AXI4_Stream
|
||||
SET_PARAMETER enable_aruser false
|
||||
SET_PARAMETER enable_tdest false
|
||||
SET_PARAMETER fifo_implementation_rach Common_Clock_Block_RAM
|
||||
SET_PARAMETER full_threshold_assert_value_rdch 1023
|
||||
SET_PARAMETER enable_ecc_rach false
|
||||
SET_PARAMETER enable_reset_synchronization true
|
||||
SET_PARAMETER inject_sbit_error_rach false
|
||||
SET_PARAMETER axi_address_width 32
|
||||
SET_PARAMETER input_depth_rach 16
|
||||
SET_PARAMETER tid_width 8
|
||||
SET_PARAMETER full_threshold_assert_value_wrch 1023
|
||||
SET_PARAMETER synchronization_stages_axi 2
|
||||
SET_PARAMETER inject_dbit_error_rdch false
|
||||
SET_PARAMETER enable_ecc false
|
||||
SET_ERROR_CODE 2
|
||||
SET_ERROR_MSG CANCEL: Customization cancelled.
|
||||
SET_ERROR_TEXT Finished initializing IP model.
|
||||
@@ -0,0 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated -->
|
||||
<!-- by the Xilinx ISE software. Any direct editing or -->
|
||||
<!-- changes made to this file may result in unpredictable -->
|
||||
<!-- behavior or data corruption. It is strongly advised that -->
|
||||
<!-- users do not edit the contents of this file. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_0/tmp/_cg/wb_ddr_ctrl_wb_to_ddr.vhd" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 wb_ddr_ctrl_wb_to_ddr
|
||||
RECTANGLE Normal 32 32 800 4064
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName rst
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 208 32 208
|
||||
PIN 0 208 LEFT 36
|
||||
PINATTR PinName wr_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din[68:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName wr_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 464 32 464
|
||||
PIN 0 464 LEFT 36
|
||||
PINATTR PinName full
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 240 800 240
|
||||
PIN 832 240 RIGHT 36
|
||||
PINATTR PinName rd_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 832 272 800 272
|
||||
PIN 832 272 RIGHT 36
|
||||
PINATTR PinName dout[68:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 304 800 304
|
||||
PIN 832 304 RIGHT 36
|
||||
PINATTR PinName rd_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 832 496 800 496
|
||||
PIN 832 496 RIGHT 36
|
||||
PINATTR PinName empty
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="wb_ddr_ctrl_wb_to_ddr.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="wb_ddr_ctrl_wb_to_ddr.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="wb_ddr_ctrl_wb_to_ddr.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,283 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file wb_ddr_ctrl_wb_to_ddr.vhd when simulating
|
||||
-- the core, wb_ddr_ctrl_wb_to_ddr. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END wb_ddr_ctrl_wb_to_ddr;
|
||||
|
||||
ARCHITECTURE wb_ddr_ctrl_wb_to_ddr_a OF wb_ddr_ctrl_wb_to_ddr IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_wb_ddr_ctrl_wb_to_ddr
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_wb_ddr_ctrl_wb_to_ddr USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_add_ngc_constraint => 0,
|
||||
c_application_type_axis => 0,
|
||||
c_application_type_rach => 0,
|
||||
c_application_type_rdch => 0,
|
||||
c_application_type_wach => 0,
|
||||
c_application_type_wdch => 0,
|
||||
c_application_type_wrch => 0,
|
||||
c_axi_addr_width => 32,
|
||||
c_axi_aruser_width => 1,
|
||||
c_axi_awuser_width => 1,
|
||||
c_axi_buser_width => 1,
|
||||
c_axi_data_width => 64,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_ruser_width => 1,
|
||||
c_axi_type => 0,
|
||||
c_axi_wuser_width => 1,
|
||||
c_axis_tdata_width => 64,
|
||||
c_axis_tdest_width => 4,
|
||||
c_axis_tid_width => 8,
|
||||
c_axis_tkeep_width => 4,
|
||||
c_axis_tstrb_width => 4,
|
||||
c_axis_tuser_width => 4,
|
||||
c_axis_type => 0,
|
||||
c_common_clock => 0,
|
||||
c_count_type => 0,
|
||||
c_data_count_width => 4,
|
||||
c_default_value => "BlankString",
|
||||
c_din_width => 69,
|
||||
c_din_width_axis => 1,
|
||||
c_din_width_rach => 32,
|
||||
c_din_width_rdch => 64,
|
||||
c_din_width_wach => 32,
|
||||
c_din_width_wdch => 64,
|
||||
c_din_width_wrch => 2,
|
||||
c_dout_rst_val => "0",
|
||||
c_dout_width => 69,
|
||||
c_enable_rlocs => 0,
|
||||
c_enable_rst_sync => 1,
|
||||
c_error_injection_type => 0,
|
||||
c_error_injection_type_axis => 0,
|
||||
c_error_injection_type_rach => 0,
|
||||
c_error_injection_type_rdch => 0,
|
||||
c_error_injection_type_wach => 0,
|
||||
c_error_injection_type_wdch => 0,
|
||||
c_error_injection_type_wrch => 0,
|
||||
c_family => "spartan3",
|
||||
c_full_flags_rst_val => 1,
|
||||
c_has_almost_empty => 0,
|
||||
c_has_almost_full => 0,
|
||||
c_has_axi_aruser => 0,
|
||||
c_has_axi_awuser => 0,
|
||||
c_has_axi_buser => 0,
|
||||
c_has_axi_rd_channel => 0,
|
||||
c_has_axi_ruser => 0,
|
||||
c_has_axi_wr_channel => 0,
|
||||
c_has_axi_wuser => 0,
|
||||
c_has_axis_tdata => 0,
|
||||
c_has_axis_tdest => 0,
|
||||
c_has_axis_tid => 0,
|
||||
c_has_axis_tkeep => 0,
|
||||
c_has_axis_tlast => 0,
|
||||
c_has_axis_tready => 1,
|
||||
c_has_axis_tstrb => 0,
|
||||
c_has_axis_tuser => 0,
|
||||
c_has_backup => 0,
|
||||
c_has_data_count => 0,
|
||||
c_has_data_counts_axis => 0,
|
||||
c_has_data_counts_rach => 0,
|
||||
c_has_data_counts_rdch => 0,
|
||||
c_has_data_counts_wach => 0,
|
||||
c_has_data_counts_wdch => 0,
|
||||
c_has_data_counts_wrch => 0,
|
||||
c_has_int_clk => 0,
|
||||
c_has_master_ce => 0,
|
||||
c_has_meminit_file => 0,
|
||||
c_has_overflow => 0,
|
||||
c_has_prog_flags_axis => 0,
|
||||
c_has_prog_flags_rach => 0,
|
||||
c_has_prog_flags_rdch => 0,
|
||||
c_has_prog_flags_wach => 0,
|
||||
c_has_prog_flags_wdch => 0,
|
||||
c_has_prog_flags_wrch => 0,
|
||||
c_has_rd_data_count => 0,
|
||||
c_has_rd_rst => 0,
|
||||
c_has_rst => 1,
|
||||
c_has_slave_ce => 0,
|
||||
c_has_srst => 0,
|
||||
c_has_underflow => 0,
|
||||
c_has_valid => 0,
|
||||
c_has_wr_ack => 0,
|
||||
c_has_wr_data_count => 0,
|
||||
c_has_wr_rst => 0,
|
||||
c_implementation_type => 2,
|
||||
c_implementation_type_axis => 1,
|
||||
c_implementation_type_rach => 1,
|
||||
c_implementation_type_rdch => 1,
|
||||
c_implementation_type_wach => 1,
|
||||
c_implementation_type_wdch => 1,
|
||||
c_implementation_type_wrch => 1,
|
||||
c_init_wr_pntr_val => 0,
|
||||
c_interface_type => 0,
|
||||
c_memory_type => 2,
|
||||
c_mif_file_name => "BlankString",
|
||||
c_msgon_val => 0,
|
||||
c_optimization_mode => 0,
|
||||
c_overflow_low => 0,
|
||||
c_preload_latency => 1,
|
||||
c_preload_regs => 0,
|
||||
c_prim_fifo_type => "512x72",
|
||||
c_prog_empty_thresh_assert_val => 2,
|
||||
c_prog_empty_thresh_assert_val_axis => 1022,
|
||||
c_prog_empty_thresh_assert_val_rach => 1022,
|
||||
c_prog_empty_thresh_assert_val_rdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wach => 1022,
|
||||
c_prog_empty_thresh_assert_val_wdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wrch => 1022,
|
||||
c_prog_empty_thresh_negate_val => 3,
|
||||
c_prog_empty_type => 0,
|
||||
c_prog_empty_type_axis => 0,
|
||||
c_prog_empty_type_rach => 0,
|
||||
c_prog_empty_type_rdch => 0,
|
||||
c_prog_empty_type_wach => 0,
|
||||
c_prog_empty_type_wdch => 0,
|
||||
c_prog_empty_type_wrch => 0,
|
||||
c_prog_full_thresh_assert_val => 13,
|
||||
c_prog_full_thresh_assert_val_axis => 1023,
|
||||
c_prog_full_thresh_assert_val_rach => 1023,
|
||||
c_prog_full_thresh_assert_val_rdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wach => 1023,
|
||||
c_prog_full_thresh_assert_val_wdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wrch => 1023,
|
||||
c_prog_full_thresh_negate_val => 12,
|
||||
c_prog_full_type => 0,
|
||||
c_prog_full_type_axis => 0,
|
||||
c_prog_full_type_rach => 0,
|
||||
c_prog_full_type_rdch => 0,
|
||||
c_prog_full_type_wach => 0,
|
||||
c_prog_full_type_wdch => 0,
|
||||
c_prog_full_type_wrch => 0,
|
||||
c_rach_type => 0,
|
||||
c_rd_data_count_width => 4,
|
||||
c_rd_depth => 16,
|
||||
c_rd_freq => 1,
|
||||
c_rd_pntr_width => 4,
|
||||
c_rdch_type => 0,
|
||||
c_reg_slice_mode_axis => 0,
|
||||
c_reg_slice_mode_rach => 0,
|
||||
c_reg_slice_mode_rdch => 0,
|
||||
c_reg_slice_mode_wach => 0,
|
||||
c_reg_slice_mode_wdch => 0,
|
||||
c_reg_slice_mode_wrch => 0,
|
||||
c_synchronizer_stage => 2,
|
||||
c_underflow_low => 0,
|
||||
c_use_common_overflow => 0,
|
||||
c_use_common_underflow => 0,
|
||||
c_use_default_settings => 0,
|
||||
c_use_dout_rst => 1,
|
||||
c_use_ecc => 0,
|
||||
c_use_ecc_axis => 0,
|
||||
c_use_ecc_rach => 0,
|
||||
c_use_ecc_rdch => 0,
|
||||
c_use_ecc_wach => 0,
|
||||
c_use_ecc_wdch => 0,
|
||||
c_use_ecc_wrch => 0,
|
||||
c_use_embedded_reg => 0,
|
||||
c_use_fifo16_flags => 0,
|
||||
c_use_fwft_data_count => 0,
|
||||
c_valid_low => 0,
|
||||
c_wach_type => 0,
|
||||
c_wdch_type => 0,
|
||||
c_wr_ack_low => 0,
|
||||
c_wr_data_count_width => 4,
|
||||
c_wr_depth => 16,
|
||||
c_wr_depth_axis => 1024,
|
||||
c_wr_depth_rach => 16,
|
||||
c_wr_depth_rdch => 1024,
|
||||
c_wr_depth_wach => 16,
|
||||
c_wr_depth_wdch => 1024,
|
||||
c_wr_depth_wrch => 16,
|
||||
c_wr_freq => 1,
|
||||
c_wr_pntr_width => 4,
|
||||
c_wr_pntr_width_axis => 10,
|
||||
c_wr_pntr_width_rach => 4,
|
||||
c_wr_pntr_width_rdch => 10,
|
||||
c_wr_pntr_width_wach => 4,
|
||||
c_wr_pntr_width_wdch => 10,
|
||||
c_wr_pntr_width_wrch => 4,
|
||||
c_wr_response_latency => 1,
|
||||
c_wrch_type => 0
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_wb_ddr_ctrl_wb_to_ddr
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END wb_ddr_ctrl_wb_to_ddr_a;
|
||||
@@ -0,0 +1,95 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --
|
||||
-- --
|
||||
-- The FIFO Generator is a parameterizable first-in/first-out memory --
|
||||
-- queue generator. Use it to generate resource and performance --
|
||||
-- optimized FIFOs with common or independent read/write clock domains, --
|
||||
-- and optional fixed or programmable full and empty flags and --
|
||||
-- handshaking signals. Choose from a selection of memory resource --
|
||||
-- types for implementation. Optional Hamming code based error --
|
||||
-- detection and correction as well as error injection capability for --
|
||||
-- system test help to insure data integrity. FIFO width and depth are --
|
||||
-- parameterizable, and for native interface FIFOs, asymmetric read and --
|
||||
-- write port widths are also supported. --
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
-- Interfaces:
|
||||
-- AXI4Stream_MASTER_M_AXIS
|
||||
-- AXI4Stream_SLAVE_S_AXIS
|
||||
-- AXI4_MASTER_M_AXI
|
||||
-- AXI4_SLAVE_S_AXI
|
||||
-- AXI4Lite_MASTER_M_AXI
|
||||
-- AXI4Lite_SLAVE_S_AXI
|
||||
-- master_aclk
|
||||
-- slave_aclk
|
||||
-- slave_aresetn
|
||||
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(68 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : wb_ddr_ctrl_wb_to_ddr
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file wb_ddr_ctrl_wb_to_ddr.vhd when simulating
|
||||
-- the core, wb_ddr_ctrl_wb_to_ddr. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -0,0 +1,696 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>wb_ddr_ctrl_wb_to_ddr</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.backup">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.backup_marker">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rst">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.srst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_rst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_rst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.din">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.din">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh_assert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh_assert">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh_negate">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh_negate">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh_assert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh_assert">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh_negate">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh_negate">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.int_clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dout">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.dout">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.full">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.almost_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_ack">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.empty">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.almost_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.valid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.rd_data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.wr_data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aresetn">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_aclk_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aclk_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awaddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awaddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wstrb">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_bid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_buser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_buser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awaddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awaddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wstrb">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_bid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_buser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_buser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_arid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_araddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_araddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_aruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_aruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_rid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_rdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_ruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_ruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_arid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_araddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_araddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_aruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_aruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_rid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_rdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_ruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_ruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tstrb">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tkeep">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tkeep">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tid">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tdest">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tdest">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tuser">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tstrb">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tkeep">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tkeep">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tid">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tdest">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tdest">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tuser">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">wb_ddr_ctrl_wb_to_ddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">69</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">69</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Stream_SLAVE_S_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4_MASTER_M_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4_SLAVE_S_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Lite_MASTER_M_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Lite_SLAVE_S_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.master_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.slave_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.slave_aresetn">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">spartan3a</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc3s700an</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">FALSE</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,213 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.3
|
||||
# Date: Tue Nov 6 15:54:37 2012
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Common_Clock
|
||||
CSET component_name=wb_ddr_ctrl_wb_to_ddr
|
||||
CSET data_count=false
|
||||
CSET data_count_width=4
|
||||
CSET disable_timing_violations=true
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_assert_value_axis=1022
|
||||
CSET empty_threshold_assert_value_rach=1022
|
||||
CSET empty_threshold_assert_value_rdch=1022
|
||||
CSET empty_threshold_assert_value_wach=1022
|
||||
CSET empty_threshold_assert_value_wdch=1022
|
||||
CSET empty_threshold_assert_value_wrch=1022
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=false
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=false
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=false
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=false
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
|
||||
CSET fifo_implementation_axis=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=13
|
||||
CSET full_threshold_assert_value_axis=1023
|
||||
CSET full_threshold_assert_value_rach=1023
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=1023
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=1023
|
||||
CSET full_threshold_negate_value=12
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=69
|
||||
CSET input_depth=16
|
||||
CSET input_depth_axis=1024
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=Native
|
||||
CSET output_data_width=69
|
||||
CSET output_depth=16
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=4
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=4
|
||||
CSET tstrb_width=4
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=4
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-07-25T18:11:59Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 646c7c3d
|
||||
@@ -0,0 +1,398 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="wb_ddr_ctrl_wb_to_ddr.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="wb_ddr_ctrl_wb_to_ddr.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wb_ddr_ctrl_wb_to_ddr|wb_ddr_ctrl_wb_to_ddr_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="wb_ddr_ctrl_wb_to_ddr.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wb_ddr_ctrl_wb_to_ddr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="wb_ddr_ctrl_wb_to_ddr" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_to_ddr_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_to_ddr_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_to_ddr_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_to_ddr_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="wb_ddr_ctrl_wb_to_ddr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-06T16:56:49" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3B44DF4BCE8D4E65C7349779106063B0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,237 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,248 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>fifo_generator_v9_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,56 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "RD_CLK" TNM_NET = "RD_CLK";
|
||||
NET "WR_CLK" TNM_NET = "WR_CLK";
|
||||
TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ;
|
||||
TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ;
|
||||
################################################################################
|
||||
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core - core top file for implementation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the FIFO core wrapper with BUFG instances for clock connections.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
entity wb_ddr_ctrl_wb_to_ddr_exdes is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(69-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end wb_ddr_ctrl_wb_to_ddr_exdes;
|
||||
|
||||
|
||||
|
||||
architecture xilinx of wb_ddr_ctrl_wb_to_ddr_exdes is
|
||||
|
||||
signal wr_clk_i : std_logic;
|
||||
signal rd_clk_i : std_logic;
|
||||
|
||||
|
||||
|
||||
component wb_ddr_ctrl_wb_to_ddr is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(69-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wr_clk_buf: bufg
|
||||
PORT map(
|
||||
i => WR_CLK,
|
||||
o => wr_clk_i
|
||||
);
|
||||
|
||||
rd_clk_buf: bufg
|
||||
PORT map(
|
||||
i => RD_CLK,
|
||||
o => rd_clk_i
|
||||
);
|
||||
|
||||
|
||||
exdes_inst : wb_ddr_ctrl_wb_to_ddr
|
||||
PORT MAP (
|
||||
WR_CLK => wr_clk_i,
|
||||
RD_CLK => rd_clk_i,
|
||||
RST => rst,
|
||||
WR_EN => wr_en,
|
||||
RD_EN => rd_en,
|
||||
DIN => din,
|
||||
DOUT => dout,
|
||||
FULL => full,
|
||||
EMPTY => empty);
|
||||
|
||||
end xilinx;
|
||||
@@ -0,0 +1,68 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_RD_CLK" -period 1000.0 [ get_ports RD_CLK ]
|
||||
create_clock -name "TS_WR_CLK" -period 1000.0 [ get_ports WR_CLK ]
|
||||
|
||||
# Following are the constrains for Fifo Generator to eleminate setup/hold violation warnings in simulations
|
||||
# This example is using the Set False Path constrains we can also make use of the Max Delay constrains,
|
||||
# to use them just un-comment them and comment the False Path constrains
|
||||
|
||||
##set wr_q_nets [get_nets -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_q?0?* }]
|
||||
set wr_q_cell [get_cells -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_? }]
|
||||
|
||||
##set rd_q_nets [get_nets -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q?0?* }]
|
||||
set rd_q_cell [get_cells -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_? }]
|
||||
|
||||
set_false_path -from $rd_q_cell -through $rd_q_cell -to $rd_q_cell
|
||||
set_false_path -from $wr_q_cell -through $wr_q_cell -to $wr_q_cell
|
||||
|
||||
##set_max_delay -through $wr_q_nets -datapath_only 2000.0##set_max_delay -through $rd_q_nets -datapath_only 2000.0################################################################################
|
||||
@@ -0,0 +1,237 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,88 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy wb_ddr_ctrl_wb_to_ddr_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\wb_ddr_ctrl_wb_to_ddr.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\wb_ddr_ctrl_wb_to_ddr_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_to_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_to_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
@@ -0,0 +1,87 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
cp wb_ddr_ctrl_wb_to_ddr_exdes.ngc ./results/
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../wb_ddr_ctrl_wb_to_ddr.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_to_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_to_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\wb_ddr_ctrl_wb_to_ddr.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\wb_ddr_ctrl_wb_to_ddr_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_to_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_to_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
@@ -0,0 +1,86 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../wb_ddr_ctrl_wb_to_ddr.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_to_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_to_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem -----------------------------------------------------------------------------
|
||||
rem Script to synthesize and implement the Coregen FIFO Generator
|
||||
rem -----------------------------------------------------------------------------
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
cd results
|
||||
copy ..\..\..\wb_ddr_ctrl_wb_to_ddr.ngc .
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -0,0 +1,55 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the Coregen FIFO Generator
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
cp ../../../wb_ddr_ctrl_wb_to_ddr.ngc .
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -0,0 +1,67 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
set device xc3s700anfgg484-4
|
||||
set projName wb_ddr_ctrl_wb_to_ddr
|
||||
set design wb_ddr_ctrl_wb_to_ddr
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
add_files -norecurse {../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd}
|
||||
add_files -norecurse {./wb_ddr_ctrl_wb_to_ddr.ngc}
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.xdc}
|
||||
set_property top wb_ddr_ctrl_wb_to_ddr_exdes [get_property srcset [current_run]]
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module wb_ddr_ctrl_wb_to_ddr_exdes -file routed.sdf
|
||||
write_vhdl -mode sim routed.vhd
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
|
||||
@@ -0,0 +1 @@
|
||||
work ../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
@@ -0,0 +1,13 @@
|
||||
run
|
||||
-ifmt VHDL
|
||||
-ent wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
-p xc3s1400a-fg676-4
|
||||
-ifn xst.prj
|
||||
-write_timing_constraints No
|
||||
-iobuf YES
|
||||
-max_fanout 100
|
||||
-ofn wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
-ofmt NGC
|
||||
-bus_delimiter ()
|
||||
-hierarchy_separator /
|
||||
-case Maintain
|
||||
@@ -0,0 +1,62 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhpcomp -work work ..\\..\\..\\wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
vhpcomp -work work ..\\..\\example_design\\wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
fuse work.wb_ddr_ctrl_wb_to_ddr_tb -L xilinxcorelib -L unisim -o wb_ddr_ctrl_wb_to_ddr_tb.exe
|
||||
|
||||
.\\wb_ddr_ctrl_wb_to_ddr_tb.exe -gui -tclbatch .\\wave_isim.tcl
|
||||
@@ -0,0 +1,64 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhpcomp -work work ../../../wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
vhpcomp -work work ../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
fuse work.wb_ddr_ctrl_wb_to_ddr_tb -L xilinxcorelib -L unisim -o wb_ddr_ctrl_wb_to_ddr_tb.exe
|
||||
|
||||
./wb_ddr_ctrl_wb_to_ddr_tb.exe -gui -tclbatch ./wave_isim.tcl
|
||||
@@ -0,0 +1,47 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -0,0 +1,73 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vcom -work work ../../../wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
vcom -work work ../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
vsim -t ps -voptargs="+acc" -L XilinxCoreLib -L unisim work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
add log -r /*
|
||||
do wave_mti.do
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
@@ -0,0 +1,49 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -0,0 +1,68 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
mkdir work
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
ncvhdl -v93 -work work ../../../wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
ncvhdl -v93 -work work ../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncelab -access +rwc work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhdlan ../../../wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
vhdlan ../../example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
vcs -time_res 1ps +vcs+lic+wait -debug wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
@@ -0,0 +1,4 @@
|
||||
dump -file wb_ddr_ctrl_wb_to_ddr.vpd -type VPD
|
||||
dump -add wb_ddr_ctrl_wb_to_ddr_tb
|
||||
run
|
||||
quit
|
||||
@@ -0,0 +1,77 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
if { ![gui_is_db_opened -db {wb_ddr_ctrl_wb_to_ddr.vpd}] } {
|
||||
gui_open_db -design V1 -file wb_ddr_ctrl_wb_to_ddr.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create wb_ddr_ctrl_wb_to_ddr_Group
|
||||
gui_list_add_group -id Wave.1 {wb_ddr_ctrl_wb_to_ddr_Group}
|
||||
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group WRITE -divider
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group READ -divider
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -0,0 +1,68 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_isim.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the ISIM wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
run all
|
||||
quit
|
||||
|
||||
@@ -0,0 +1,88 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_mti.do
|
||||
#
|
||||
# Description:
|
||||
# This is the modelsim wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
add wave -noupdate -divider WRITE
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
add wave -noupdate -radix hexadecimal /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/DIN
|
||||
add wave -noupdate -divider READ
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
add wave -noupdate -radix hexadecimal /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/DOUT
|
||||
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
|
||||
configure wave -namecolwidth 197
|
||||
configure wave -valuecolwidth 106
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {9464063 ps}
|
||||
@@ -0,0 +1,70 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_ncsim.sv
|
||||
#
|
||||
# Description:
|
||||
# This is the IUS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
window new WaveWindow -name "Waves for FIFO Generator Example Design"
|
||||
waveform using "Waves for FIFO Generator Example Design"
|
||||
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
waveform add -label WRITE
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
waveform add -label READ
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
console submit -using simulator -wait no "run"
|
||||
@@ -0,0 +1,61 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhpcomp -work work ..\\..\\implement\\results\\routed.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhpcomp -work work ..\\wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
fuse work.wb_ddr_ctrl_wb_to_ddr_tb -L simprim -o wb_ddr_ctrl_wb_to_ddr_tb.exe
|
||||
|
||||
.\\wb_ddr_ctrl_wb_to_ddr_tb.exe -sdfmax /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl
|
||||
@@ -0,0 +1,63 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhpcomp -work work ../../implement/results/routed.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhpcomp -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
fuse work.wb_ddr_ctrl_wb_to_ddr_tb -L simprim -o wb_ddr_ctrl_wb_to_ddr_tb.exe
|
||||
|
||||
./wb_ddr_ctrl_wb_to_ddr_tb.exe -sdfmax /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl
|
||||
@@ -0,0 +1,47 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -0,0 +1,72 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vcom -work work ../../implement/results/routed.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vcom -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
vsim -t ps -voptargs="+acc" +transport_int_delays -L simprim -sdfmax /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst=../../implement/results/routed.sdf work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
add log -r /*
|
||||
do wave_mti.do
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
@@ -0,0 +1,49 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -0,0 +1,73 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
mkdir work
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
ncvhdl -v93 -work work ../../implement/results/routed.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
ncvhdl -v93 -work work ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
echo "Compiling SDF file"
|
||||
ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
|
||||
|
||||
echo "Generating SDF command file"
|
||||
echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
|
||||
echo 'SCOPE = :wb_ddr_ctrl_wb_to_ddr_synth_inst:wb_ddr_ctrl_wb_to_ddr_inst,' >> sdf.cmd
|
||||
echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncelab -access +rwc -sdf_cmd_file sdf.cmd work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.wb_ddr_ctrl_wb_to_ddr_tb
|
||||
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core VHDL UNISIM/Behavioral model"
|
||||
vhdlan ../../implement/results/routed.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
vhdlan ../wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
vcs -time_res 1ps +neg_tchk +vcs+lic+wait -debug wb_ddr_ctrl_wb_to_ddr_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
@@ -0,0 +1,4 @@
|
||||
dump -file wb_ddr_ctrl_wb_to_ddr.vpd -type VPD
|
||||
dump -add wb_ddr_ctrl_wb_to_ddr_tb
|
||||
run
|
||||
quit
|
||||
@@ -0,0 +1,76 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
if { ![gui_is_db_opened -db {wb_ddr_ctrl_wb_to_ddr.vpd}] } {
|
||||
gui_open_db -design V1 -file wb_ddr_ctrl_wb_to_ddr.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create wb_ddr_ctrl_wb_to_ddr_Group
|
||||
gui_list_add_group -id Wave.1 {wb_ddr_ctrl_wb_to_ddr_Group}
|
||||
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group WRITE -divider
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group READ -divider
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
gui_sg_addsignal -group wb_ddr_ctrl_wb_to_ddr_Group /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -0,0 +1,68 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_isim.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the ISIM wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
wave add /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
run all
|
||||
quit
|
||||
|
||||
@@ -0,0 +1,88 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_mti.do
|
||||
#
|
||||
# Description:
|
||||
# This is the modelsim wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
add wave -noupdate -divider WRITE
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
add wave -noupdate -radix hexadecimal /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/DIN
|
||||
add wave -noupdate -divider READ
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
add wave -noupdate /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
add wave -noupdate -radix hexadecimal /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/DOUT
|
||||
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
|
||||
configure wave -namecolwidth 197
|
||||
configure wave -valuecolwidth 106
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {9464063 ps}
|
||||
@@ -0,0 +1,70 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: wave_ncsim.sv
|
||||
#
|
||||
# Description:
|
||||
# This is the IUS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
window new WaveWindow -name "Waves for FIFO Generator Example Design"
|
||||
waveform using "Waves for FIFO Generator Example Design"
|
||||
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RST
|
||||
waveform add -label WRITE
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_CLK
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/WR_EN
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/FULL
|
||||
waveform add -label READ
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_CLK
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/RD_EN
|
||||
waveform add -signals /wb_ddr_ctrl_wb_to_ddr_tb/wb_ddr_ctrl_wb_to_ddr_synth_inst/wb_ddr_ctrl_wb_to_ddr_inst/EMPTY
|
||||
console submit -using simulator -wait no "run"
|
||||
@@ -0,0 +1,123 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for write interface stimulus generation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.wb_ddr_ctrl_wb_to_ddr_pkg.ALL;
|
||||
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_dgen IS
|
||||
GENERIC (
|
||||
C_DIN_WIDTH : INTEGER := 32;
|
||||
C_DOUT_WIDTH : INTEGER := 32;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT (
|
||||
RESET : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
PRC_WR_EN : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
WR_EN : OUT STD_LOGIC;
|
||||
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_dg_arch OF wb_ddr_ctrl_wb_to_ddr_dgen IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
|
||||
|
||||
SIGNAL pr_w_en : STD_LOGIC := '0';
|
||||
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
|
||||
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
BEGIN
|
||||
|
||||
WR_EN <= PRC_WR_EN ;
|
||||
WR_DATA <= wr_data_i AFTER 50 ns;
|
||||
|
||||
----------------------------------------------
|
||||
-- Generation of DATA
|
||||
----------------------------------------------
|
||||
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
rd_gen_inst1:wb_ddr_ctrl_wb_to_ddr_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+N
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => WR_CLK,
|
||||
RESET => RESET,
|
||||
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
|
||||
ENABLE => pr_w_en
|
||||
);
|
||||
END GENERATE;
|
||||
|
||||
pr_w_en <= PRC_WR_EN AND NOT FULL;
|
||||
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,159 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for FIFO read interface stimulus generation and data checking
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.wb_ddr_ctrl_wb_to_ddr_pkg.ALL;
|
||||
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_dverif IS
|
||||
GENERIC(
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_USE_EMBEDDED_REG : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
PRC_RD_EN : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
RD_EN : OUT STD_LOGIC;
|
||||
DOUT_CHK : OUT STD_LOGIC
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_dv_arch OF wb_ddr_ctrl_wb_to_ddr_dverif IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
|
||||
|
||||
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL data_chk : STD_LOGIC := '1';
|
||||
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
|
||||
SIGNAL rd_en_i : STD_LOGIC := '0';
|
||||
SIGNAL pr_r_en : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_d1 : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
|
||||
|
||||
DOUT_CHK <= data_chk;
|
||||
RD_EN <= rd_en_i;
|
||||
rd_en_i <= PRC_RD_EN;
|
||||
|
||||
|
||||
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
|
||||
-------------------------------------------------------
|
||||
-- Expected data generation and checking for data_fifo
|
||||
-------------------------------------------------------
|
||||
PROCESS (RD_CLK,RESET)
|
||||
BEGIN
|
||||
IF (RESET = '1') THEN
|
||||
rd_en_d1 <= '0';
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
|
||||
rd_en_d1 <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
|
||||
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
|
||||
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
rd_gen_inst2:wb_ddr_ctrl_wb_to_ddr_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+N
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => RD_CLK,
|
||||
RESET => RESET,
|
||||
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
|
||||
ENABLE => pr_r_en
|
||||
);
|
||||
END GENERATE;
|
||||
|
||||
PROCESS (RD_CLK,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
data_chk <= '0';
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
|
||||
IF(DATA_OUT = expected_dout) THEN
|
||||
data_chk <= '0';
|
||||
ELSE
|
||||
data_chk <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE data_fifo_chk;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,541 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for protocol control on write and read interface stimulus and status generation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.wb_ddr_ctrl_wb_to_ddr_pkg.ALL;
|
||||
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_pctrl IS
|
||||
GENERIC(
|
||||
AXI_CHANNEL : STRING :="NONE";
|
||||
C_APPLICATION_TYPE : INTEGER := 0;
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_WR_PNTR_WIDTH : INTEGER := 0;
|
||||
C_RD_PNTR_WIDTH : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 2;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET_WR : IN STD_LOGIC;
|
||||
RESET_RD : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
ALMOST_FULL : IN STD_LOGIC;
|
||||
ALMOST_EMPTY : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
DOUT_CHK : IN STD_LOGIC;
|
||||
PRC_WR_EN : OUT STD_LOGIC;
|
||||
PRC_RD_EN : OUT STD_LOGIC;
|
||||
RESET_EN : OUT STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_pc_arch OF wb_ddr_ctrl_wb_to_ddr_pctrl IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
|
||||
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
|
||||
|
||||
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_en_i : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_i : STD_LOGIC := '0';
|
||||
SIGNAL state : STD_LOGIC := '0';
|
||||
SIGNAL wr_control : STD_LOGIC := '0';
|
||||
SIGNAL rd_control : STD_LOGIC := '0';
|
||||
SIGNAL stop_on_err : STD_LOGIC := '0';
|
||||
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
|
||||
SIGNAL sim_done_i : STD_LOGIC := '0';
|
||||
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
|
||||
SIGNAL prc_we_i : STD_LOGIC := '0';
|
||||
SIGNAL prc_re_i : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_i : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_d1 : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL empty_d1 : STD_LOGIC := '0';
|
||||
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
|
||||
SIGNAL state_d1 : STD_LOGIC := '0';
|
||||
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_d1 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
|
||||
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
|
||||
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
|
||||
BEGIN
|
||||
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
|
||||
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
|
||||
|
||||
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
|
||||
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
|
||||
|
||||
SIM_DONE <= sim_done_i;
|
||||
rdw_gt_wrw <= (OTHERS => '1');
|
||||
wrw_gt_rdw <= (OTHERS => '1');
|
||||
|
||||
PROCESS(RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(prc_re_i = '1') THEN
|
||||
rd_activ_cont <= rd_activ_cont + "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(sim_done_i)
|
||||
BEGIN
|
||||
assert sim_done_i = '0'
|
||||
report "Simulation Complete for:" & AXI_CHANNEL
|
||||
severity note;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- SIM_DONE SIGNAL GENERATION
|
||||
-----------------------------------------------------
|
||||
PROCESS (RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
--sim_done_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
|
||||
sim_done_i <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- TB Timeout/Stop
|
||||
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
|
||||
PROCESS (RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
|
||||
sim_stop_cntr <= sim_stop_cntr - "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE fifo_tb_stop_run;
|
||||
|
||||
|
||||
-- Stop when error found
|
||||
PROCESS (RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(sim_done_i = '0') THEN
|
||||
status_d1_i <= status_i OR status_d1_i;
|
||||
END IF;
|
||||
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
|
||||
stop_on_err <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
-----------------------------------------------------
|
||||
|
||||
-----------------------------------------------------
|
||||
-- CHECKS FOR FIFO
|
||||
-----------------------------------------------------
|
||||
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
post_rst_dly_rd <= (OTHERS => '1');
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
post_rst_dly_wr <= (OTHERS => '1');
|
||||
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- FULL de-assert Counter
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
full_ds_timeout <= (OTHERS => '0');
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
|
||||
full_ds_timeout <= full_ds_timeout + '1';
|
||||
END IF;
|
||||
ELSE
|
||||
full_ds_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- EMPTY deassert counter
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_ds_timeout <= (OTHERS => '0');
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state = '0') THEN
|
||||
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
|
||||
empty_ds_timeout <= empty_ds_timeout + '1';
|
||||
END IF;
|
||||
ELSE
|
||||
empty_ds_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- Full check signal generation
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
full_chk_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
|
||||
full_chk_i <= '0';
|
||||
ELSE
|
||||
full_chk_i <= AND_REDUCE(full_as_timeout) OR
|
||||
AND_REDUCE(full_ds_timeout);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- Empty checks
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_chk_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
|
||||
empty_chk_i <= '0';
|
||||
ELSE
|
||||
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
|
||||
AND_REDUCE(empty_ds_timeout);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
|
||||
PRC_WR_EN <= prc_we_i AFTER 50 ns;
|
||||
PRC_RD_EN <= prc_re_i AFTER 100 ns;
|
||||
data_chk_i <= dout_chk;
|
||||
END GENERATE fifo_d_chk;
|
||||
-----------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
empty_wr_dom1 <= '1';
|
||||
empty_wr_dom2 <= '1';
|
||||
state_d1 <= '0';
|
||||
wr_en_d1 <= '0';
|
||||
rd_en_wr1 <= '0';
|
||||
rd_en_wr2 <= '0';
|
||||
full_chk_d1 <= '0';
|
||||
reset_en_d1 <= '0';
|
||||
sim_done_wr1 <= '0';
|
||||
sim_done_wr2 <= '0';
|
||||
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
sim_done_wr1 <= sim_done_d1;
|
||||
sim_done_wr2 <= sim_done_wr1;
|
||||
reset_en_d1 <= reset_en_i;
|
||||
state_d1 <= state;
|
||||
empty_wr_dom1 <= empty_d1;
|
||||
empty_wr_dom2 <= empty_wr_dom1;
|
||||
wr_en_d1 <= wr_en_i;
|
||||
rd_en_wr1 <= rd_en_d1;
|
||||
rd_en_wr2 <= rd_en_wr1;
|
||||
full_chk_d1 <= full_chk_i;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_d1 <= '1';
|
||||
state_rd_dom1 <= '0';
|
||||
state_rd_dom2 <= '0';
|
||||
state_rd_dom3 <= '0';
|
||||
wr_en_rd1 <= '0';
|
||||
wr_en_rd2 <= '0';
|
||||
rd_en_d1 <= '0';
|
||||
full_chk_rd1 <= '0';
|
||||
full_chk_rd2 <= '0';
|
||||
reset_en_rd1 <= '0';
|
||||
reset_en_rd2 <= '0';
|
||||
sim_done_d1 <= '0';
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
sim_done_d1 <= sim_done_i;
|
||||
reset_en_rd1 <= reset_en_d1;
|
||||
reset_en_rd2 <= reset_en_rd1;
|
||||
empty_d1 <= EMPTY;
|
||||
rd_en_d1 <= rd_en_i;
|
||||
state_rd_dom1 <= state_d1;
|
||||
state_rd_dom2 <= state_rd_dom1;
|
||||
state_rd_dom3 <= state_rd_dom2;
|
||||
wr_en_rd1 <= wr_en_d1;
|
||||
wr_en_rd2 <= wr_en_rd1;
|
||||
full_chk_rd1 <= full_chk_d1;
|
||||
full_chk_rd2 <= full_chk_rd1;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RESET_EN <= reset_en_rd2;
|
||||
|
||||
|
||||
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
|
||||
-----------------------------------------------------
|
||||
-- WR_EN GENERATION
|
||||
-----------------------------------------------------
|
||||
gen_rand_wr_en:wb_ddr_ctrl_wb_to_ddr_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+1
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => WR_CLK,
|
||||
RESET => RESET_WR,
|
||||
RANDOM_NUM => wr_en_gen,
|
||||
ENABLE => '1'
|
||||
);
|
||||
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
wr_en_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
|
||||
ELSE
|
||||
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- WR_EN CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
wr_cntr <= (OTHERS => '0');
|
||||
wr_control <= '1';
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
IF(wr_en_i = '1') THEN
|
||||
wr_cntr <= wr_cntr + "1";
|
||||
END IF;
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
ELSE
|
||||
wr_cntr <= (OTHERS => '0');
|
||||
IF(rd_en_wr2 = '0') THEN
|
||||
IF(wr_en_i = '1') THEN
|
||||
full_as_timeout <= full_as_timeout + "1";
|
||||
END IF;
|
||||
ELSE
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
wr_control <= NOT wr_cntr(wr_cntr'high);
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- RD_EN GENERATION
|
||||
-----------------------------------------------------
|
||||
gen_rand_rd_en:wb_ddr_ctrl_wb_to_ddr_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => RD_CLK,
|
||||
RESET => RESET_RD,
|
||||
RANDOM_NUM => rd_en_gen,
|
||||
ENABLE => '1'
|
||||
);
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
rd_en_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0') THEN
|
||||
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
|
||||
ELSE
|
||||
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- RD_EN CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
rd_cntr <= (OTHERS => '0');
|
||||
rd_control <= '1';
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0') THEN
|
||||
IF(rd_en_i = '1') THEN
|
||||
rd_cntr <= rd_cntr + "1";
|
||||
END IF;
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
ELSE
|
||||
rd_cntr <= (OTHERS => '0');
|
||||
IF(wr_en_rd2 = '0') THEN
|
||||
IF(rd_en_i = '1') THEN
|
||||
empty_as_timeout <= empty_as_timeout + "1";
|
||||
END IF;
|
||||
ELSE
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
rd_control <= NOT rd_cntr(rd_cntr'high);
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- STIMULUS CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
state <= '0';
|
||||
reset_en_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
CASE state IS
|
||||
WHEN '0' =>
|
||||
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
|
||||
state <= '1';
|
||||
reset_en_i <= '0';
|
||||
END IF;
|
||||
WHEN '1' =>
|
||||
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
|
||||
state <= '0';
|
||||
reset_en_i <= '1';
|
||||
END IF;
|
||||
WHEN OTHERS => state <= state;
|
||||
END CASE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE data_fifo_en;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,348 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench package file for FIFO Generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.std_logic_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE wb_ddr_ctrl_wb_to_ddr_pkg IS
|
||||
|
||||
FUNCTION divroundup (
|
||||
data_value : INTEGER;
|
||||
divisor : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : INTEGER;
|
||||
false_case : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : STD_LOGIC;
|
||||
false_case : STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : TIME;
|
||||
false_case : TIME)
|
||||
RETURN TIME;
|
||||
------------------------
|
||||
FUNCTION log2roundup (
|
||||
data_value : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION hexstr_to_std_logic_vec(
|
||||
arg1 : string;
|
||||
size : integer )
|
||||
RETURN std_logic_vector;
|
||||
------------------------
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_rng IS
|
||||
GENERIC (WIDTH : integer := 8;
|
||||
SEED : integer := 3);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
ENABLE : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_dgen IS
|
||||
GENERIC (
|
||||
C_DIN_WIDTH : INTEGER := 32;
|
||||
C_DOUT_WIDTH : INTEGER := 32;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT (
|
||||
RESET : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
PRC_WR_EN : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
WR_EN : OUT STD_LOGIC;
|
||||
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_dverif IS
|
||||
GENERIC(
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_USE_EMBEDDED_REG : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
PRC_RD_EN : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
RD_EN : OUT STD_LOGIC;
|
||||
DOUT_CHK : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_pctrl IS
|
||||
GENERIC(
|
||||
AXI_CHANNEL : STRING := "NONE";
|
||||
C_APPLICATION_TYPE : INTEGER := 0;
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_WR_PNTR_WIDTH : INTEGER := 0;
|
||||
C_RD_PNTR_WIDTH : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 2;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET_WR : IN STD_LOGIC;
|
||||
RESET_RD : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
ALMOST_FULL : IN STD_LOGIC;
|
||||
ALMOST_EMPTY : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
DOUT_CHK : IN STD_LOGIC;
|
||||
PRC_WR_EN : OUT STD_LOGIC;
|
||||
PRC_RD_EN : OUT STD_LOGIC;
|
||||
RESET_EN : OUT STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_synth IS
|
||||
GENERIC(
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 1
|
||||
);
|
||||
PORT(
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
COMPONENT wb_ddr_ctrl_wb_to_ddr_exdes IS
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(69-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
|
||||
END wb_ddr_ctrl_wb_to_ddr_pkg;
|
||||
|
||||
|
||||
|
||||
PACKAGE BODY wb_ddr_ctrl_wb_to_ddr_pkg IS
|
||||
|
||||
FUNCTION divroundup (
|
||||
data_value : INTEGER;
|
||||
divisor : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE div : INTEGER;
|
||||
BEGIN
|
||||
div := data_value/divisor;
|
||||
IF ( (data_value MOD divisor) /= 0) THEN
|
||||
div := div+1;
|
||||
END IF;
|
||||
RETURN div;
|
||||
END divroundup;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : INTEGER;
|
||||
false_case : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE retval : INTEGER := 0;
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : STD_LOGIC;
|
||||
false_case : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
VARIABLE retval : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : TIME;
|
||||
false_case : TIME)
|
||||
RETURN TIME IS
|
||||
VARIABLE retval : TIME := 0 ps;
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
-------------------------------
|
||||
FUNCTION log2roundup (
|
||||
data_value : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
|
||||
VARIABLE width : INTEGER := 0;
|
||||
VARIABLE cnt : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (data_value <= 1) THEN
|
||||
width := 1;
|
||||
ELSE
|
||||
WHILE (cnt < data_value) LOOP
|
||||
width := width + 1;
|
||||
cnt := cnt *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
|
||||
RETURN width;
|
||||
END log2roundup;
|
||||
------------------------------------------------------------------------------
|
||||
-- hexstr_to_std_logic_vec
|
||||
-- This function converts a hex string to a std_logic_vector
|
||||
------------------------------------------------------------------------------
|
||||
FUNCTION hexstr_to_std_logic_vec(
|
||||
arg1 : string;
|
||||
size : integer )
|
||||
RETURN std_logic_vector IS
|
||||
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
|
||||
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
|
||||
VARIABLE index : integer := 0;
|
||||
BEGIN
|
||||
FOR i IN arg1'reverse_range LOOP
|
||||
CASE arg1(i) IS
|
||||
WHEN '0' => bin := (OTHERS => '0');
|
||||
WHEN '1' => bin := (0 => '1', OTHERS => '0');
|
||||
WHEN '2' => bin := (1 => '1', OTHERS => '0');
|
||||
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
|
||||
WHEN '4' => bin := (2 => '1', OTHERS => '0');
|
||||
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
|
||||
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
|
||||
WHEN '7' => bin := (3 => '0', OTHERS => '1');
|
||||
WHEN '8' => bin := (3 => '1', OTHERS => '0');
|
||||
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
|
||||
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
|
||||
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
|
||||
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
|
||||
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
|
||||
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
|
||||
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
|
||||
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
|
||||
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
|
||||
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
|
||||
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
|
||||
WHEN 'F' => bin := (OTHERS => '1');
|
||||
WHEN 'f' => bin := (OTHERS => '1');
|
||||
WHEN OTHERS =>
|
||||
FOR j IN 0 TO 3 LOOP
|
||||
bin(j) := 'X';
|
||||
END LOOP;
|
||||
END CASE;
|
||||
FOR j IN 0 TO 3 LOOP
|
||||
IF (index*4)+j < size THEN
|
||||
result((index*4)+j) := bin(j);
|
||||
END IF;
|
||||
END LOOP;
|
||||
index := index + 1;
|
||||
END LOOP;
|
||||
RETURN result;
|
||||
END hexstr_to_std_logic_vec;
|
||||
|
||||
END wb_ddr_ctrl_wb_to_ddr_pkg;
|
||||
@@ -0,0 +1,100 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for generation of pseudo random numbers
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_rng IS
|
||||
GENERIC (
|
||||
WIDTH : integer := 8;
|
||||
SEED : integer := 3);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
ENABLE : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE rg_arch OF wb_ddr_ctrl_wb_to_ddr_rng IS
|
||||
BEGIN
|
||||
PROCESS (CLK,RESET)
|
||||
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
|
||||
VARIABLE temp : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rand_temp := conv_std_logic_vector(SEED,width);
|
||||
temp := '0';
|
||||
ELSIF (CLK'event AND CLK = '1') THEN
|
||||
IF (ENABLE = '1') THEN
|
||||
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
|
||||
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
|
||||
rand_temp(0) := temp;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
RANDOM_NUM <= rand_temp;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,296 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench for fifo_generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.STD_LOGIC_1164.ALL;
|
||||
USE ieee.STD_LOGIC_unsigned.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
USE ieee.STD_LOGIC_misc.ALL;
|
||||
|
||||
LIBRARY std;
|
||||
USE std.textio.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.wb_ddr_ctrl_wb_to_ddr_pkg.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_synth IS
|
||||
GENERIC(
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 1
|
||||
);
|
||||
PORT(
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE simulation_arch OF wb_ddr_ctrl_wb_to_ddr_synth IS
|
||||
|
||||
-- FIFO interface signal declarations
|
||||
SIGNAL wr_clk_i : STD_LOGIC;
|
||||
SIGNAL rd_clk_i : STD_LOGIC;
|
||||
SIGNAL rst : STD_LOGIC;
|
||||
SIGNAL wr_en : STD_LOGIC;
|
||||
SIGNAL rd_en : STD_LOGIC;
|
||||
SIGNAL din : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL dout : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL full : STD_LOGIC;
|
||||
SIGNAL empty : STD_LOGIC;
|
||||
-- TB Signals
|
||||
SIGNAL wr_data : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL dout_i : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL wr_en_i : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_i : STD_LOGIC := '0';
|
||||
SIGNAL full_i : STD_LOGIC := '0';
|
||||
SIGNAL empty_i : STD_LOGIC := '0';
|
||||
SIGNAL almost_full_i : STD_LOGIC := '0';
|
||||
SIGNAL almost_empty_i : STD_LOGIC := '0';
|
||||
SIGNAL prc_we_i : STD_LOGIC := '0';
|
||||
SIGNAL prc_re_i : STD_LOGIC := '0';
|
||||
SIGNAL dout_chk_i : STD_LOGIC := '0';
|
||||
SIGNAL rst_int_rd : STD_LOGIC := '0';
|
||||
SIGNAL rst_int_wr : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_rd : STD_LOGIC := '0';
|
||||
SIGNAL reset_en : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
---- Reset generation logic -----
|
||||
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
|
||||
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
|
||||
|
||||
--Testbench reset synchronization
|
||||
PROCESS(rd_clk_i,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rst_async_rd1 <= '1';
|
||||
rst_async_rd2 <= '1';
|
||||
rst_async_rd3 <= '1';
|
||||
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
|
||||
rst_async_rd1 <= RESET;
|
||||
rst_async_rd2 <= rst_async_rd1;
|
||||
rst_async_rd3 <= rst_async_rd2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(wr_clk_i,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rst_async_wr1 <= '1';
|
||||
rst_async_wr2 <= '1';
|
||||
rst_async_wr3 <= '1';
|
||||
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
|
||||
rst_async_wr1 <= RESET;
|
||||
rst_async_wr2 <= rst_async_wr1;
|
||||
rst_async_wr3 <= rst_async_wr2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--Soft reset for core and testbench
|
||||
PROCESS(rd_clk_i)
|
||||
BEGIN
|
||||
IF(rd_clk_i'event AND rd_clk_i='1') THEN
|
||||
rst_gen_rd <= rst_gen_rd + "1";
|
||||
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
|
||||
rst_s_rd <= '1';
|
||||
assert false
|
||||
report "Reset applied..Memory Collision checks are not valid"
|
||||
severity note;
|
||||
ELSE
|
||||
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
|
||||
rst_s_rd <= '0';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(wr_clk_i)
|
||||
BEGIN
|
||||
IF(wr_clk_i'event AND wr_clk_i='1') THEN
|
||||
rst_s_wr1 <= rst_s_rd;
|
||||
rst_s_wr2 <= rst_s_wr1;
|
||||
rst_s_wr3 <= rst_s_wr2;
|
||||
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
|
||||
assert false
|
||||
report "Reset removed..Memory Collision checks are valid"
|
||||
severity note;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
------------------
|
||||
|
||||
---- Clock buffers for testbench ----
|
||||
wr_clk_i <= WR_CLK;
|
||||
rd_clk_i <= RD_CLK;
|
||||
------------------
|
||||
|
||||
rst <= RESET OR rst_s_rd AFTER 12 ns;
|
||||
din <= wr_data;
|
||||
dout_i <= dout;
|
||||
wr_en <= wr_en_i;
|
||||
rd_en <= rd_en_i;
|
||||
full_i <= full;
|
||||
empty_i <= empty;
|
||||
|
||||
fg_dg_nv: wb_ddr_ctrl_wb_to_ddr_dgen
|
||||
GENERIC MAP (
|
||||
C_DIN_WIDTH => 69,
|
||||
C_DOUT_WIDTH => 69,
|
||||
TB_SEED => TB_SEED,
|
||||
C_CH_TYPE => 0
|
||||
)
|
||||
PORT MAP ( -- Write Port
|
||||
RESET => rst_int_wr,
|
||||
WR_CLK => wr_clk_i,
|
||||
PRC_WR_EN => prc_we_i,
|
||||
FULL => full_i,
|
||||
WR_EN => wr_en_i,
|
||||
WR_DATA => wr_data
|
||||
);
|
||||
|
||||
fg_dv_nv: wb_ddr_ctrl_wb_to_ddr_dverif
|
||||
GENERIC MAP (
|
||||
C_DOUT_WIDTH => 69,
|
||||
C_DIN_WIDTH => 69,
|
||||
C_USE_EMBEDDED_REG => 0,
|
||||
TB_SEED => TB_SEED,
|
||||
C_CH_TYPE => 0
|
||||
)
|
||||
PORT MAP(
|
||||
RESET => rst_int_rd,
|
||||
RD_CLK => rd_clk_i,
|
||||
PRC_RD_EN => prc_re_i,
|
||||
RD_EN => rd_en_i,
|
||||
EMPTY => empty_i,
|
||||
DATA_OUT => dout_i,
|
||||
DOUT_CHK => dout_chk_i
|
||||
);
|
||||
|
||||
fg_pc_nv: wb_ddr_ctrl_wb_to_ddr_pctrl
|
||||
GENERIC MAP (
|
||||
AXI_CHANNEL => "Native",
|
||||
C_APPLICATION_TYPE => 0,
|
||||
C_DOUT_WIDTH => 69,
|
||||
C_DIN_WIDTH => 69,
|
||||
C_WR_PNTR_WIDTH => 4,
|
||||
C_RD_PNTR_WIDTH => 4,
|
||||
C_CH_TYPE => 0,
|
||||
FREEZEON_ERROR => FREEZEON_ERROR,
|
||||
TB_SEED => TB_SEED,
|
||||
TB_STOP_CNT => TB_STOP_CNT
|
||||
)
|
||||
PORT MAP(
|
||||
RESET_WR => rst_int_wr,
|
||||
RESET_RD => rst_int_rd,
|
||||
RESET_EN => reset_en,
|
||||
WR_CLK => wr_clk_i,
|
||||
RD_CLK => rd_clk_i,
|
||||
PRC_WR_EN => prc_we_i,
|
||||
PRC_RD_EN => prc_re_i,
|
||||
FULL => full_i,
|
||||
ALMOST_FULL => almost_full_i,
|
||||
ALMOST_EMPTY => almost_empty_i,
|
||||
DOUT_CHK => dout_chk_i,
|
||||
EMPTY => empty_i,
|
||||
DATA_IN => wr_data,
|
||||
DATA_OUT => dout,
|
||||
SIM_DONE => SIM_DONE,
|
||||
STATUS => STATUS
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wb_ddr_ctrl_wb_to_ddr_inst : wb_ddr_ctrl_wb_to_ddr_exdes
|
||||
PORT MAP (
|
||||
WR_CLK => wr_clk_i,
|
||||
RD_CLK => rd_clk_i,
|
||||
RST => rst,
|
||||
WR_EN => wr_en,
|
||||
RD_EN => rd_en,
|
||||
DIN => din,
|
||||
DOUT => dout,
|
||||
FULL => full,
|
||||
EMPTY => empty);
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,208 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench top file for fifo_generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
LIBRARY std;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.ALL;
|
||||
USE IEEE.std_logic_arith.ALL;
|
||||
USE IEEE.std_logic_misc.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
USE ieee.std_logic_textio.ALL;
|
||||
USE std.textio.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.wb_ddr_ctrl_wb_to_ddr_pkg.ALL;
|
||||
|
||||
ENTITY wb_ddr_ctrl_wb_to_ddr_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE wb_ddr_ctrl_wb_to_ddr_arch OF wb_ddr_ctrl_wb_to_ddr_tb IS
|
||||
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
|
||||
SIGNAL wr_clk : STD_LOGIC;
|
||||
SIGNAL rd_clk : STD_LOGIC;
|
||||
SIGNAL reset : STD_LOGIC;
|
||||
SIGNAL sim_done : STD_LOGIC := '0';
|
||||
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
|
||||
-- Write and Read clock periods
|
||||
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
|
||||
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
|
||||
-- Procedures to display strings
|
||||
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
|
||||
variable dp_l : line := null;
|
||||
BEGIN
|
||||
write(dp_l,str);
|
||||
writeline(output,dp_l);
|
||||
END PROCEDURE;
|
||||
|
||||
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
|
||||
variable dp_lx : line := null;
|
||||
BEGIN
|
||||
hwrite(dp_lx,hex);
|
||||
writeline(output,dp_lx);
|
||||
END PROCEDURE;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Generation of clock
|
||||
|
||||
PROCESS BEGIN
|
||||
WAIT FOR 200 ns; -- Wait for global reset
|
||||
WHILE 1 = 1 LOOP
|
||||
wr_clk <= '0';
|
||||
WAIT FOR wr_clk_period_by_2;
|
||||
wr_clk <= '1';
|
||||
WAIT FOR wr_clk_period_by_2;
|
||||
END LOOP;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS BEGIN
|
||||
WAIT FOR 400 ns;-- Wait for global reset
|
||||
WHILE 1 = 1 LOOP
|
||||
rd_clk <= '0';
|
||||
WAIT FOR rd_clk_period_by_2;
|
||||
rd_clk <= '1';
|
||||
WAIT FOR rd_clk_period_by_2;
|
||||
END LOOP;
|
||||
END PROCESS;
|
||||
|
||||
-- Generation of Reset
|
||||
|
||||
PROCESS BEGIN
|
||||
reset <= '1';
|
||||
WAIT FOR 4200 ns;
|
||||
reset <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- Error message printing based on STATUS signal from wb_ddr_ctrl_wb_to_ddr_synth
|
||||
|
||||
PROCESS(status)
|
||||
BEGIN
|
||||
IF(status /= "0" AND status /= "1") THEN
|
||||
disp_str("STATUS:");
|
||||
disp_hex(status);
|
||||
END IF;
|
||||
|
||||
IF(status(7) = '1') THEN
|
||||
assert false
|
||||
report "Data mismatch found"
|
||||
severity error;
|
||||
END IF;
|
||||
|
||||
IF(status(1) = '1') THEN
|
||||
END IF;
|
||||
|
||||
IF(status(5) = '1') THEN
|
||||
assert false
|
||||
report "Empty flag Mismatch/timeout"
|
||||
severity error;
|
||||
END IF;
|
||||
|
||||
IF(status(6) = '1') THEN
|
||||
assert false
|
||||
report "Full Flag Mismatch/timeout"
|
||||
severity error;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait until sim_done = '1';
|
||||
IF(status /= "0" AND status /= "1") THEN
|
||||
assert false
|
||||
report "Simulation failed"
|
||||
severity failure;
|
||||
ELSE
|
||||
assert false
|
||||
report "Test Completed Successfully"
|
||||
severity failure;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait for 400 ms;
|
||||
assert false
|
||||
report "Test bench timed out"
|
||||
severity failure;
|
||||
END PROCESS;
|
||||
|
||||
-- Instance of wb_ddr_ctrl_wb_to_ddr_synth
|
||||
|
||||
wb_ddr_ctrl_wb_to_ddr_synth_inst:wb_ddr_ctrl_wb_to_ddr_synth
|
||||
GENERIC MAP(
|
||||
FREEZEON_ERROR => 0,
|
||||
TB_STOP_CNT => 2,
|
||||
TB_SEED => 87
|
||||
)
|
||||
PORT MAP(
|
||||
WR_CLK => wr_clk,
|
||||
RD_CLK => rd_clk,
|
||||
RESET => reset,
|
||||
SIM_DONE => sim_done,
|
||||
STATUS => status
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -0,0 +1,57 @@
|
||||
# Output products list for <wb_ddr_ctrl_wb_to_ddr>
|
||||
wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt
|
||||
wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html
|
||||
wb_ddr_ctrl_wb_to_ddr/doc/pg057-fifo-generator.pdf
|
||||
wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf
|
||||
wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.xdc
|
||||
wb_ddr_ctrl_wb_to_ddr/fifo_generator_v9_3_readme.txt
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/implement.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/implement.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.tcl
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/xst.prj
|
||||
wb_ddr_ctrl_wb_to_ddr/implement/xst.scr
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.do
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_ncsim.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_vcs.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/ucli_commands.key
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/vcs_session.tcl
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_isim.tcl
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_mti.do
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_ncsim.sv
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.bat
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.do
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_ncsim.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_vcs.sh
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/ucli_commands.key
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/vcs_session.tcl
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_isim.tcl
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_mti.do
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_ncsim.sv
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr.asy
|
||||
wb_ddr_ctrl_wb_to_ddr.gise
|
||||
wb_ddr_ctrl_wb_to_ddr.ngc
|
||||
wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
wb_ddr_ctrl_wb_to_ddr.vho
|
||||
wb_ddr_ctrl_wb_to_ddr.xco
|
||||
wb_ddr_ctrl_wb_to_ddr.xise
|
||||
wb_ddr_ctrl_wb_to_ddr_flist.txt
|
||||
wb_ddr_ctrl_wb_to_ddr_xmdf.tcl
|
||||
@@ -0,0 +1,255 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide wb_ddr_ctrl_wb_to_ddr_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::wb_ddr_ctrl_wb_to_ddr_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::wb_ddr_ctrl_wb_to_ddr_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name wb_ddr_ctrl_wb_to_ddr
|
||||
}
|
||||
# ::wb_ddr_ctrl_wb_to_ddr_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::wb_ddr_ctrl_wb_to_ddr_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/doc/pg057-fifo-generator.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/fifo_generator_v9_3_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/implement.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/xst.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/implement/xst.scr
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_isim.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_ncsim.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_isim.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_ncsim.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dgen.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dverif.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pctrl.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pkg.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_rng.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_synth.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_tb.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_ctrl_wb_to_ddr_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module wb_ddr_ctrl_wb_to_ddr
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -0,0 +1,30 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="sim" num="172" delta="new" >Generating IP...
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'wb_ddr_ctrl_wb_from_ddr' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'wb_ddr_ctrl_wb_from_ddr'...</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option '-ifmt' found multiple times. Only the first occurence is considered.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html with file from view xilinx_documentation</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="949" delta="new" >Finished generation of ASY schematic symbol.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="948" delta="new" >Finished FLIST file generation.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@@ -0,0 +1,943 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>projects</spirit:library>
|
||||
<spirit:name>coregen</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>wb_ddr_ctrl_wb_from_ddr</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3" />
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">wb_ddr_ctrl_wb_from_ddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">spartan3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue>
|
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<xilinx:userFileType>vhdl</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:51:56 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x8B6EE6CF</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_tb.vhd</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>vhdl</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:51:56 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x86CAA91F</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>ngc_netlist_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.ngc</xilinx:name>
|
||||
<xilinx:userFileType>ngc</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:58 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xDA454DAB</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>obfuscate_netlist_generator</xilinx:name>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>padded_implementation_netlist_generator</xilinx:name>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>instantiation_template_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.vho</xilinx:name>
|
||||
<xilinx:userFileType>vho</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:59 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xA5CD245E</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>structural_simulation_model_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.vhd</xilinx:name>
|
||||
<xilinx:userFileType>vhdl</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:59 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x04E2C272</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>all_documents_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_readme.txt</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>txt</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:59 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xD700FB89</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>unknown</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:59 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x5A766369</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr/doc/pg057-fifo-generator.pdf</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>pdf</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:53:59 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x90F23916</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>readme_documents_generator</xilinx:name>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>asy_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.asy</xilinx:name>
|
||||
<xilinx:userFileType>asy</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:04 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xF0F5946D</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>xmdf_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr_xmdf.tcl</xilinx:name>
|
||||
<xilinx:userFileType>tclXmdf</xilinx:userFileType>
|
||||
<xilinx:userFileType>tcl</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:04 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xC757466F</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>synthesis_ise_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.gise</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>gise</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:10 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x10DE92DE</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.xise</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>xise</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:10 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x241C094F</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>ise_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.gise</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>gise</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:16 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x84F72A77</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr.xise</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>xise</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:16 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0xD47A8864</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>deliver_readme_generator</xilinx:name>
|
||||
</xilinx:fileSet>
|
||||
<xilinx:fileSet>
|
||||
<xilinx:name>flist_generator</xilinx:name>
|
||||
<xilinx:file>
|
||||
<xilinx:name>./wb_ddr_ctrl_wb_from_ddr_flist.txt</xilinx:name>
|
||||
<xilinx:userFileType>ignore</xilinx:userFileType>
|
||||
<xilinx:userFileType>txtFlist</xilinx:userFileType>
|
||||
<xilinx:userFileType>txt</xilinx:userFileType>
|
||||
<xilinx:timeStamp>Tue Nov 06 15:54:17 GMT 2012</xilinx:timeStamp>
|
||||
<xilinx:checkSum>0x21E1AF65</xilinx:checkSum>
|
||||
<xilinx:generationId>generationID_1879581046</xilinx:generationId>
|
||||
</xilinx:file>
|
||||
</xilinx:fileSet>
|
||||
</xilinx:generationHistory>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:instanceProperties>
|
||||
<xilinx:projectOptions>
|
||||
<xilinx:projectName>coregen</xilinx:projectName>
|
||||
<xilinx:outputDirectory>./</xilinx:outputDirectory>
|
||||
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
|
||||
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
|
||||
</xilinx:projectOptions>
|
||||
<xilinx:part>
|
||||
<xilinx:device>xc3s700an</xilinx:device>
|
||||
<xilinx:deviceFamily>spartan3a</xilinx:deviceFamily>
|
||||
<xilinx:package>fgg484</xilinx:package>
|
||||
<xilinx:speedGrade>-4</xilinx:speedGrade>
|
||||
</xilinx:part>
|
||||
<xilinx:flowOptions>
|
||||
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
|
||||
<xilinx:designEntry>VHDL</xilinx:designEntry>
|
||||
<xilinx:asySymbol>true</xilinx:asySymbol>
|
||||
<xilinx:flowVendor>Other</xilinx:flowVendor>
|
||||
<xilinx:addPads>false</xilinx:addPads>
|
||||
<xilinx:removeRPMs>false</xilinx:removeRPMs>
|
||||
<xilinx:createNDF>false</xilinx:createNDF>
|
||||
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
|
||||
<xilinx:formalVerification>false</xilinx:formalVerification>
|
||||
</xilinx:flowOptions>
|
||||
<xilinx:simulationOptions>
|
||||
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
|
||||
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
|
||||
<xilinx:foundationSym>false</xilinx:foundationSym>
|
||||
</xilinx:simulationOptions>
|
||||
</xilinx:instanceProperties>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:design>
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
# Date: Tue Nov 6 15:54:17 2012
|
||||
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
SET workingdirectory = ./tmp/
|
||||
|
||||
# CRC: e0289cf1
|
||||
@@ -0,0 +1,73 @@
|
||||
INFO:sim:172 - Generating IP...
|
||||
Applying current project options...
|
||||
Finished applying current project options.
|
||||
Resolving generics for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
WARNING:sim - A core named 'wb_ddr_ctrl_wb_from_ddr' already exists in the
|
||||
project. Output products for this core may be overwritten.
|
||||
Applying external generics to 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
Delivering associated files for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
Delivering EJava files for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
Generating implementation netlist for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
INFO:sim - Pre-processing HDL files for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
WARNING:sim - BlackBox generator run option '-ifmt' found multiple times. Only
|
||||
the first occurence is considered.
|
||||
Running synthesis for 'wb_ddr_ctrl_wb_from_ddr'
|
||||
Running ngcbuild...
|
||||
Writing VHO instantiation template for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
Writing VHDL behavioral simulation model for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
WARNING:sim - Overwriting existing file
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fi
|
||||
fo_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_v
|
||||
info.html with file from view xilinx_documentation
|
||||
Delivered 3 files into directory
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr
|
||||
Delivered 1 file into directory
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr
|
||||
Generating ASY schematic symbol...
|
||||
INFO:sim:949 - Finished generation of ASY schematic symbol.
|
||||
Generating metadata file...
|
||||
Generating ISE project file for 'wb_ddr_ctrl_wb_from_ddr'...
|
||||
Generating ISE project...
|
||||
XCO file found: wb_ddr_ctrl_wb_from_ddr.xco
|
||||
XMDF file found: wb_ddr_ctrl_wb_from_ddr_xmdf.tcl
|
||||
Adding
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.asy -view all -origin_type
|
||||
imported
|
||||
Adding
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.ngc -view all -origin_type
|
||||
created
|
||||
Checking file
|
||||
"/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo
|
||||
_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.ngc" for project device match
|
||||
...
|
||||
File
|
||||
"/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo
|
||||
_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.ngc" device information
|
||||
matches project device.
|
||||
Adding
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.vhd -view all -origin_type
|
||||
created
|
||||
INFO:HDLCompiler:1061 - Parsing VHDL file
|
||||
"/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/f
|
||||
ifo_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.vhd" into library work
|
||||
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
|
||||
Adding
|
||||
/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_
|
||||
generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.vho -view all -origin_type
|
||||
imported
|
||||
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
|
||||
Please set the new top explicitly by running the "project set top" command.
|
||||
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
||||
property to true.
|
||||
Top level has been set to "/wb_ddr_ctrl_wb_from_ddr"
|
||||
Generating README file...
|
||||
Generating FLIST file...
|
||||
INFO:sim:948 - Finished FLIST file generation.
|
||||
Moving files to output directory...
|
||||
Finished moving files to output directory
|
||||
Wrote CGP file for project 'coregen'.
|
||||
@@ -0,0 +1,108 @@
|
||||
<?xml version="1.0"?>
|
||||
<BillOfMaterials Version="1" Minor="2">
|
||||
<IPInstance name="wb_ddr_ctrl_wb_from_ddr">
|
||||
<FileSets>
|
||||
<FileSet generator="apply_current_project_options_generator">
|
||||
<File name="./apply_current_project_options_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="model_parameter_resolution_generator">
|
||||
<File name="./model_parameter_resolution_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ip_xco_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.xco" type="xco" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x83A370AD"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="associated_files_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html" type="ignore" timestamp="Sat Oct 13 03:01:40 GMT 2012" checksum="0x5A766369"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/fifo_generator_v9_3_readme.txt" type="ignore" timestamp="Sat Oct 13 03:01:40 GMT 2012" checksum="0xD700FB89"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ejava_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.ucf" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0xB547BB7D"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x35ED98B7"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.xdc" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x77D89547"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/implement.bat" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x192E0FAA"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/implement.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x20337A12"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xD919F981"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x43EA05DA"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xB958E3B7"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xD7D40E1B"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.tcl" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xA0C1ABF4"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/xst.prj" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x8573CCD5"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/implement/xst.scr" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x236660A1"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xC83FD6FF"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xFD3DE2A7"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x0C3CDB0C"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.do" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x444A03C1"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x5FDBD750"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_ncsim.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xD08A592E"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_vcs.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x104A8D56"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/ucli_commands.key" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xF1BDBC27"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/vcs_session.tcl" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xC635497A"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_isim.tcl" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x7F420673"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_mti.do" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xCA6B8089"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_ncsim.sv" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x9EEEF980"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_isim.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x52E8AF77"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_isim.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xBEF17236"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.bat" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x0C3CDB0C"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.do" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x38ACA586"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x5FDBD750"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_ncsim.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x6DB6900E"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_vcs.sh" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x9611AE74"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/ucli_commands.key" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xF1BDBC27"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/vcs_session.tcl" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x33F51969"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_isim.tcl" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x7F420673"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_mti.do" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0xCA6B8089"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_ncsim.sv" type="ignore" timestamp="Tue Nov 06 15:51:57 GMT 2012" checksum="0x9EEEF980"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dgen.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0xECF0BC76"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dverif.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x4C32772D"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pctrl.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x889DB751"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pkg.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x9EDC13A9"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_rng.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x299D093D"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_synth.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x8B6EE6CF"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_tb.vhd" type="ignore" timestamp="Tue Nov 06 15:51:56 GMT 2012" checksum="0x86CAA91F"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ngc_netlist_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.ngc" type="ngc" timestamp="Tue Nov 06 15:53:58 GMT 2012" checksum="0xDA454DAB"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="obfuscate_netlist_generator">
|
||||
<File name="./obfuscate_netlist_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="padded_implementation_netlist_generator">
|
||||
<File name="./padded_implementation_netlist_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="instantiation_template_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.vho" type="vho" timestamp="Tue Nov 06 15:53:59 GMT 2012" checksum="0xA5CD245E"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="structural_simulation_model_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.vhd" type="vhdl" timestamp="Tue Nov 06 15:53:59 GMT 2012" checksum="0x04E2C272"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="all_documents_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_readme.txt" type="ignore" timestamp="Tue Nov 06 15:53:59 GMT 2012" checksum="0xD700FB89"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html" type="ignore" timestamp="Tue Nov 06 15:53:59 GMT 2012" checksum="0x5A766369"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr/doc/pg057-fifo-generator.pdf" type="ignore" timestamp="Tue Nov 06 15:53:59 GMT 2012" checksum="0x90F23916"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="readme_documents_generator">
|
||||
<File name="./readme_documents_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="asy_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.asy" type="asy" timestamp="Tue Nov 06 15:54:04 GMT 2012" checksum="0xF0F5946D"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="xmdf_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr_xmdf.tcl" type="tclXmdf" timestamp="Tue Nov 06 15:54:04 GMT 2012" checksum="0xC757466F"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="synthesis_ise_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.gise" type="ignore" timestamp="Tue Nov 06 15:54:10 GMT 2012" checksum="0x10DE92DE"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.xise" type="ignore" timestamp="Tue Nov 06 15:54:10 GMT 2012" checksum="0x241C094F"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="ise_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.gise" type="ignore" timestamp="Tue Nov 06 15:54:16 GMT 2012" checksum="0x84F72A77"></File>
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr.xise" type="ignore" timestamp="Tue Nov 06 15:54:16 GMT 2012" checksum="0xD47A8864"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="deliver_readme_generator">
|
||||
<File name="./deliver_readme_generator.xlog" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0xFFFFFFFF"></File>
|
||||
</FileSet>
|
||||
<FileSet generator="flist_generator">
|
||||
<File name="./wb_ddr_ctrl_wb_from_ddr_flist.txt" type="ignore" timestamp="Tue Nov 06 15:54:17 GMT 2012" checksum="0x21E1AF65"></File>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
</IPInstance>
|
||||
</BillOfMaterials>
|
||||
@@ -0,0 +1,29 @@
|
||||
# Tcl script generated by PlanAhead
|
||||
|
||||
set reloadAllCoreGenRepositories false
|
||||
|
||||
set tclUtilsPath "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
|
||||
|
||||
set repoPaths ""
|
||||
|
||||
set cgProjectPath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_1/coregen.cgc"
|
||||
|
||||
set ipFile "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_1/wb_ddr_ctrl_wb_from_ddr.xco"
|
||||
|
||||
set ipName "wb_ddr_ctrl_wb_from_ddr"
|
||||
|
||||
set hdlType "VHDL"
|
||||
|
||||
set cgPartSpec "xc3s700an-4fgg484"
|
||||
|
||||
set chains "GENERATE_CURRENT_CHAIN"
|
||||
|
||||
set params ""
|
||||
|
||||
set bomFilePath "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_1/pa_cg_bom.xml"
|
||||
|
||||
# generate the IP
|
||||
set result [source "/opt/Xilinx/14.3/ISE_DS/PlanAhead/scripts/pa_cg_gen_out_prods.tcl"]
|
||||
|
||||
exit $result
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated -->
|
||||
<!-- by the Xilinx ISE software. Any direct editing or -->
|
||||
<!-- changes made to this file may result in unpredictable -->
|
||||
<!-- behavior or data corruption. It is strongly advised that -->
|
||||
<!-- users do not edit the contents of this file. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/matthias/devel/2d_display_engine/2d_display_engine.srcs/sources_1/ip/fifo_generator_v9_3_1/tmp/_cg/wb_ddr_ctrl_wb_from_ddr.vhd" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 wb_ddr_ctrl_wb_from_ddr
|
||||
RECTANGLE Normal 32 32 800 4064
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName rst
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 208 32 208
|
||||
PIN 0 208 LEFT 36
|
||||
PINATTR PinName wr_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din[32:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName wr_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 464 32 464
|
||||
PIN 0 464 LEFT 36
|
||||
PINATTR PinName full
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 240 800 240
|
||||
PIN 832 240 RIGHT 36
|
||||
PINATTR PinName rd_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 832 272 800 272
|
||||
PIN 832 272 RIGHT 36
|
||||
PINATTR PinName dout[32:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 304 800 304
|
||||
PIN 832 304 RIGHT 36
|
||||
PINATTR PinName rd_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 832 496 800 496
|
||||
PIN 832 496 RIGHT 36
|
||||
PINATTR PinName empty
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="wb_ddr_ctrl_wb_from_ddr.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="wb_ddr_ctrl_wb_from_ddr.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="wb_ddr_ctrl_wb_from_ddr.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,283 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file wb_ddr_ctrl_wb_from_ddr.vhd when simulating
|
||||
-- the core, wb_ddr_ctrl_wb_from_ddr. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY wb_ddr_ctrl_wb_from_ddr IS
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END wb_ddr_ctrl_wb_from_ddr;
|
||||
|
||||
ARCHITECTURE wb_ddr_ctrl_wb_from_ddr_a OF wb_ddr_ctrl_wb_from_ddr IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_wb_ddr_ctrl_wb_from_ddr
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_wb_ddr_ctrl_wb_from_ddr USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_add_ngc_constraint => 0,
|
||||
c_application_type_axis => 0,
|
||||
c_application_type_rach => 0,
|
||||
c_application_type_rdch => 0,
|
||||
c_application_type_wach => 0,
|
||||
c_application_type_wdch => 0,
|
||||
c_application_type_wrch => 0,
|
||||
c_axi_addr_width => 32,
|
||||
c_axi_aruser_width => 1,
|
||||
c_axi_awuser_width => 1,
|
||||
c_axi_buser_width => 1,
|
||||
c_axi_data_width => 64,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_ruser_width => 1,
|
||||
c_axi_type => 0,
|
||||
c_axi_wuser_width => 1,
|
||||
c_axis_tdata_width => 64,
|
||||
c_axis_tdest_width => 4,
|
||||
c_axis_tid_width => 8,
|
||||
c_axis_tkeep_width => 4,
|
||||
c_axis_tstrb_width => 4,
|
||||
c_axis_tuser_width => 4,
|
||||
c_axis_type => 0,
|
||||
c_common_clock => 0,
|
||||
c_count_type => 0,
|
||||
c_data_count_width => 4,
|
||||
c_default_value => "BlankString",
|
||||
c_din_width => 33,
|
||||
c_din_width_axis => 1,
|
||||
c_din_width_rach => 32,
|
||||
c_din_width_rdch => 64,
|
||||
c_din_width_wach => 32,
|
||||
c_din_width_wdch => 64,
|
||||
c_din_width_wrch => 2,
|
||||
c_dout_rst_val => "0",
|
||||
c_dout_width => 33,
|
||||
c_enable_rlocs => 0,
|
||||
c_enable_rst_sync => 1,
|
||||
c_error_injection_type => 0,
|
||||
c_error_injection_type_axis => 0,
|
||||
c_error_injection_type_rach => 0,
|
||||
c_error_injection_type_rdch => 0,
|
||||
c_error_injection_type_wach => 0,
|
||||
c_error_injection_type_wdch => 0,
|
||||
c_error_injection_type_wrch => 0,
|
||||
c_family => "spartan3",
|
||||
c_full_flags_rst_val => 1,
|
||||
c_has_almost_empty => 0,
|
||||
c_has_almost_full => 0,
|
||||
c_has_axi_aruser => 0,
|
||||
c_has_axi_awuser => 0,
|
||||
c_has_axi_buser => 0,
|
||||
c_has_axi_rd_channel => 0,
|
||||
c_has_axi_ruser => 0,
|
||||
c_has_axi_wr_channel => 0,
|
||||
c_has_axi_wuser => 0,
|
||||
c_has_axis_tdata => 0,
|
||||
c_has_axis_tdest => 0,
|
||||
c_has_axis_tid => 0,
|
||||
c_has_axis_tkeep => 0,
|
||||
c_has_axis_tlast => 0,
|
||||
c_has_axis_tready => 1,
|
||||
c_has_axis_tstrb => 0,
|
||||
c_has_axis_tuser => 0,
|
||||
c_has_backup => 0,
|
||||
c_has_data_count => 0,
|
||||
c_has_data_counts_axis => 0,
|
||||
c_has_data_counts_rach => 0,
|
||||
c_has_data_counts_rdch => 0,
|
||||
c_has_data_counts_wach => 0,
|
||||
c_has_data_counts_wdch => 0,
|
||||
c_has_data_counts_wrch => 0,
|
||||
c_has_int_clk => 0,
|
||||
c_has_master_ce => 0,
|
||||
c_has_meminit_file => 0,
|
||||
c_has_overflow => 0,
|
||||
c_has_prog_flags_axis => 0,
|
||||
c_has_prog_flags_rach => 0,
|
||||
c_has_prog_flags_rdch => 0,
|
||||
c_has_prog_flags_wach => 0,
|
||||
c_has_prog_flags_wdch => 0,
|
||||
c_has_prog_flags_wrch => 0,
|
||||
c_has_rd_data_count => 0,
|
||||
c_has_rd_rst => 0,
|
||||
c_has_rst => 1,
|
||||
c_has_slave_ce => 0,
|
||||
c_has_srst => 0,
|
||||
c_has_underflow => 0,
|
||||
c_has_valid => 0,
|
||||
c_has_wr_ack => 0,
|
||||
c_has_wr_data_count => 0,
|
||||
c_has_wr_rst => 0,
|
||||
c_implementation_type => 2,
|
||||
c_implementation_type_axis => 1,
|
||||
c_implementation_type_rach => 1,
|
||||
c_implementation_type_rdch => 1,
|
||||
c_implementation_type_wach => 1,
|
||||
c_implementation_type_wdch => 1,
|
||||
c_implementation_type_wrch => 1,
|
||||
c_init_wr_pntr_val => 0,
|
||||
c_interface_type => 0,
|
||||
c_memory_type => 2,
|
||||
c_mif_file_name => "BlankString",
|
||||
c_msgon_val => 0,
|
||||
c_optimization_mode => 0,
|
||||
c_overflow_low => 0,
|
||||
c_preload_latency => 1,
|
||||
c_preload_regs => 0,
|
||||
c_prim_fifo_type => "512x36",
|
||||
c_prog_empty_thresh_assert_val => 2,
|
||||
c_prog_empty_thresh_assert_val_axis => 1022,
|
||||
c_prog_empty_thresh_assert_val_rach => 1022,
|
||||
c_prog_empty_thresh_assert_val_rdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wach => 1022,
|
||||
c_prog_empty_thresh_assert_val_wdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wrch => 1022,
|
||||
c_prog_empty_thresh_negate_val => 3,
|
||||
c_prog_empty_type => 0,
|
||||
c_prog_empty_type_axis => 0,
|
||||
c_prog_empty_type_rach => 0,
|
||||
c_prog_empty_type_rdch => 0,
|
||||
c_prog_empty_type_wach => 0,
|
||||
c_prog_empty_type_wdch => 0,
|
||||
c_prog_empty_type_wrch => 0,
|
||||
c_prog_full_thresh_assert_val => 13,
|
||||
c_prog_full_thresh_assert_val_axis => 1023,
|
||||
c_prog_full_thresh_assert_val_rach => 1023,
|
||||
c_prog_full_thresh_assert_val_rdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wach => 1023,
|
||||
c_prog_full_thresh_assert_val_wdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wrch => 1023,
|
||||
c_prog_full_thresh_negate_val => 12,
|
||||
c_prog_full_type => 0,
|
||||
c_prog_full_type_axis => 0,
|
||||
c_prog_full_type_rach => 0,
|
||||
c_prog_full_type_rdch => 0,
|
||||
c_prog_full_type_wach => 0,
|
||||
c_prog_full_type_wdch => 0,
|
||||
c_prog_full_type_wrch => 0,
|
||||
c_rach_type => 0,
|
||||
c_rd_data_count_width => 4,
|
||||
c_rd_depth => 16,
|
||||
c_rd_freq => 1,
|
||||
c_rd_pntr_width => 4,
|
||||
c_rdch_type => 0,
|
||||
c_reg_slice_mode_axis => 0,
|
||||
c_reg_slice_mode_rach => 0,
|
||||
c_reg_slice_mode_rdch => 0,
|
||||
c_reg_slice_mode_wach => 0,
|
||||
c_reg_slice_mode_wdch => 0,
|
||||
c_reg_slice_mode_wrch => 0,
|
||||
c_synchronizer_stage => 2,
|
||||
c_underflow_low => 0,
|
||||
c_use_common_overflow => 0,
|
||||
c_use_common_underflow => 0,
|
||||
c_use_default_settings => 0,
|
||||
c_use_dout_rst => 1,
|
||||
c_use_ecc => 0,
|
||||
c_use_ecc_axis => 0,
|
||||
c_use_ecc_rach => 0,
|
||||
c_use_ecc_rdch => 0,
|
||||
c_use_ecc_wach => 0,
|
||||
c_use_ecc_wdch => 0,
|
||||
c_use_ecc_wrch => 0,
|
||||
c_use_embedded_reg => 0,
|
||||
c_use_fifo16_flags => 0,
|
||||
c_use_fwft_data_count => 0,
|
||||
c_valid_low => 0,
|
||||
c_wach_type => 0,
|
||||
c_wdch_type => 0,
|
||||
c_wr_ack_low => 0,
|
||||
c_wr_data_count_width => 4,
|
||||
c_wr_depth => 16,
|
||||
c_wr_depth_axis => 1024,
|
||||
c_wr_depth_rach => 16,
|
||||
c_wr_depth_rdch => 1024,
|
||||
c_wr_depth_wach => 16,
|
||||
c_wr_depth_wdch => 1024,
|
||||
c_wr_depth_wrch => 16,
|
||||
c_wr_freq => 1,
|
||||
c_wr_pntr_width => 4,
|
||||
c_wr_pntr_width_axis => 10,
|
||||
c_wr_pntr_width_rach => 4,
|
||||
c_wr_pntr_width_rdch => 10,
|
||||
c_wr_pntr_width_wach => 4,
|
||||
c_wr_pntr_width_wdch => 10,
|
||||
c_wr_pntr_width_wrch => 4,
|
||||
c_wr_response_latency => 1,
|
||||
c_wrch_type => 0
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_wb_ddr_ctrl_wb_from_ddr
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END wb_ddr_ctrl_wb_from_ddr_a;
|
||||
@@ -0,0 +1,95 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --
|
||||
-- --
|
||||
-- The FIFO Generator is a parameterizable first-in/first-out memory --
|
||||
-- queue generator. Use it to generate resource and performance --
|
||||
-- optimized FIFOs with common or independent read/write clock domains, --
|
||||
-- and optional fixed or programmable full and empty flags and --
|
||||
-- handshaking signals. Choose from a selection of memory resource --
|
||||
-- types for implementation. Optional Hamming code based error --
|
||||
-- detection and correction as well as error injection capability for --
|
||||
-- system test help to insure data integrity. FIFO width and depth are --
|
||||
-- parameterizable, and for native interface FIFOs, asymmetric read and --
|
||||
-- write port widths are also supported. --
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
-- Interfaces:
|
||||
-- AXI4Stream_MASTER_M_AXIS
|
||||
-- AXI4Stream_SLAVE_S_AXIS
|
||||
-- AXI4_MASTER_M_AXI
|
||||
-- AXI4_SLAVE_S_AXI
|
||||
-- AXI4Lite_MASTER_M_AXI
|
||||
-- AXI4Lite_SLAVE_S_AXI
|
||||
-- master_aclk
|
||||
-- slave_aclk
|
||||
-- slave_aresetn
|
||||
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT wb_ddr_ctrl_wb_from_ddr
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : wb_ddr_ctrl_wb_from_ddr
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file wb_ddr_ctrl_wb_from_ddr.vhd when simulating
|
||||
-- the core, wb_ddr_ctrl_wb_from_ddr. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -0,0 +1,696 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>wb_ddr_ctrl_wb_from_ddr</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.backup">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.backup_marker">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rst">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.srst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_rst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_rst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.din">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.din">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh_assert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh_assert">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty_thresh_negate">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_empty_thresh_negate">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh_assert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh_assert">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full_thresh_negate">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.prog_full_thresh_negate">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.int_clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dout">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.dout">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.full">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.almost_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_ack">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.empty">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.almost_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.valid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.rd_data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.wr_data_count">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aresetn">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_aclk_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_aclk_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awaddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awaddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_awuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_awready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wstrb">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_wuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_wready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_bid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_buser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_buser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_bready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awaddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awaddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_awuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_awready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wstrb">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_wuser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_wready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_bid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_buser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_buser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_bready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_arid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_araddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_araddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_aruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_aruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_arready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_rid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_rdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_ruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axi_ruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axi_rready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_arid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_araddr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_araddr">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arlen">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arsize">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arburst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arlock">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arcache">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arprot">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arqos">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arregion">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_aruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_aruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_arready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_rid">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_rdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rresp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_ruser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axi_ruser">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axi_rready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tstrb">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tkeep">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tkeep">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tid">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tdest">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tdest">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.s_axis_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.s_axis_tuser">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tvalid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tdata">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tdata">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tstrb">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tstrb">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tkeep">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tkeep">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tid">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tid">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tdest">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tdest">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.m_axis_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.m_axis_tuser">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_aw_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_aw_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_w_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_w_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_b_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_b_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_prog_full_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_prog_empty_thresh">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_wr_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_ar_rd_data_count">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_ar_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axi_r_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_injectsbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axi_r_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_injectdbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_full_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_prog_full_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_empty_thresh">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_prog_empty_thresh">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_wr_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_wr_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_rd_data_count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_VECTOR_LEFT.axis_rd_data_count">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_sbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_dbiterr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_full">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.axis_prog_empty">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">wb_ddr_ctrl_wb_from_ddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Stream_SLAVE_S_AXIS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4_MASTER_M_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4_SLAVE_S_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Lite_MASTER_M_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.AXI4Lite_SLAVE_S_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.master_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.slave_aclk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIF_ENABLEMENT.slave_aresetn">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">spartan3a</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc3s700an</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">FALSE</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,213 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.3
|
||||
# Date: Tue Nov 6 15:51:56 2012
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Common_Clock
|
||||
CSET component_name=wb_ddr_ctrl_wb_from_ddr
|
||||
CSET data_count=false
|
||||
CSET data_count_width=4
|
||||
CSET disable_timing_violations=true
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_assert_value_axis=1022
|
||||
CSET empty_threshold_assert_value_rach=1022
|
||||
CSET empty_threshold_assert_value_rdch=1022
|
||||
CSET empty_threshold_assert_value_wach=1022
|
||||
CSET empty_threshold_assert_value_wdch=1022
|
||||
CSET empty_threshold_assert_value_wrch=1022
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=false
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=false
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=false
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=false
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
|
||||
CSET fifo_implementation_axis=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=13
|
||||
CSET full_threshold_assert_value_axis=1023
|
||||
CSET full_threshold_assert_value_rach=1023
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=1023
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=1023
|
||||
CSET full_threshold_negate_value=12
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=33
|
||||
CSET input_depth=16
|
||||
CSET input_depth_axis=1024
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=Native
|
||||
CSET output_data_width=33
|
||||
CSET output_depth=16
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=4
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=4
|
||||
CSET tstrb_width=4
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=4
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-07-25T18:11:59Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: bab20e74
|
||||
@@ -0,0 +1,398 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="wb_ddr_ctrl_wb_from_ddr.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="wb_ddr_ctrl_wb_from_ddr.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wb_ddr_ctrl_wb_from_ddr|wb_ddr_ctrl_wb_from_ddr_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="wb_ddr_ctrl_wb_from_ddr.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wb_ddr_ctrl_wb_from_ddr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="wb_ddr_ctrl_wb_from_ddr" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_from_ddr_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_from_ddr_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_from_ddr_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wb_ddr_ctrl_wb_from_ddr_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="wb_ddr_ctrl_wb_from_ddr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-06T16:54:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="114766F5512DE75F748976BF9DE6E38F" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,237 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,248 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>fifo_generator_v9_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,56 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "RD_CLK" TNM_NET = "RD_CLK";
|
||||
NET "WR_CLK" TNM_NET = "WR_CLK";
|
||||
TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ;
|
||||
TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ;
|
||||
################################################################################
|
||||
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core - core top file for implementation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: wb_ddr_ctrl_wb_from_ddr_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the FIFO core wrapper with BUFG instances for clock connections.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
entity wb_ddr_ctrl_wb_from_ddr_exdes is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(33-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(33-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end wb_ddr_ctrl_wb_from_ddr_exdes;
|
||||
|
||||
|
||||
|
||||
architecture xilinx of wb_ddr_ctrl_wb_from_ddr_exdes is
|
||||
|
||||
signal wr_clk_i : std_logic;
|
||||
signal rd_clk_i : std_logic;
|
||||
|
||||
|
||||
|
||||
component wb_ddr_ctrl_wb_from_ddr is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(33-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(33-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wr_clk_buf: bufg
|
||||
PORT map(
|
||||
i => WR_CLK,
|
||||
o => wr_clk_i
|
||||
);
|
||||
|
||||
rd_clk_buf: bufg
|
||||
PORT map(
|
||||
i => RD_CLK,
|
||||
o => rd_clk_i
|
||||
);
|
||||
|
||||
|
||||
exdes_inst : wb_ddr_ctrl_wb_from_ddr
|
||||
PORT MAP (
|
||||
WR_CLK => wr_clk_i,
|
||||
RD_CLK => rd_clk_i,
|
||||
RST => rst,
|
||||
WR_EN => wr_en,
|
||||
RD_EN => rd_en,
|
||||
DIN => din,
|
||||
DOUT => dout,
|
||||
FULL => full,
|
||||
EMPTY => empty);
|
||||
|
||||
end xilinx;
|
||||
@@ -0,0 +1,68 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_RD_CLK" -period 1000.0 [ get_ports RD_CLK ]
|
||||
create_clock -name "TS_WR_CLK" -period 1000.0 [ get_ports WR_CLK ]
|
||||
|
||||
# Following are the constrains for Fifo Generator to eleminate setup/hold violation warnings in simulations
|
||||
# This example is using the Set False Path constrains we can also make use of the Max Delay constrains,
|
||||
# to use them just un-comment them and comment the False Path constrains
|
||||
|
||||
##set wr_q_nets [get_nets -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_q?0?* }]
|
||||
set wr_q_cell [get_cells -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_? }]
|
||||
|
||||
##set rd_q_nets [get_nets -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q?0?* }]
|
||||
set rd_q_cell [get_cells -hier -filter { NAME =~ */xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_? }]
|
||||
|
||||
set_false_path -from $rd_q_cell -through $rd_q_cell -to $rd_q_cell
|
||||
set_false_path -from $wr_q_cell -through $wr_q_cell -to $wr_q_cell
|
||||
|
||||
##set_max_delay -through $wr_q_nets -datapath_only 2000.0##set_max_delay -through $rd_q_nets -datapath_only 2000.0################################################################################
|
||||
@@ -0,0 +1,237 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3
|
||||
|
||||
Release Date: October 16, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.3 software support
|
||||
- Clock Enable support for AXI4 Stream FIFO
|
||||
- IP level constraint for cross clock domain logic
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,88 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy wb_ddr_ctrl_wb_from_ddr_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\wb_ddr_ctrl_wb_from_ddr.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\wb_ddr_ctrl_wb_from_ddr_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_from_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_from_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_from_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
@@ -0,0 +1,87 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
cp wb_ddr_ctrl_wb_from_ddr_exdes.ngc ./results/
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../wb_ddr_ctrl_wb_from_ddr.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/wb_ddr_ctrl_wb_from_ddr_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_from_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_from_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_from_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\wb_ddr_ctrl_wb_from_ddr.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\wb_ddr_ctrl_wb_from_ddr_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_from_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_from_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_from_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
@@ -0,0 +1,86 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../wb_ddr_ctrl_wb_from_ddr.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/wb_ddr_ctrl_wb_from_ddr_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc3s1400a-fg676-4 -sd ../../../ wb_ddr_ctrl_wb_from_ddr_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map wb_ddr_ctrl_wb_from_ddr_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level VHDL model'
|
||||
netgen -ofmt vhdl -sim -tm wb_ddr_ctrl_wb_from_ddr_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem -----------------------------------------------------------------------------
|
||||
rem Script to synthesize and implement the Coregen FIFO Generator
|
||||
rem -----------------------------------------------------------------------------
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
cd results
|
||||
copy ..\..\..\wb_ddr_ctrl_wb_from_ddr.ngc .
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -0,0 +1,55 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the Coregen FIFO Generator
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
cp ../../../wb_ddr_ctrl_wb_from_ddr.ngc .
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user