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Added missing planAhead project files

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This commit is contained in:
Matthias Blankertz
2012-11-03 22:35:06 +01:00
parent 9fabbd17a2
commit 3b0da02655
12 changed files with 653 additions and 0 deletions
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22
2d_display_engine.data/constrs_1/fileset.xml Executable file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/2d_display_engine.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/2d_display_engine.ucf"/>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>

20
2d_display_engine.data/runs/impl_1.psg Normal file
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<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>

6
2d_display_engine.data/runs/runs.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="8">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700anfgg484-4" ConstrsSet="constrs_1" Description="PlanAhead Defaults (XST defaults with hierarchy)" State="current"/>
<Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700anfgg484-4" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
</Runs>

9
2d_display_engine.data/runs/synth_1.psg Normal file
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<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="PlanAhead Defaults" Flow="XST14">
<Desc>PlanAhead Defaults (XST defaults with hierarchy)</Desc>
</StratHandle>
<Step Id="xst">
</Step>
</Strategy>

22
2d_display_engine.data/runs/synth_1/constrs_in.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/2d_display_engine.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/2d_display_engine.ucf"/>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>

236
2d_display_engine.data/runs/synth_1/sources.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/toplevel.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_gen_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmp_data_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmd_fsm_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_addr_gen_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_test_bench_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_main_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="toplevel"/>
<Option Name="TopLib" Val="work"/>
<Option Name="TopArchitecture" Val="Mixed"/>
<Option Name="TopRTLFile" Val="$PSRCDIR/sources_1/new/toplevel.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</DARoots>

9
2d_display_engine.data/runs/synth_1/synth_1.psg Normal file
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@@ -0,0 +1,9 @@
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="PlanAhead Defaults" Flow="XST14">
<Desc>PlanAhead Defaults (XST defaults with hierarchy)</Desc>
</StratHandle>
<Step Id="xst">
</Step>
</Strategy>

15
2d_display_engine.data/sim_1/fileset.xml Executable file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="toplevel"/>
<Option Name="TopLib" Val="work"/>
<Option Name="TopArchitecture" Val="Mixed"/>
<Option Name="TopRTLFile" Val="$PSRCDIR/sources_1/new/toplevel.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="NGOutputHDLFormat" Val="vhdl"/>
</Config>
</FileSet>
</DARoots>

236
2d_display_engine.data/sources_1/fileset.xml Executable file
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@@ -0,0 +1,236 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/wb_ddr_ctrl.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/toplevel.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_gen_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmp_data_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmd_fsm_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_addr_gen_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_test_bench_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_main_0.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4.vhd">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInSimulation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="toplevel"/>
<Option Name="TopLib" Val="work"/>
<Option Name="TopArchitecture" Val="Mixed"/>
<Option Name="TopRTLFile" Val="$PSRCDIR/sources_1/new/toplevel.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</DARoots>

24
2d_display_engine.data/wt/java_command_handlers.wdf Executable file
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@@ -0,0 +1,24 @@
version:1
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eof:3362552667

3
2d_display_engine.data/wt/project.wpc Executable file
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@@ -0,0 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:2
eof:

51
2d_display_engine.data/wt/webtalk_pa.xml Executable file
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@@ -0,0 +1,51 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Nov 3 22:26:14 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="b957e4bd74fe47ca91032f9c1b5d8362" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddCore" value="1" type="JavaHandler"/>
<property name="AddSrc" value="8" type="JavaHandler"/>
<property name="CheckForUpdates" value="1" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="2" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="EditFind" value="1" type="JavaHandler"/>
<property name="FileExit" value="1" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenFile" value="1" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="ProjectSummary" value="2" type="JavaHandler"/>
<property name="ReloadDesign" value="2" type="JavaHandler"/>
<property name="RunResourceEstimation" value="2" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="SetTargetUCF" value="2" type="JavaHandler"/>
<property name="ShowSource" value="2" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="2" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
<property name="ui.views.c.e.f" value="1" type="JavaHandler"/>
</item>
<item name="Other">
<property name="GuiMode" value="6" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="0" type="ISEMode"/>
</item>
</section>
</application>
</document>