Initial commit
This commit is contained in:
28
2d_display_engine.ppr
Executable file
28
2d_display_engine.ppr
Executable file
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0"?>
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||||
<!--Product Version: PlanAhead v14.3 (64-bit)-->
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||||
<Project Version="4" Minor="36">
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||||
<FileSet Dir="sources_1" File="fileset.xml"/>
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||||
<FileSet Dir="constrs_1" File="fileset.xml"/>
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||||
<FileSet Dir="sim_1" File="fileset.xml"/>
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<RunSet Dir="runs" File="runs.xml"/>
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||||
<DefaultLaunch Dir="$PRUNDIR"/>
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||||
<DefaultPromote Dir="$PROMOTEDIR"/>
|
||||
<Config>
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||||
<Option Name="Id" Val="50d9205c09c34a16b2c2f1df129a4a3e"/>
|
||||
<Option Name="Part" Val="xc3s700anfgg484-4"/>
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||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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||||
<Option Name="TargetLanguage" Val="VHDL"/>
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||||
<Option Name="TargetSimulator" Val="ISim"/>
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||||
<Option Name="Board" Val="spartan3an"/>
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||||
<Option Name="SourceMgmtMode" Val="All"/>
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||||
<Option Name="ActiveSimSet" Val="sim_1"/>
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||||
<Option Name="CxlOverwriteLibs" Val="1"/>
|
||||
<Option Name="CxlFuncsim" Val="1"/>
|
||||
<Option Name="CxlTimesim" Val="1"/>
|
||||
<Option Name="CxlCore" Val="1"/>
|
||||
<Option Name="CxlEdk" Val="0"/>
|
||||
<Option Name="CxlExcludeCores" Val="1"/>
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||||
<Option Name="CxlExcludeSubLibs" Val="0"/>
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||||
</Config>
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||||
</Project>
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||||
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||||
33
2d_display_engine.srcs/constrs_1/new/2d_display_engine.ucf
Executable file
33
2d_display_engine.srcs/constrs_1/new/2d_display_engine.ucf
Executable file
@@ -0,0 +1,33 @@
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# Timing constraints
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NET "CLKIN_50MHZ" PERIOD = 20.0ns HIGH 40%;
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NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%;
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# Location and I/O defs
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# Clocks
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NET "CLKIN_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
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NET "CLKIN_133MHZ" LOC = "V12"| IOSTANDARD = LVCMOS33 ;
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# VGA output
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NET "VGA_R<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_R<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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# SPI flash
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NET "DATAFLASH_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
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NET "DATAFLASH_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "DATAFLASH_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "DATAFLASH_SS" LOC = "Y4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# write-protect and reset controls for Atmel AT45DB161D PROM
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NET "DATAFLASH_WP" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "DATAFLASH_RST" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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105
2d_display_engine.srcs/sources_1/new/toplevel.vhd
Executable file
105
2d_display_engine.srcs/sources_1/new/toplevel.vhd
Executable file
@@ -0,0 +1,105 @@
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||||
----------------------------------------------------------------------------------
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||||
-- Company:
|
||||
-- Engineer:
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||||
--
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||||
-- Create Date: 11/02/2012 03:48:47 PM
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||||
-- Design Name:
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||||
-- Module Name: toplevel - Mixed
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||||
-- Project Name:
|
||||
-- Target Devices:
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||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
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||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
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||||
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||||
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||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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|
||||
-- Uncomment the following library declaration if using
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||||
-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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||||
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||||
-- Uncomment the following library declaration if instantiating
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||||
-- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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use work.all;
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entity toplevel is
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Port (
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-- global signals
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clkin_50MHz : IN std_ulogic;
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clkin_133MHz : IN std_ulogic;
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reset : IN std_ulogic;
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-- VGA port
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vga_r, vga_g, vga_b : OUT std_ulogic_vector(3 downto 0);
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vga_vsync, vga_hsync : OUT std_ulogic;
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||||
|
||||
-- spi flash
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dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic;
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dataflash_miso : IN std_ulogic;
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|
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-- LEDs
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led : OUT std_ulogic_vector(7 downto 0);
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-- DDR2 SDRAM
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ddr2_dq : inout std_logic_vector(15 downto 0);
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ddr2_a : out std_logic_vector(12 downto 0);
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ddr2_ba : out std_logic_vector(1 downto 0);
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ddr2_cke : out std_logic;
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ddr2_cs_n : out std_logic;
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ddr2_ras_n : out std_logic;
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ddr2_cas_n : out std_logic;
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ddr2_we_n : out std_logic;
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ddr2_odt : out std_logic;
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ddr2_dm : out std_logic_vector(1 downto 0);
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rst_dqs_div_in : in std_logic;
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rst_dqs_div_out : out std_logic;
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ddr2_dqs : inout std_logic_vector(1 downto 0);
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||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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ddr2_ck : out std_logic_vector(0 downto 0);
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ddr2_ck_n : out std_logic_vector(0 downto 0)
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||||
);
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end toplevel;
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architecture Mixed of toplevel is
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begin
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ddr_crtl0 : wb_ddr_ctrl
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port map (
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sys_clock => clk_50MHz,
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sys_reset => reset,
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-- DDR2 control
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ddr2_clock => clkin_133MHz,
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ddr2_reset => reset,
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||||
|
||||
-- DDR2 SDRAM
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ddr2_dq => ddr2_dq,
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ddr2_a => ddr2_a,
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ddr2_ba => dr2_ba,
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ddr2_cke => ddr2_cke,
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ddr2_cs_n => ddr2_cs_n,
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||||
ddr2_ras_n => ddr2_ras_n,
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||||
ddr2_cas_n => ddr2_cas_n,
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ddr2_we_n => ddr2_we_n,
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ddr2_odt => ddr2_odt,
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ddr2_dm => ddr2_dm,
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||||
rst_dqs_div_in => rst_dqs_div_in,
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rst_dqs_div_out => rst_dqs_div_out,
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ddr2_dqs => ddr2_dqs,
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||||
ddr2_dqs_n => ddr2_dqs_n,
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ddr2_ck => ddr2_ck,
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ddr2_ck_n => ddr2_ck_n
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||||
);
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end Mixed;
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||||
93
2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd
Executable file
93
2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd
Executable file
@@ -0,0 +1,93 @@
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||||
----------------------------------------------------------------------------------
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||||
-- Company:
|
||||
-- Engineer:
|
||||
--
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||||
-- Create Date: 11/02/2012 06:00:40 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl - Behavioral
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||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
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||||
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||||
-- Uncomment the following library declaration if instantiating
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||||
-- any Xilinx primitives in this code.
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||||
--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.all;
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entity wb_ddr_ctrl is
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Port (
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-- System control
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sys_clock : in std_ulogic;
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sys_reset : in std_ulogic;
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||||
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||||
-- DDR2 control
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||||
ddr2_clock : in std_ulogic;
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||||
ddr2_reset : in std_ulogic;
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||||
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||||
-- DDR2 SDRAM
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||||
ddr2_dq : inout std_logic_vector(15 downto 0);
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ddr2_a : out std_logic_vector(12 downto 0);
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||||
ddr2_ba : out std_logic_vector(1 downto 0);
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||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
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||||
rst_dqs_div_in : in std_logic;
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||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
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||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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||||
ddr2_ck : out std_logic_vector(0 downto 0);
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||||
ddr2_ck_n : out std_logic_vector(0 downto 0)
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||||
);
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end wb_ddr_ctrl;
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||||
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architecture Behavioral of wb_ddr_ctrl is
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||||
|
||||
begin
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||||
ddr_0 : wb_ddr_ctrl_ddrwrap
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||||
port map (
|
||||
ddr2_clock => ddr2_clock,
|
||||
ddr2_reset => ddr2_reset,
|
||||
|
||||
ddr2_dq => ddr2_dq,
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||||
ddr2_a => ddr2_a,
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||||
ddr2_ba => ddr2_ba,
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||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
160
2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd
Executable file
160
2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd
Executable file
@@ -0,0 +1,160 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11/02/2012 06:12:05 PM
|
||||
-- Design Name:
|
||||
-- Module Name: wb_ddr_ctrl_ddrwrap - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
use work.all;
|
||||
|
||||
entity wb_ddr_ctrl_ddrwrap is
|
||||
Port (
|
||||
-- DDR2 control
|
||||
ddr2_clock_in : in std_ulogic;
|
||||
ddr2_reset : in std_ulogic;
|
||||
|
||||
-- DDR2 ctrl to system
|
||||
ctrl_input_data : in std_logic_vector(31 downto 0);
|
||||
ctrl_data_mask : in std_logic_vector(3 downto 0);
|
||||
ctrl_output_data : out std_logic_vector(31 downto 0) := (others => 'Z');
|
||||
ctrl_data_valid : out std_logic;
|
||||
ctrl_input_address : in std_logic_vector(((13 + 10 + 2)-1) downto 0);
|
||||
ctrl_command_register : in std_logic_vector(2 downto 0);
|
||||
ctrl_burst_done : in std_logic;
|
||||
ctrl_auto_ref_req : out std_logic;
|
||||
ctrl_cmd_ack : out std_logic;
|
||||
ctrl_init_done : out std_logic;
|
||||
ctrl_ar_done : out std_logic;
|
||||
|
||||
-- DDR2 SDRAM
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
|
||||
-- Clock out
|
||||
ddr2_clk0 : out std_ulogic;
|
||||
ddr2_clk90 : out std_ulogic
|
||||
);
|
||||
end wb_ddr_ctrl_ddrwrap;
|
||||
|
||||
architecture Behavioral of wb_ddr_ctrl_ddrwrap is
|
||||
signal ddr2_rst0, ddr2_rst90, ddr2_rst180 : std_logic;
|
||||
signal ddr2_clk0_int, ddr2_clk90_int : std_logic;
|
||||
signal wait_200us : std_logic;
|
||||
signal delay_sel : std_logic_vector(4 downto 0);
|
||||
begin
|
||||
|
||||
infrastructure_0 : vhdl_bl4_infrastructure_top
|
||||
port map (
|
||||
reset_in_n => ddr2_reset,
|
||||
sys_clk => '0',
|
||||
sys_clkb => '0',
|
||||
sys_clk_in => ddr2_clock_in,
|
||||
delay_sel_val1_val => delay_sel,
|
||||
sys_rst_val => ddr2_rst0,
|
||||
sys_rst90_val => ddr2_rst90,
|
||||
sys_rst180_val => ddr2_rst180,
|
||||
clk_int_val => ddr2_clk0_int,
|
||||
clk90_int_val => ddr2_clk90_int,
|
||||
wait_200us => wait_200us,
|
||||
-- debug signals
|
||||
dbg_phase_cnt => open,
|
||||
dbg_cnt => open,
|
||||
dbg_trans_onedtct => open,
|
||||
dbg_trans_twodtct => open,
|
||||
dbg_enb_trans_two_dtct => open
|
||||
);
|
||||
|
||||
top_0 : vhdl_bl4_top_0
|
||||
port map (
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_dm => ddr2_dm,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
|
||||
clk_int => ddr2_clk0_int,
|
||||
clk90_int => ddr2_clk90_int,
|
||||
delay_sel_val => delay_sel,
|
||||
sys_rst => ddr2_rst0,
|
||||
sys_rst90 => ddr2_rst90,
|
||||
sys_rst180 => ddr2_rst180,
|
||||
|
||||
user_input_data => ctrl_input_data,
|
||||
user_data_mask => ctrl_data_mask,
|
||||
user_output_data => ctrl_output_data,
|
||||
user_data_valid => ctrl_data_valid,
|
||||
user_input_address => ctrl_input_address,
|
||||
user_command_register => ctrl_command_register,
|
||||
burst_done => ctrl_burst_done,
|
||||
auto_ref_req => ctrl_auto_ref_req,
|
||||
user_cmd_ack => ctrl_cmd_ack,
|
||||
init_done => ctrl_init_done,
|
||||
ar_done => ctrl_ar_done,
|
||||
|
||||
dbg_delay_sel => open,
|
||||
dbg_rst_calib => open,
|
||||
dbg_controller => open,
|
||||
vio_out_dqs => (others => '0'),
|
||||
vio_out_dqs_en => '0',
|
||||
vio_out_rst_dqs_div => (others => '0'),
|
||||
vio_out_rst_dqs_div_en => '0'
|
||||
);
|
||||
|
||||
ddr2_clk0 <= ddr2_clk0_int;
|
||||
ddr2_clk90 <= ddr2_clk90_int;
|
||||
|
||||
end Behavioral;
|
||||
52
ddr2_sdram/vhdl_bl4/example_design/datasheet.txt
Executable file
52
ddr2_sdram/vhdl_bl4/example_design/datasheet.txt
Executable file
@@ -0,0 +1,52 @@
|
||||
Datasheet
|
||||
Generated by mig Version 3.3 on Fri June 5 11:28 2009
|
||||
|
||||
************* INPUTS GIVEN ***********
|
||||
PART : xc3s700afg484
|
||||
Frequency in MHz : 133
|
||||
Speed grade : -4
|
||||
No of controllers : 1
|
||||
Synthesis tool : XST
|
||||
HDL : vhdl
|
||||
Implementation Options:
|
||||
DCM used : 1
|
||||
Add test bench : 1
|
||||
Number of write pipelines: 4
|
||||
Debug Signals : 1
|
||||
System Clock : Single-Ended
|
||||
Class for Address/Control: Class II
|
||||
Class for Data : Class II
|
||||
|
||||
**************************************
|
||||
Generating interface for controller 0
|
||||
Memory type : DDR2_SDRAM/Components/MT47H32M16XX-5E
|
||||
Supported Part Numbers : MT47H32M16BN-5E;MT47H32M16CC-5E;MT47H32M16FN-5E;MT47H32M16GC-5E
|
||||
Bits per strobe : X8
|
||||
Banks for Data : 1
|
||||
Data bits : 16
|
||||
Banks for addr & cntrl : 1
|
||||
Banks for System Control : 0,2
|
||||
Banks for System Clock : 0
|
||||
Row address bits : 13
|
||||
Column address bits : 10
|
||||
Bank address bits : 2
|
||||
Data mask : 1
|
||||
****************************************************
|
||||
Design Parameters :
|
||||
Mode Register :
|
||||
Burst Length : 4(010)
|
||||
Burst Type : sequential(0)
|
||||
CAS Latency : 3(011)
|
||||
Mode : normal(0)
|
||||
DLL Reset : yes(1)
|
||||
PD Mode : fast exit(0)
|
||||
Write Recovery : 3(010)
|
||||
Extended Mode Register :
|
||||
DLL Enable : Enable-Normal(0)
|
||||
Output Drive Strength : Fullstrength(0)
|
||||
RTT (nominal) - ODT : RTT Disabled(00)
|
||||
Additive Latency (AL) : 0(000)
|
||||
OCD Operation : OCD Exit(000)
|
||||
DQS# Enable : Enable(0)
|
||||
RDQS Enable : Disable(0)
|
||||
Outputs : Enable(0)
|
||||
33
ddr2_sdram/vhdl_bl4/example_design/design_testing.txt
Executable file
33
ddr2_sdram/vhdl_bl4/example_design/design_testing.txt
Executable file
@@ -0,0 +1,33 @@
|
||||
|
||||
Following steps explain how to load the bit files using chip scope.
|
||||
|
||||
Steps to load the bit file:
|
||||
|
||||
1. Open the chipscope analyzer.
|
||||
|
||||
2. Open the project vhdl_bl4.cpj in the par directory by selecting File -> Open Project from the menu and give the
|
||||
path to the Project file.
|
||||
|
||||
3. Activate the cable port by selecting JTAG Chain -> Xilinx Platform USB Cable. Hit 'OK' for the Cable Select screen.
|
||||
|
||||
4. Two devices should be recognized and displayed in the pop-up window. Hit"OK".
|
||||
|
||||
5. Right click on DEV:0 in the upper left hand "New Project" window and choose "configure" to chose a bit file to
|
||||
assign to this device.
|
||||
|
||||
(a) The JTAG configuration window pops up.
|
||||
(b) Hit "Select New File" and navigate to the bit File "par\vhdl_bl4.bit" and hit "OK"
|
||||
|
||||
If orange DONE LED glows, then device configuration was successful.
|
||||
|
||||
Double click the waveform and trigger_setup in the MyILA0.
|
||||
|
||||
Apply the reset, with the help of "Button SOUTH (T15)" push button switch on the board.
|
||||
|
||||
6. On Board clock is used to verify the design. To see the waveforms in the waveform window press Ctrl+F5 or the T! icon
|
||||
in the analyzer window. The LD1 LED should be dimly illuminated to show that there is a valid "cntrl0_data_valid_out"
|
||||
signal, and the LD0 LED should not be illuminated for the passing case (no errors detected in testbench).
|
||||
|
||||
|
||||
|
||||
|
||||
7
ddr2_sdram/vhdl_bl4/example_design/par/create_ise.bat
Executable file
7
ddr2_sdram/vhdl_bl4/example_design/par/create_ise.bat
Executable file
@@ -0,0 +1,7 @@
|
||||
|
||||
coregen -b makeproj.bat
|
||||
coregen -p . -b ila_coregen.xco
|
||||
coregen -p . -b icon_coregen.xco
|
||||
coregen -p . -b vio_coregen.xco
|
||||
|
||||
xtclsh set_ise_prop.tcl
|
||||
48
ddr2_sdram/vhdl_bl4/example_design/par/icon_coregen.xco
Executable file
48
ddr2_sdram/vhdl_bl4/example_design/par/icon_coregen.xco
Executable file
@@ -0,0 +1,48 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.37
|
||||
# Date: Tue Jul 29 11:13:27 2008
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = vhdl
|
||||
SET device = xc3s700a
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = ISE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = False
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET component_name=icon
|
||||
CSET enable_jtag_bufg=true
|
||||
CSET number_control_ports=2
|
||||
CSET use_ext_bscan=false
|
||||
CSET use_softbscan=false
|
||||
CSET use_unused_bscan=false
|
||||
CSET user_scan_chain=USER1
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: b1aa8c39
|
||||
|
||||
131
ddr2_sdram/vhdl_bl4/example_design/par/ila_coregen.xco
Executable file
131
ddr2_sdram/vhdl_bl4/example_design/par/ila_coregen.xco
Executable file
@@ -0,0 +1,131 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.37
|
||||
# Date: Tue Jul 29 10:56:15 2008
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = vhdl
|
||||
SET device = xc3s700a
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = ISE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = False
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET component_name=ila
|
||||
CSET counter_width_1=Disabled
|
||||
CSET counter_width_10=Disabled
|
||||
CSET counter_width_11=Disabled
|
||||
CSET counter_width_12=Disabled
|
||||
CSET counter_width_13=Disabled
|
||||
CSET counter_width_14=Disabled
|
||||
CSET counter_width_15=Disabled
|
||||
CSET counter_width_16=Disabled
|
||||
CSET counter_width_2=Disabled
|
||||
CSET counter_width_3=Disabled
|
||||
CSET counter_width_4=Disabled
|
||||
CSET counter_width_5=Disabled
|
||||
CSET counter_width_6=Disabled
|
||||
CSET counter_width_7=Disabled
|
||||
CSET counter_width_8=Disabled
|
||||
CSET counter_width_9=Disabled
|
||||
CSET data_port_width=58
|
||||
CSET data_same_as_trigger=false
|
||||
CSET enable_storage_qualification=true
|
||||
CSET enable_trigger_output_port=false
|
||||
CSET exclude_from_data_storage_1=true
|
||||
CSET exclude_from_data_storage_10=true
|
||||
CSET exclude_from_data_storage_11=true
|
||||
CSET exclude_from_data_storage_12=true
|
||||
CSET exclude_from_data_storage_13=true
|
||||
CSET exclude_from_data_storage_14=true
|
||||
CSET exclude_from_data_storage_15=true
|
||||
CSET exclude_from_data_storage_16=true
|
||||
CSET exclude_from_data_storage_2=true
|
||||
CSET exclude_from_data_storage_3=true
|
||||
CSET exclude_from_data_storage_4=true
|
||||
CSET exclude_from_data_storage_5=true
|
||||
CSET exclude_from_data_storage_6=true
|
||||
CSET exclude_from_data_storage_7=true
|
||||
CSET exclude_from_data_storage_8=true
|
||||
CSET exclude_from_data_storage_9=true
|
||||
CSET match_type_1=extended_with_edges
|
||||
CSET match_type_10=basic
|
||||
CSET match_type_11=basic
|
||||
CSET match_type_12=basic
|
||||
CSET match_type_13=basic
|
||||
CSET match_type_14=basic
|
||||
CSET match_type_15=basic
|
||||
CSET match_type_16=basic
|
||||
CSET match_type_2=basic
|
||||
CSET match_type_3=basic
|
||||
CSET match_type_4=basic
|
||||
CSET match_type_5=basic
|
||||
CSET match_type_6=basic
|
||||
CSET match_type_7=basic
|
||||
CSET match_type_8=basic
|
||||
CSET match_type_9=basic
|
||||
CSET match_units_1=1
|
||||
CSET match_units_10=1
|
||||
CSET match_units_11=1
|
||||
CSET match_units_12=1
|
||||
CSET match_units_13=1
|
||||
CSET match_units_14=1
|
||||
CSET match_units_15=1
|
||||
CSET match_units_16=1
|
||||
CSET match_units_2=1
|
||||
CSET match_units_3=1
|
||||
CSET match_units_4=1
|
||||
CSET match_units_5=1
|
||||
CSET match_units_6=1
|
||||
CSET match_units_7=1
|
||||
CSET match_units_8=1
|
||||
CSET match_units_9=1
|
||||
CSET max_sequence_levels=1
|
||||
CSET number_of_trigger_ports=1
|
||||
CSET sample_data_depth=512
|
||||
CSET sample_on=Rising
|
||||
CSET trigger_port_width_1=7
|
||||
CSET trigger_port_width_10=8
|
||||
CSET trigger_port_width_11=8
|
||||
CSET trigger_port_width_12=8
|
||||
CSET trigger_port_width_13=8
|
||||
CSET trigger_port_width_14=8
|
||||
CSET trigger_port_width_15=8
|
||||
CSET trigger_port_width_16=8
|
||||
CSET trigger_port_width_2=8
|
||||
CSET trigger_port_width_3=8
|
||||
CSET trigger_port_width_4=8
|
||||
CSET trigger_port_width_5=8
|
||||
CSET trigger_port_width_6=8
|
||||
CSET trigger_port_width_7=8
|
||||
CSET trigger_port_width_8=8
|
||||
CSET trigger_port_width_9=8
|
||||
CSET use_rpms=true
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 5c770836
|
||||
|
||||
20
ddr2_sdram/vhdl_bl4/example_design/par/ise_flow.bat
Executable file
20
ddr2_sdram/vhdl_bl4/example_design/par/ise_flow.bat
Executable file
@@ -0,0 +1,20 @@
|
||||
coregen -b makeproj.bat
|
||||
coregen -p . -b ila_coregen.xco
|
||||
coregen -p . -b icon_coregen.xco
|
||||
coregen -p . -b vio_coregen.xco
|
||||
|
||||
echo Synthesis Tool: XST
|
||||
|
||||
mkdir "../synth/__projnav" > ise_flow_results.txt
|
||||
mkdir "../synth/xst" >> ise_flow_results.txt
|
||||
mkdir "../synth/xst/work" >> ise_flow_results.txt
|
||||
|
||||
xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
|
||||
ngdbuild -intstyle ise -dd ../synth/_ngo -uc vhdl_bl4.ucf -p xc3s700afg484-4 vhdl_bl4.ngc vhdl_bl4.ngd >> ise_flow_results.txt
|
||||
|
||||
map -intstyle ise -detail -cm speed -pr off -c 100 -o vhdl_bl4_map.ncd vhdl_bl4.ngd vhdl_bl4.pcf >> ise_flow_results.txt
|
||||
par -w -intstyle ise -ol std -t 1 vhdl_bl4_map.ncd vhdl_bl4.ncd vhdl_bl4.pcf >> ise_flow_results.txt
|
||||
trce -e 100 vhdl_bl4.ncd vhdl_bl4.pcf >> ise_flow_results.txt
|
||||
bitgen -intstyle ise -f mem_interface_top.ut vhdl_bl4.ncd >> ise_flow_results.txt
|
||||
|
||||
echo done!
|
||||
64
ddr2_sdram/vhdl_bl4/example_design/par/ise_run.txt
Executable file
64
ddr2_sdram/vhdl_bl4/example_design/par/ise_run.txt
Executable file
@@ -0,0 +1,64 @@
|
||||
set -tmpdir ../synth/__projnav
|
||||
set -xsthdpdir ../synth/xst
|
||||
run
|
||||
#Source Parameters
|
||||
-ifn ../synth/vhdl_bl4.prj
|
||||
-ifmt mixed
|
||||
-iuc No
|
||||
#Target Parameters
|
||||
-ofn vhdl_bl4
|
||||
-ofmt NGC
|
||||
-p xc3s700a-4fg484
|
||||
#Source Options
|
||||
-top vhdl_bl4
|
||||
-fsm_extract Yes
|
||||
-fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-rom_style Auto
|
||||
-mux_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract Yes
|
||||
-priority_extract Yes
|
||||
-shreg_extract Yes
|
||||
-shift_extract Yes
|
||||
-xor_collapse Yes
|
||||
-resource_sharing Yes
|
||||
-async_to_sync no
|
||||
-mult_style auto
|
||||
-register_balancing No
|
||||
#Target Options
|
||||
-iobuf Yes
|
||||
-max_fanout 500
|
||||
-bufg 8
|
||||
-register_duplication yes
|
||||
-slice_packing yes
|
||||
-optimize_primitives No
|
||||
-use_clock_enable yes
|
||||
-use_sync_set yes
|
||||
-use_sync_reset yes
|
||||
-iob auto
|
||||
-equivalent_register_removal yes
|
||||
#General Options
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-lso ../synth/vhdl_bl4.lso
|
||||
-keep_hierarchy soft
|
||||
-netlist_hierarchy as_optimized
|
||||
-rtlview Yes
|
||||
-glob_opt allclocknets
|
||||
-read_cores Yes
|
||||
-write_timing_constraints No
|
||||
-cross_clock_analysis No
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-verilog2001 Yes
|
||||
-auto_bram_packing No
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
quit
|
||||
2
ddr2_sdram/vhdl_bl4/example_design/par/makeproj.bat
Executable file
2
ddr2_sdram/vhdl_bl4/example_design/par/makeproj.bat
Executable file
@@ -0,0 +1,2 @@
|
||||
NEWPROJECT .
|
||||
SETPROJECT .
|
||||
23
ddr2_sdram/vhdl_bl4/example_design/par/mem_interface_top.ut
Executable file
23
ddr2_sdram/vhdl_bl4/example_design/par/mem_interface_top.ut
Executable file
@@ -0,0 +1,23 @@
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g CclkPin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullNone
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g ConfigRate:6
|
||||
|
||||
81
ddr2_sdram/vhdl_bl4/example_design/par/readme.txt
Executable file
81
ddr2_sdram/vhdl_bl4/example_design/par/readme.txt
Executable file
@@ -0,0 +1,81 @@
|
||||
This folder has the batch files to synthesize using the XST or Synplify Pro
|
||||
and PAR the design through command mode.
|
||||
|
||||
Steps to run the design using the ise_flow (batch mode):
|
||||
|
||||
1. Executing the ise_flow.bat file, synthesizes the design using
|
||||
XST or Synplify Pro and does the PAR.
|
||||
On running "ise_flow.bat" file, removes the XST/Synplify Pro report
|
||||
files first (if exist any on previous runs) and then does
|
||||
implementation of the design.
|
||||
|
||||
2. On running the ise_flow.bat file, creates the all report files.
|
||||
|
||||
Steps to run the design using the create_ise (GUI mode - for XST cases only):
|
||||
|
||||
1. This file will appear for XST cases only.
|
||||
|
||||
2. On executing the "create_ise.bat" file creates "test.xise" project file
|
||||
and set all the properties of the design selected.
|
||||
|
||||
3. The design can be implemented in ISE Projnav GUI by invoking
|
||||
the "test.xise" project file.
|
||||
|
||||
4. In Linux operating systems, test.xise project can be invoked by executing
|
||||
the command 'ise test.xise' from the terminal.
|
||||
|
||||
About other files in PAR folder :
|
||||
|
||||
* vhdl_bl4.ucf file is the constratint file for the design. This is used
|
||||
by ISE tool during PAR phase. It has all the clock constraints,
|
||||
Location constraints, false paths if any, IO standards and
|
||||
Area group constraints if any.
|
||||
|
||||
* ise_run.txt file has synthesis options for the XST tool.
|
||||
This file is used for batch mode.
|
||||
|
||||
* mem_interface_top.ut file has the options for the Configuration file
|
||||
generation i.e. the .bit file.
|
||||
|
||||
|
||||
* "set_ise_prop.tcl" file has all the properties that needs to be set
|
||||
in GUI mode. This file will appear only for XST cases.
|
||||
|
||||
* "icon_coregen.xco" and "ila_coregen.xco" files are used to
|
||||
generate chipscope ila and icon EDIF/NGC files. view the design signals
|
||||
on chipscope, you should port the design signals to chipscope modules
|
||||
i.e., ila and icon and set DEBUG_EN parameter to 1 in vhdl_bl4 rtl file.
|
||||
In order to generate the EDIF/NGC files, you must execute the following
|
||||
commands before starting systhesis and PAR.
|
||||
|
||||
coregen -b ila_coregen.xco
|
||||
coregen -b icon_coregen.xco
|
||||
coregen -b vio_coregen.xco
|
||||
|
||||
Note : When you generate the design usign DEBUG_EN option, the above mentioned
|
||||
chipscope coregen commands are printed into ise_flow.bat and
|
||||
create_ise.bat files. The vhdl_bl4 rtl file will have the design
|
||||
debug signals portmapped to ila and icon chipscope modules.
|
||||
|
||||
* At the start of a Chip Scope Analyzer project, all of the signals in
|
||||
every core have generic names. "vhdl_bl4.cdc" is a file that contains
|
||||
all the signal names of all cores. Upon importing this file, signal names are
|
||||
renamed to the specified names in "vhdl_bl4.cdc" file. This file will work
|
||||
for the generated designs from MIG. If any of the design parameter values
|
||||
are changed after generating the design, this file will not work.
|
||||
|
||||
Synth folder:
|
||||
|
||||
* Synth folder has the constraint file for synplify Pro designs i.e.
|
||||
the .sdc file, Project file which has the design files to be added to
|
||||
the project i.e. the .prj file and the synthesis tool options file for
|
||||
synplify Pro i.e. .tcl file.
|
||||
|
||||
Design without chipscope :
|
||||
|
||||
If the user wants to run the design without chipscope, following are the steps required
|
||||
to be done by the user.
|
||||
|
||||
1. Set the parameter DEBUG_EN to 0 in vhdl_bl4_parameters_0.vhd under rtl folder
|
||||
2. Comment out coregen commands in ise_flow.bat in par directory
|
||||
3. Run ise_flow.bat
|
||||
129
ddr2_sdram/vhdl_bl4/example_design/par/set_ise_prop.tcl
Executable file
129
ddr2_sdram/vhdl_bl4/example_design/par/set_ise_prop.tcl
Executable file
@@ -0,0 +1,129 @@
|
||||
project new test.ise
|
||||
|
||||
project set "Device Family" "spartan3a"
|
||||
|
||||
project set "Device" "xc3s700a"
|
||||
|
||||
project set "Package" "fg484"
|
||||
|
||||
project set "Speed Grade" "-4"
|
||||
|
||||
project set "Synthesis Tool" "XST (VHDL/Verilog)"
|
||||
|
||||
project set "Simulator" "ISim (VHDL/Verilog)"
|
||||
|
||||
xfile add "../rtl/vhdl_bl4_parameters_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_addr_gen_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_cal_ctl.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_cal_top.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_clk_dcm.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_cmd_fsm_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_cmp_data_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_controller_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_controller_iobs_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_gen_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_path_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_path_iobs_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_read_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_read_controller_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_data_write_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_dqs_delay_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_fifo_0_wr_en_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_fifo_1_wr_en_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_infrastructure.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_infrastructure_iobs_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_infrastructure_top.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_iobs_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_main_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_ram8d_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_ram8d_1.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_rd_gray_cntr.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_s3_dm_iob.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_s3_dq_iob.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_s3_dqs_iob.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_tap_dly.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_test_bench_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_top_0.vhd"
|
||||
xfile add "../rtl/vhdl_bl4_wr_gray_cntr.vhd"
|
||||
|
||||
xfile add "vhdl_bl4.ucf"
|
||||
|
||||
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
|
||||
project set "Safe Implementation" "No" -process "Synthesize - XST"
|
||||
project set "FSM Style" "LUT" -process "Synthesize - XST"
|
||||
project set "RAM Extraction" "True" -process "Synthesize - XST"
|
||||
project set "RAM Style" "Auto" -process "Synthesize - XST"
|
||||
project set "ROM Extraction" "True" -process "Synthesize - XST"
|
||||
project set "ROM Style" "Auto" -process "Synthesize - XST"
|
||||
project set "Mux Extraction" "Yes" -process "Synthesize - XST"
|
||||
project set "Mux Style" "Auto" -process "Synthesize - XST"
|
||||
project set "Decoder Extraction" "True" -process "Synthesize - XST"
|
||||
project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST"
|
||||
project set "Shift Register Extraction" "True" -process "Synthesize - XST"
|
||||
project set "Logical Shifter Extraction" "True" -process "Synthesize - XST"
|
||||
project set "XOR Collapsing" "True" -process "Synthesize - XST"
|
||||
project set "Resource Sharing" "True" -process "Synthesize - XST"
|
||||
project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
|
||||
project set "Register Balancing" "No" -process "Synthesize - XST"
|
||||
project set "Add I/O Buffers" "True" -process "Synthesize - XST"
|
||||
project set "Max Fanout" "500" -process "Synthesize - XST"
|
||||
project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
|
||||
project set "Register Duplication" "True" -process "Synthesize - XST"
|
||||
project set "Slice Packing" "True" -process "Synthesize - XST"
|
||||
project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
|
||||
project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
|
||||
project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
|
||||
project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
|
||||
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
|
||||
project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
|
||||
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
|
||||
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
|
||||
project set "Library Search Order" "../synth/vhdl_bl4.lso" -process "Synthesize - XST"
|
||||
project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
|
||||
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
|
||||
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
|
||||
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
|
||||
project set "Read Cores" "True" -process "Synthesize - XST"
|
||||
project set "Write Timing Constraints" "False" -process "Synthesize - XST"
|
||||
project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
|
||||
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
|
||||
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
|
||||
project set "Case" "Maintain" -process "Synthesize - XST"
|
||||
project set "Slice Utilization Ratio" "100" -process "Synthesize - XST"
|
||||
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
|
||||
project set "Verilog 2001" "True" -process "Synthesize - XST"
|
||||
project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
|
||||
|
||||
project set "Optimization Strategy (Cover Mode)" "Speed" -process Map
|
||||
project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
|
||||
|
||||
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
|
||||
project set "Starting Placer Cost Table (1-100)" "1" -process "Place & Route"
|
||||
|
||||
project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
|
||||
|
||||
project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
|
||||
project set "Create Binary Configuration File" "False" -process "Generate Programming File"
|
||||
project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
|
||||
project set "Configuration Rate" "6" -process "Generate Programming File"
|
||||
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
|
||||
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
|
||||
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
|
||||
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
|
||||
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
|
||||
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
|
||||
project set "Unused IOB Pins" "Float" -process "Generate Programming File"
|
||||
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
|
||||
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
|
||||
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
|
||||
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
|
||||
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
|
||||
project set "Wait for DLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
|
||||
project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
|
||||
project set "Drive Done Pin High" "False" -process "Generate Programming File"
|
||||
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
|
||||
|
||||
project close
|
||||
|
||||
|
||||
BIN
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.bit
Executable file
BIN
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.bit
Executable file
Binary file not shown.
98
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.cdc
Executable file
98
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.cdc
Executable file
@@ -0,0 +1,98 @@
|
||||
#ChipScope Core Inserter Project File Version 3.0
|
||||
#Mon Aug 24 11:12:23 IST 2009
|
||||
|
||||
Project.unit.count=2
|
||||
|
||||
Project.unit<0>.type=ila
|
||||
Project.unit<0>.dataPortWidth=58
|
||||
Project.unit<0>.triggerPort<0000>.name=TRIG0
|
||||
Project.unit<0>.triggerPortCount=1
|
||||
Project.unit<0>.triggerPortIsData<0000>=false
|
||||
Project.unit<0>.triggerPortWidth<0000>=7
|
||||
Project.unit<0>.triggerChannel<0000><0000>=dbg_enb_trans_two_dtct
|
||||
Project.unit<0>.triggerChannel<0000><0001>=dbg_trans_twodtct
|
||||
Project.unit<0>.triggerChannel<0000><0002>=dbg_trans_onedtct
|
||||
Project.unit<0>.triggerChannel<0000><0003>=dbg_rst_calib
|
||||
Project.unit<0>.triggerChannel<0000><0004>=dbg_init_done
|
||||
Project.unit<0>.triggerChannel<0000><0005>=dbg_led_error_out
|
||||
Project.unit<0>.triggerChannel<0000><0006>=dbg_data_valid_out
|
||||
Project.unit<0>.dataEqualsTrigger=false
|
||||
Project.unit<0>.dataChannel<0000>=dbg_enb_trans_two_dtct
|
||||
Project.unit<0>.dataChannel<0001>=dbg_trans_twodtct
|
||||
Project.unit<0>.dataChannel<0002>=dbg_trans_onedtct
|
||||
Project.unit<0>.dataChannel<0003>=dbg_cnt[0]
|
||||
Project.unit<0>.dataChannel<0004>=dbg_cnt[1]
|
||||
Project.unit<0>.dataChannel<0005>=dbg_cnt[2]
|
||||
Project.unit<0>.dataChannel<0006>=dbg_cnt[3]
|
||||
Project.unit<0>.dataChannel<0007>=dbg_cnt[4]
|
||||
Project.unit<0>.dataChannel<0008>=dbg_cnt[5]
|
||||
Project.unit<0>.dataChannel<0009>=dbg_phase_cnt[0]
|
||||
Project.unit<0>.dataChannel<0010>=dbg_phase_cnt[1]
|
||||
Project.unit<0>.dataChannel<0011>=dbg_phase_cnt[2]
|
||||
Project.unit<0>.dataChannel<0012>=dbg_phase_cnt[3]
|
||||
Project.unit<0>.dataChannel<0013>=dbg_phase_cnt[4]
|
||||
Project.unit<0>.dataChannel<0014>=dbg_rst_calib
|
||||
Project.unit<0>.dataChannel<0015>=dbg_delay_sel[0]
|
||||
Project.unit<0>.dataChannel<0016>=dbg_delay_sel[1]
|
||||
Project.unit<0>.dataChannel<0017>=dbg_delay_sel[2]
|
||||
Project.unit<0>.dataChannel<0018>=dbg_delay_sel[3]
|
||||
Project.unit<0>.dataChannel<0019>=dbg_delay_sel[4]
|
||||
Project.unit<0>.dataChannel<0020>=dbg_init_done
|
||||
Project.unit<0>.dataChannel<0021>=dbg_led_error_out
|
||||
Project.unit<0>.dataChannel<0022>=dbg_data_valid_out
|
||||
Project.unit<0>.dataChannel<0023>=dbg_cmp_data[0]
|
||||
Project.unit<0>.dataChannel<0024>=dbg_cmp_data[1]
|
||||
Project.unit<0>.dataChannel<0025>=dbg_cmp_data[2]
|
||||
Project.unit<0>.dataChannel<0026>=dbg_cmp_data[3]
|
||||
Project.unit<0>.dataChannel<0027>=dbg_cmp_data[4]
|
||||
Project.unit<0>.dataChannel<0028>=dbg_cmp_data[5]
|
||||
Project.unit<0>.dataChannel<0029>=dbg_cmp_data[6]
|
||||
Project.unit<0>.dataChannel<0030>=dbg_cmp_data[7]
|
||||
Project.unit<0>.dataChannel<0031>=dbg_cmp_data[8]
|
||||
Project.unit<0>.dataChannel<0032>=dbg_cmp_data[9]
|
||||
Project.unit<0>.dataChannel<0033>=dbg_cmp_data[10]
|
||||
Project.unit<0>.dataChannel<0034>=dbg_cmp_data[11]
|
||||
Project.unit<0>.dataChannel<0035>=dbg_cmp_data[12]
|
||||
Project.unit<0>.dataChannel<0036>=dbg_cmp_data[13]
|
||||
Project.unit<0>.dataChannel<0037>=dbg_cmp_data[14]
|
||||
Project.unit<0>.dataChannel<0038>=dbg_cmp_data[15]
|
||||
Project.unit<0>.dataChannel<0039>=dbg_cmp_data[16]
|
||||
Project.unit<0>.dataChannel<0040>=dbg_cmp_data[17]
|
||||
Project.unit<0>.dataChannel<0041>=dbg_cmp_data[18]
|
||||
Project.unit<0>.dataChannel<0042>=dbg_cmp_data[19]
|
||||
Project.unit<0>.dataChannel<0043>=dbg_cmp_data[20]
|
||||
Project.unit<0>.dataChannel<0044>=dbg_cmp_data[21]
|
||||
Project.unit<0>.dataChannel<0045>=dbg_cmp_data[22]
|
||||
Project.unit<0>.dataChannel<0046>=dbg_cmp_data[23]
|
||||
Project.unit<0>.dataChannel<0047>=dbg_cmp_data[24]
|
||||
Project.unit<0>.dataChannel<0048>=dbg_cmp_data[25]
|
||||
Project.unit<0>.dataChannel<0049>=dbg_cmp_data[26]
|
||||
Project.unit<0>.dataChannel<0050>=dbg_cmp_data[27]
|
||||
Project.unit<0>.dataChannel<0051>=dbg_cmp_data[28]
|
||||
Project.unit<0>.dataChannel<0052>=dbg_cmp_data[29]
|
||||
Project.unit<0>.dataChannel<0053>=dbg_cmp_data[30]
|
||||
Project.unit<0>.dataChannel<0054>=dbg_cmp_data[31]
|
||||
Project.unit<0>.dataChannel<0055>=dbg_controller[0]
|
||||
Project.unit<0>.dataChannel<0056>=dbg_controller[1]
|
||||
Project.unit<0>.dataChannel<0057>=dbg_controller[2]
|
||||
Project.unit<0>.clockChannel=clk_0
|
||||
|
||||
|
||||
Project.unit<1>.type=vio
|
||||
Project.unit<1>.asyncInputWidth=0
|
||||
Project.unit<1>.asyncOutput<0000>=vio_out_dqs[0]
|
||||
Project.unit<1>.asyncOutput<0001>=vio_out_dqs[1]
|
||||
Project.unit<1>.asyncOutput<0002>=vio_out_dqs[2]
|
||||
Project.unit<1>.asyncOutput<0003>=vio_out_dqs[3]
|
||||
Project.unit<1>.asyncOutput<0004>=vio_out_dqs[4]
|
||||
Project.unit<1>.asyncOutput<0005>=vio_out_dqs_en
|
||||
Project.unit<1>.asyncOutput<0006>=vio_out_rst_dqs_div[0]
|
||||
Project.unit<1>.asyncOutput<0007>=vio_out_rst_dqs_div[1]
|
||||
Project.unit<1>.asyncOutput<0008>=vio_out_rst_dqs_div[2]
|
||||
Project.unit<1>.asyncOutput<0009>=vio_out_rst_dqs_div[3]
|
||||
Project.unit<1>.asyncOutput<0010>=vio_out_rst_dqs_div[4]
|
||||
Project.unit<1>.asyncOutput<0011>=vio_out_rst_dqs_div_en
|
||||
Project.unit<1>.asyncOutputWidth=12
|
||||
Project.unit<1>.syncInputWidth=0
|
||||
Project.unit<1>.syncOutputWidth=0
|
||||
|
||||
630
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.ucf
Executable file
630
ddr2_sdram/vhdl_bl4/example_design/par/vhdl_bl4.ucf
Executable file
@@ -0,0 +1,630 @@
|
||||
#################################################################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2008 www.xilinx.com
|
||||
## Fri January 4 11:51: 2008
|
||||
##
|
||||
##
|
||||
##################################################################################################################
|
||||
## File name : vhdl_bl4.ucf
|
||||
##
|
||||
## Description : Constraints file
|
||||
## targetted to FPGA: xc3s700afg484
|
||||
## Speed Grade: -4
|
||||
## FPGA family: spartan3a
|
||||
## Design Entry: vhdl
|
||||
## Frequency: 133 MHz
|
||||
## Data width: 16
|
||||
## Memory: DDR2_SDRAM/Components/MT47H32M16XX-5E
|
||||
## Supported Part Numbers: MT47H32M16BN-5E;MT47H32M16CC-5E;MT47H32M16FN-5E;MT47H32M16GC-5E
|
||||
## Design: with Test bench
|
||||
## DCM Used: Enabled
|
||||
## Data Mask: Enabled
|
||||
##
|
||||
####################################################################################################################
|
||||
|
||||
#####################################################################################################################
|
||||
## Clock constraints
|
||||
#####################################################################################################################
|
||||
NET "ddr_ctrl0/ddr0/infrastructure_0/sys_clk_ibuf" TNM_NET = "SYS_CLK";
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5187 ns HIGH 50 %;
|
||||
|
||||
#######################################################################################################################
|
||||
## Calibration Circuit Constraints
|
||||
#######################################################################################################################
|
||||
## Placement constraints for LUTS in tap delay ckt
|
||||
#######################################################################################################################
|
||||
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;
|
||||
|
||||
#######################################################################################################################
|
||||
# Placement constraints for first stage flops in tap delay ckt #
|
||||
#######################################################################################################################
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;
|
||||
|
||||
#######################################################################################################################
|
||||
## BEL constraints for LUTS in tap delay ckt
|
||||
#######################################################################################################################
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l0" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l1" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l2" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l3" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l4" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l5" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l6" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l7" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l8" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l9" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l10" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l11" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l12" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l13" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l14" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l15" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l16" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l17" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l18" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l19" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l20" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l21" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l22" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l23" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l24" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l25" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l26" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l27" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l28" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l29" BEL= F;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l30" BEL= G;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l31" BEL= F;
|
||||
|
||||
##############################################################################################################
|
||||
## Area Group Constraint For tap_dly and cal_ctl module.
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0/l0" RLOC_ORIGIN=X28Y16;
|
||||
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
|
||||
INST "ddr_ctrl0/ddr0/infrastructure_0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
|
||||
AREA_GROUP "cal_ctl" RANGE = SLICE_X26Y8:SLICE_X37Y21;
|
||||
AREA_GROUP "cal_ctl" GROUP = CLOSED;
|
||||
################################################################################################################
|
||||
#**************************************************************************************************************#
|
||||
# CONTROLLER 0 #
|
||||
#**************************************************************************************************************#
|
||||
################################################################################################################
|
||||
# I/O STANDARDS
|
||||
################################################################################################################
|
||||
#NET "sys_clk_in" IOSTANDARD = LVCMOS33;
|
||||
NET "ddr2_a[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ba[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_cke" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_cs_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_ras_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_cas_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_we_n" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_odt" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dm[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "rst_dqs_div_in" IOSTANDARD = SSTL18_I;
|
||||
NET "rst_dqs_div_out" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dq[*]" IOSTANDARD = SSTL18_I;
|
||||
NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_I;
|
||||
|
||||
####################################################################################################################
|
||||
# Banks 2
|
||||
# Pin Location Constraints for System clock signals
|
||||
####################################################################################################################
|
||||
#NET "sys_clk_in" LOC = "V12"; # on board clock
|
||||
#NET "sys_clk_in" LOC = "U12"; #external clock
|
||||
|
||||
####################################################################################################################
|
||||
# Banks 3
|
||||
# Pin Location Constraints for Clock,Masks, Address, and Controls
|
||||
####################################################################################################################
|
||||
NET "ddr2_ck[0]" LOC = "M1" ;
|
||||
NET "ddr2_ck_n[0]" LOC = "M2" ;
|
||||
NET "ddr2_dm[0]" LOC = "J3" ;
|
||||
NET "ddr2_dm[1]" LOC = "E3" ;
|
||||
NET "ddr2_a[0]" LOC = "R2" ;
|
||||
NET "ddr2_a[1]" LOC = "T4" ;
|
||||
NET "ddr2_a[2]" LOC = "R1" ;
|
||||
NET "ddr2_a[3]" LOC = "U3" ;
|
||||
NET "ddr2_a[4]" LOC = "U2" ;
|
||||
NET "ddr2_a[5]" LOC = "U4" ;
|
||||
NET "ddr2_a[6]" LOC = "U1" ;
|
||||
NET "ddr2_a[7]" LOC = "Y1" ;
|
||||
NET "ddr2_a[8]" LOC = "W1" ;
|
||||
NET "ddr2_a[9]" LOC = "W2" ;
|
||||
NET "ddr2_a[10]" LOC = "T3" ;
|
||||
NET "ddr2_a[11]" LOC = "V1" ;
|
||||
NET "ddr2_a[12]" LOC = "Y2" ;
|
||||
NET "ddr2_ba[0]" LOC = "P3" ;
|
||||
NET "ddr2_ba[1]" LOC = "R3" ;
|
||||
NET "ddr2_cke" LOC = "N3" ;
|
||||
NET "ddr2_cs_n" LOC = "M5" ;
|
||||
NET "ddr2_ras_n" LOC = "M3" ;
|
||||
NET "ddr2_cas_n" LOC = "M4" ;
|
||||
NET "ddr2_we_n" LOC = "N4" ;
|
||||
NET "ddr2_odt" LOC = "P1" ;
|
||||
|
||||
#NET "reset_in_n" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ;
|
||||
#NET "cntrl0_led_error_output1" LOC = "R20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO | PULLDOWN ;
|
||||
#NET "cntrl0_data_valid_out" LOC = "T19" | IOSTANDARD = LVTTL;
|
||||
#NET "cntrl0_init_done" LOC = "V16" | IOSTANDARD = LVTTL;
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## MAXDELAY constraints
|
||||
##############################################################################################################
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
|
||||
## accurate calibration of tap delays. The following constraints are independent of frequency.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[7]" MAXDELAY = 400ps;
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 400ps;
|
||||
NET "ddr_ctrl0/ddr_0/infrastructure_0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 400ps;
|
||||
|
||||
##############################################################################################################
|
||||
## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the
|
||||
## wire delays between the LUTs.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*" MAXDELAY = 190ps;
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*" MAXDELAY = 200 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint from the dqs PAD to input of LUT delay element.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/dqs_int_delay_in*" MAXDELAY = 580 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Constraint from rst_dqs_div_in PAD to input of LUT delay element.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/dqs_div_rst" MAXDELAY = 460 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.
|
||||
## These constraints are required since these paths are not covered by timing analysis. The requirement is total
|
||||
## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 3007 ps;
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/fifo*_wr_en*" MAXDELAY = 3007 ps;
|
||||
|
||||
##############################################################################################################
|
||||
## The MAXDELAY value on fifo write address should be less than clock period. This constraint is
|
||||
## required since this path is not covered by timing analysis.
|
||||
##############################################################################################################
|
||||
NET "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/fifo*_wr_addr[*]" MAXDELAY = 6390 ps;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[1]" LOC = K5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit1" LOC = SLICE_X0Y58;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit1" LOC = SLICE_X0Y59;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[0]" LOC = H1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit0" LOC = SLICE_X2Y62;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit0" LOC = SLICE_X2Y63;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 3, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[3]" LOC = L3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit3" LOC = SLICE_X2Y52;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit3" LOC = SLICE_X2Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 2, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[2]" LOC = K1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit2" LOC = SLICE_X0Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit2" LOC = SLICE_X0Y51;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dqs[0]" LOC = K3;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs_n, 0, location in tile: 0
|
||||
##############################################################################################################
|
||||
#############################################################
|
||||
NET "ddr2_dqs_n[0]" LOC = K2;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col0
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X2Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X2Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X2Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X2Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X3Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col1
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X0Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X0Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X0Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X0Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X1Y55;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X1Y54;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for Fifo write address and write enable
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y49;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X1Y53;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X3Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 5, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[5]" LOC = L1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit5" LOC = SLICE_X2Y50;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit5" LOC = SLICE_X2Y51;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 4, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[4]" LOC = L5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit4" LOC = SLICE_X0Y52;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit4" LOC = SLICE_X0Y53;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 7, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[7]" LOC = H2;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit7" LOC = SLICE_X0Y62;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit7" LOC = SLICE_X0Y63;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 6, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[6]" LOC = K4;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0/fifo_bit6" LOC = SLICE_X2Y58;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe0_n/fifo_bit6" LOC = SLICE_X2Y59;
|
||||
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 9, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[9]" LOC = G4;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit1" LOC = SLICE_X2Y78;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit1" LOC = SLICE_X2Y79;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 8, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[8]" LOC = F2;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit0" LOC = SLICE_X0Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit0" LOC = SLICE_X0Y71;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 11, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[11]" LOC = H6;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit3" LOC = SLICE_X2Y76;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit3" LOC = SLICE_X2Y77;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 10, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[10]" LOC = G1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit2" LOC = SLICE_X2Y68;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit2" LOC = SLICE_X2Y69;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dqs[1]" LOC = K6;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dqs_n, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
#############################################################
|
||||
NET "ddr2_dqs_n[1]" LOC = J5;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col0
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X2Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X2Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X2Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X2Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X3Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X3Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## LUT location constraints for dqs_delayed_col1
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X0Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X0Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X0Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X0Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X1Y75;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X1Y74;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for Fifo write address and write enable
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y69;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC = SLICE_X1Y72;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC = SLICE_X3Y72;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 13, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[13]" LOC = F1;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit5" LOC = SLICE_X2Y70;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit5" LOC = SLICE_X2Y71;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 12, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[12]" LOC = H5;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit4" LOC = SLICE_X0Y76;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit4" LOC = SLICE_X0Y77;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 15, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[15]" LOC = F3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit7" LOC = SLICE_X0Y78;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit7" LOC = SLICE_X0Y79;
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_ddr2_dq, 14, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "ddr2_dq[14]" LOC = G3;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1/fifo_bit6" LOC = SLICE_X0Y68;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read0/strobe1_n/fifo_bit6" LOC = SLICE_X0Y69;
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1
|
||||
##############################################################################################################
|
||||
NET "rst_dqs_div_in" LOC = H4;
|
||||
|
||||
##############################################################################################################
|
||||
## Slice location constraints for delayed rst_dqs_div signal
|
||||
##############################################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y66;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y67;
|
||||
INST "ddr_ctrl0/ddr_0/top_0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
|
||||
|
||||
##############################################################################################################
|
||||
## constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 0
|
||||
##############################################################################################################
|
||||
NET "rst_dqs_div_out" LOC = H3;
|
||||
#################################################################################
|
||||
INST "ddr_ctrl0/ddr_0/top_0/controller0/rst_dqs_div_r" LOC = SLICE_X4Y66;
|
||||
51
ddr2_sdram/vhdl_bl4/example_design/par/vio_coregen.xco
Executable file
51
ddr2_sdram/vhdl_bl4/example_design/par/vio_coregen.xco
Executable file
@@ -0,0 +1,51 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.37
|
||||
# Date: Tue Jul 29 11:12:08 2008
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = vhdl
|
||||
SET device = xc3s700a
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = ISE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = False
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET asynchronous_input_port_width=8
|
||||
CSET asynchronous_output_port_width=12
|
||||
CSET component_name=vio
|
||||
CSET enable_asynchronous_input_port=false
|
||||
CSET enable_asynchronous_output_port=true
|
||||
CSET enable_synchronous_input_port=false
|
||||
CSET enable_synchronous_output_port=false
|
||||
CSET invert_clock_input=false
|
||||
CSET synchronous_input_port_width=8
|
||||
CSET synchronous_output_port_width=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 862f8b9d
|
||||
|
||||
348
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4.vhd
Executable file
348
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4.vhd
Executable file
@@ -0,0 +1,348 @@
|
||||
--*****************************************************************************
|
||||
-- (c) Copyright 2005 - 2009 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : %module_name.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations infrastructure_top and
|
||||
-- main modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4 is
|
||||
port (
|
||||
cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
cntrl0_ddr2_a : out std_logic_vector(12 downto 0);
|
||||
cntrl0_ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
cntrl0_ddr2_cke : out std_logic;
|
||||
cntrl0_ddr2_cs_n : out std_logic;
|
||||
cntrl0_ddr2_ras_n : out std_logic;
|
||||
cntrl0_ddr2_cas_n : out std_logic;
|
||||
cntrl0_ddr2_we_n : out std_logic;
|
||||
cntrl0_ddr2_odt : out std_logic;
|
||||
cntrl0_ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
cntrl0_rst_dqs_div_in : in std_logic;
|
||||
cntrl0_rst_dqs_div_out : out std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
cntrl0_led_error_output1 : out std_logic;
|
||||
cntrl0_data_valid_out : out std_logic;
|
||||
cntrl0_init_done : out std_logic;
|
||||
reset_in_n : in std_logic;
|
||||
cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
cntrl0_ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0)
|
||||
);
|
||||
end vhdl_bl4;
|
||||
|
||||
architecture arc_mem_interface_top of vhdl_bl4 is
|
||||
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
|
||||
ATTRIBUTE X_CORE_INFO of arc_mem_interface_top : ARCHITECTURE IS "mig_v3_3_ddr2_sp3, Coregen 11.4";
|
||||
ATTRIBUTE CORE_GENERATION_INFO of arc_mem_interface_top : ARCHITECTURE IS "ddr2_sp3,mig_v3_3,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000}";
|
||||
|
||||
component vhdl_bl4_main_0
|
||||
port(
|
||||
ddr2_dq : inout std_logic_vector(15 downto 0);
|
||||
ddr2_a : out std_logic_vector(12 downto 0);
|
||||
ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_dm : out std_logic_vector(1 downto 0);
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
led_error_output1 : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
init_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector(1 downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
|
||||
ddr2_ck : out std_logic_vector(0 downto 0);
|
||||
ddr2_ck_n : out std_logic_vector(0 downto 0);
|
||||
clk_int : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
wait_200us : in std_logic;
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
--Debug ports
|
||||
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_cmp_data : out std_logic_vector(31 downto 0);
|
||||
dbg_test_bench : out std_logic_vector(2 downto 0);
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_infrastructure_top
|
||||
port (
|
||||
sys_clkb : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
reset_in_n : in std_logic;
|
||||
wait_200us : out std_logic;
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
sys_rst_val : out std_logic;
|
||||
sys_rst90_val : out std_logic;
|
||||
clk_int_val : out std_logic;
|
||||
clk90_int_val : out std_logic;
|
||||
sys_rst180_val : out std_logic;
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component icon
|
||||
port (
|
||||
CONTROL0 : inout std_logic_vector(35 downto 0);
|
||||
CONTROL1 : inout std_logic_vector(35 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ila
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
DATA : in std_logic_vector(57 downto 0);
|
||||
TRIG0 : in std_logic_vector(6 downto 0);
|
||||
CONTROL : inout std_logic_vector(35 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component vio
|
||||
port (
|
||||
CONTROL : inout std_logic_vector(35 downto 0);
|
||||
ASYNC_OUT: out std_logic_vector(11 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_noprune : boolean;
|
||||
attribute syn_black_box of icon : component is TRUE;
|
||||
attribute syn_noprune of icon : component is TRUE;
|
||||
attribute syn_black_box of ila : component is TRUE;
|
||||
attribute syn_noprune of ila : component is TRUE;
|
||||
attribute syn_black_box of vio : component is TRUE;
|
||||
attribute syn_noprune of vio : component is TRUE;
|
||||
|
||||
|
||||
|
||||
signal sys_rst : std_logic;
|
||||
signal wait_200us : std_logic;
|
||||
signal sys_rst90 : std_logic;
|
||||
signal sys_rst180 : std_logic;
|
||||
signal clk_0 : std_logic;
|
||||
signal clk90_0 : std_logic;
|
||||
signal delay_sel : std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
signal dbg_phase_cnt : std_logic_vector(4 downto 0);
|
||||
signal dbg_cnt : std_logic_vector(5 downto 0);
|
||||
signal dbg_trans_onedtct : std_logic;
|
||||
signal dbg_trans_twodtct : std_logic;
|
||||
signal dbg_enb_trans_two_dtct : std_logic;
|
||||
signal dbg_delay_sel : std_logic_vector(4 downto 0);
|
||||
signal dbg_rst_calib : std_logic;
|
||||
-- chipscope signals
|
||||
signal dbg_data : std_logic_vector(57 downto 0);
|
||||
signal dbg_trig : std_logic_vector(6 downto 0);
|
||||
signal control0 : std_logic_vector(35 downto 0);
|
||||
signal control1 : std_logic_vector(35 downto 0);
|
||||
signal vio_out_dqs : std_logic_vector(4 downto 0);
|
||||
signal vio_out_dqs_en : std_logic;
|
||||
signal vio_out_rst_dqs_div : std_logic_vector(4 downto 0);
|
||||
signal vio_out_rst_dqs_div_en : std_logic;
|
||||
signal vio_out : std_logic_vector(11 downto 0);
|
||||
signal sys_clkb : std_logic;
|
||||
signal sys_clk : std_logic;
|
||||
signal dbg_cmp_data : std_logic_vector(31 downto 0);
|
||||
signal dbg_test_bench : std_logic_vector(2 downto 0);
|
||||
signal dbg_controller : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
sys_clkb <= '0';
|
||||
sys_clk <= '0';
|
||||
|
||||
main_00 : vhdl_bl4_main_0
|
||||
port map (
|
||||
ddr2_dq => cntrl0_ddr2_dq,
|
||||
ddr2_a => cntrl0_ddr2_a,
|
||||
ddr2_ba => cntrl0_ddr2_ba,
|
||||
ddr2_cke => cntrl0_ddr2_cke,
|
||||
ddr2_cs_n => cntrl0_ddr2_cs_n,
|
||||
ddr2_ras_n => cntrl0_ddr2_ras_n,
|
||||
ddr2_cas_n => cntrl0_ddr2_cas_n,
|
||||
ddr2_we_n => cntrl0_ddr2_we_n,
|
||||
ddr2_odt => cntrl0_ddr2_odt,
|
||||
ddr2_dm => cntrl0_ddr2_dm,
|
||||
rst_dqs_div_in => cntrl0_rst_dqs_div_in,
|
||||
rst_dqs_div_out => cntrl0_rst_dqs_div_out,
|
||||
led_error_output1 => cntrl0_led_error_output1,
|
||||
data_valid_out => cntrl0_data_valid_out,
|
||||
init_done => cntrl0_init_done,
|
||||
ddr2_dqs => cntrl0_ddr2_dqs,
|
||||
ddr2_dqs_n => cntrl0_ddr2_dqs_n,
|
||||
ddr2_ck => cntrl0_ddr2_ck,
|
||||
ddr2_ck_n => cntrl0_ddr2_ck_n,
|
||||
wait_200us => wait_200us,
|
||||
delay_sel_val => delay_sel,
|
||||
clk_int => clk_0,
|
||||
clk90_int => clk90_0,
|
||||
sys_rst => sys_rst,
|
||||
sys_rst90 => sys_rst90,
|
||||
sys_rst180 => sys_rst180,
|
||||
|
||||
--Debug signals
|
||||
|
||||
dbg_delay_sel => dbg_delay_sel,
|
||||
dbg_rst_calib => dbg_rst_calib,
|
||||
dbg_controller => dbg_controller,
|
||||
dbg_cmp_data => dbg_cmp_data,
|
||||
dbg_test_bench => dbg_test_bench,
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
infrastructure_top0 : vhdl_bl4_infrastructure_top
|
||||
port map (
|
||||
wait_200us => wait_200us,
|
||||
delay_sel_val1_val => delay_sel,
|
||||
clk_int_val => clk_0,
|
||||
clk90_int_val => clk90_0,
|
||||
sys_rst_val => sys_rst,
|
||||
sys_rst90_val => sys_rst90,
|
||||
sys_rst180_val => sys_rst180,
|
||||
dbg_phase_cnt => dbg_phase_cnt,
|
||||
dbg_cnt => dbg_cnt,
|
||||
dbg_trans_onedtct => dbg_trans_onedtct,
|
||||
dbg_trans_twodtct => dbg_trans_twodtct,
|
||||
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct,
|
||||
sys_clkb => sys_clkb,
|
||||
sys_clk => sys_clk,
|
||||
sys_clk_in => sys_clk_in,
|
||||
reset_in_n => reset_in_n
|
||||
);
|
||||
|
||||
DEBUG_SIGNALS_INST : if (DEBUG_EN = 1) generate
|
||||
|
||||
dbg_data(57 downto 0) <= (dbg_controller & dbg_cmp_data & dbg_test_bench(2) & dbg_test_bench(1) &
|
||||
dbg_test_bench(0) &
|
||||
dbg_delay_sel & dbg_rst_calib &
|
||||
dbg_phase_cnt & dbg_cnt & dbg_trans_onedtct &
|
||||
dbg_trans_twodtct & dbg_enb_trans_two_dtct);
|
||||
|
||||
dbg_trig(6 downto 0) <= (dbg_test_bench(2) & dbg_test_bench(1) & dbg_test_bench(0) &
|
||||
dbg_rst_calib & dbg_trans_onedtct & dbg_trans_twodtct &
|
||||
dbg_enb_trans_two_dtct);
|
||||
|
||||
vio_out_rst_dqs_div_en <= vio_out(11);
|
||||
vio_out_rst_dqs_div <= vio_out(10 downto 6);
|
||||
vio_out_dqs_en <= vio_out(5);
|
||||
vio_out_dqs <= vio_out(4 downto 0);
|
||||
|
||||
|
||||
ILA_INST : ila
|
||||
port map (
|
||||
CONTROL => control0,
|
||||
CLK => clk_0,
|
||||
DATA => dbg_data,
|
||||
TRIG0 => dbg_trig
|
||||
);
|
||||
|
||||
ICON_INST : icon
|
||||
port map (
|
||||
CONTROL0 => control0,
|
||||
CONTROL1 => control1
|
||||
);
|
||||
|
||||
VIO_INST : vio
|
||||
port map (
|
||||
CONTROL => control1,
|
||||
ASYNC_OUT => vio_out
|
||||
);
|
||||
end generate DEBUG_SIGNALS_INST;
|
||||
|
||||
WITHOUT_DEBUG_SIGNALS_INST : if (DEBUG_EN /= 1) generate
|
||||
|
||||
dbg_data(57 downto 0) <= (others => '0');
|
||||
dbg_trig(6 downto 0) <= (others => '0');
|
||||
vio_out_rst_dqs_div_en <= '0';
|
||||
vio_out_rst_dqs_div <= (others => '0');
|
||||
vio_out_dqs_en <= '0';
|
||||
vio_out_dqs <= (others => '0');
|
||||
|
||||
end generate WITHOUT_DEBUG_SIGNALS_INST;
|
||||
|
||||
end arc_mem_interface_top;
|
||||
230
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_addr_gen_0.vhd
Executable file
230
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_addr_gen_0.vhd
Executable file
@@ -0,0 +1,230 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_addr_gen_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates address and burst done signals to the
|
||||
-- controller. Address consists of bank address at the lsb followed
|
||||
-- by column and row address. This module generates address depending
|
||||
-- on the addr_rst,addr_inc and r_w signals from the cmd_fsm module.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_addr_gen_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
addr_rst : in std_logic;
|
||||
addr_inc : in std_logic;
|
||||
r_w : in std_logic;
|
||||
addr_out : out std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS
|
||||
+ BANK_ADDRESS)- 1) downto 0);
|
||||
burst_done : out std_logic;
|
||||
cnt_roll : out std_logic);
|
||||
end vhdl_bl4_addr_gen_0;
|
||||
|
||||
architecture arc of vhdl_bl4_addr_gen_0 is
|
||||
|
||||
signal column_counter : std_logic_vector(7 downto 0);
|
||||
signal cnt : std_logic_vector(1 downto 0);
|
||||
signal cnt1 : std_logic_vector(1 downto 0);
|
||||
signal burst_cnt : std_logic_vector(2 downto 0);
|
||||
signal ba_count : std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
signal row_address1 : std_logic_vector(ROW_ADDRESS-1 downto 0);
|
||||
signal burst_done_r1 : std_logic;
|
||||
signal burst_done_r2 : std_logic;
|
||||
signal burst_done_r3 : std_logic;
|
||||
signal burst_done_r4 : std_logic;
|
||||
signal burst_done_r5 : std_logic;
|
||||
signal low : std_logic_vector(13 downto 0);
|
||||
signal rst180_r : std_logic;
|
||||
signal burst_len : std_logic_vector(2 downto 0);
|
||||
signal col_incr : std_logic_vector(3 downto 0);
|
||||
signal col_val : std_logic_vector(1 downto 0);
|
||||
signal lmr : std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
|
||||
attribute syn_keep : boolean;
|
||||
attribute syn_keep of low : signal is true;
|
||||
|
||||
begin
|
||||
lmr <= LOAD_MODE_REGISTER;
|
||||
low <= "00000000000000";
|
||||
burst_len <= lmr(2 downto 0);
|
||||
burst_done <= burst_done_r4 when (burst_len = "011") else
|
||||
burst_done_r2;
|
||||
cnt_roll <= burst_done_r3 when (burst_len = "011") else
|
||||
burst_done_r1;
|
||||
|
||||
col_incr <= "1000" when (burst_len = "011") else
|
||||
"0100" when (burst_len = "010") else
|
||||
"0000";
|
||||
col_val <= "11" when (burst_len = "011") else
|
||||
"01" when (burst_len = "010") else
|
||||
"00";
|
||||
addr_out <= (row_address1 & (low(COLUMN_ADDRESS -9 downto 0))
|
||||
& column_counter & ba_count);
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
rst180_r <= rst180;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--row address counter increments after every five writes and five reads
|
||||
process ( clk )
|
||||
begin
|
||||
if falling_edge(clk) then
|
||||
if(rst180_r = '1' or row_address1(5) = '1') then
|
||||
row_address1 <= low(ROW_ADDRESS-3 downto 0) & "10";
|
||||
elsif( r_w = '1' and burst_done_r4 = '0' and burst_done_r5 = '1') then
|
||||
row_address1 <= row_address1 + "10";
|
||||
else
|
||||
row_address1 <= row_address1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- bank address counter increments after every five writes and five reads
|
||||
-- commands
|
||||
process ( clk )
|
||||
begin
|
||||
if falling_edge(clk) then
|
||||
if(rst180_r = '1') then
|
||||
ba_count <= (others => '0');
|
||||
elsif( r_w = '1' and burst_done_r4 = '0' and burst_done_r5 = '1') then
|
||||
ba_count <= ba_count + '1';
|
||||
else
|
||||
ba_count <= ba_count;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if (rst180_r = '1' or addr_rst = '1') then
|
||||
cnt <= "00";
|
||||
elsif (addr_inc = '1' and cnt1 = "01") then
|
||||
if (cnt = col_val ) then
|
||||
cnt <= "00";
|
||||
else
|
||||
cnt <= cnt + '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- burst cnt to count number of the writes/reads ccommands
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if (rst180_r = '1' or addr_rst = '1') then
|
||||
burst_cnt <= "000";
|
||||
elsif (addr_inc = '1' and cnt = "00") then
|
||||
burst_cnt <= burst_cnt + '1';
|
||||
else
|
||||
burst_cnt <= burst_cnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- column address counter increments in multilple of 4,8 depending
|
||||
-- on the burst length 4 and 8 respectively
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if (rst180_r = '1' or addr_rst = '1') then
|
||||
column_counter <= "00000000";
|
||||
cnt1 <= "00";
|
||||
elsif(addr_inc = '1') then
|
||||
if(cnt1 = "00") then
|
||||
cnt1 <= cnt1 + '1';
|
||||
elsif(cnt1 = "01" and cnt = "00" and burst_cnt < "101") then
|
||||
column_counter <= column_counter + col_incr;
|
||||
else
|
||||
column_counter <= column_counter;
|
||||
end if;
|
||||
elsif(burst_done_r4 = '0' and burst_done_r5 = '1') then
|
||||
column_counter <= "00000000";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- burst done is generated after five writes/reads
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '0') then
|
||||
if (rst180_r = '1' ) then
|
||||
burst_done_r1 <= '0';
|
||||
elsif(burst_cnt = "101") then
|
||||
burst_done_r1 <= '1';
|
||||
else
|
||||
burst_done_r1 <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '0') then
|
||||
burst_done_r2 <= burst_done_r1;
|
||||
burst_done_r3 <= burst_done_r2;
|
||||
burst_done_r4 <= burst_done_r3;
|
||||
burst_done_r5 <= burst_done_r4;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd
Executable file
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd
Executable file
@@ -0,0 +1,255 @@
|
||||
--*****************************************************************************
|
||||
-- (c) Copyright 2005 - 2009 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cal_ctl.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates the select lines for the LUT delay
|
||||
-- circuit that generate the required delay for the DQS with
|
||||
-- respect to the DQ. It calculates the dealy of a LUT dynalically
|
||||
-- by finding the number of LUTs in a clock phase.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_cal_ctl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
flop2 : in std_logic_vector(31 downto 0);
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end vhdl_bl4_cal_ctl;
|
||||
|
||||
architecture arc_cal_ctl of vhdl_bl4_cal_ctl is
|
||||
|
||||
signal cnt : std_logic_vector(5 downto 0);
|
||||
signal cnt1 : std_logic_vector(5 downto 0);
|
||||
signal trans_onedtct : std_logic;
|
||||
signal trans_twodtct : std_logic;
|
||||
signal phase_cnt : std_logic_vector(4 downto 0);
|
||||
signal tap_dly_reg : std_logic_vector(31 downto 0);
|
||||
signal enb_trans_two_dtct : std_logic;
|
||||
signal tapfordqs_val : std_logic_vector(4 downto 0);
|
||||
signal cnt_val : integer;
|
||||
signal reset_r : std_logic;
|
||||
|
||||
constant tap1 : std_logic_vector(4 downto 0) := "01111";
|
||||
constant tap2 : std_logic_vector(4 downto 0) := "10111";
|
||||
constant tap3 : std_logic_vector(4 downto 0) := "11011";
|
||||
constant tap4 : std_logic_vector(4 downto 0) := "11101";
|
||||
constant tap5 : std_logic_vector(4 downto 0) := "11110";
|
||||
constant tap6 : std_logic_vector(4 downto 0) := "11111";
|
||||
constant default_tap : std_logic_vector(4 downto 0) := "11101";
|
||||
|
||||
attribute syn_keep : boolean;
|
||||
attribute syn_keep of cnt : signal is true;
|
||||
attribute syn_keep of cnt1 : signal is true;
|
||||
attribute syn_keep of trans_onedtct : signal is true;
|
||||
attribute syn_keep of trans_twodtct : signal is true;
|
||||
attribute syn_keep of tap_dly_reg : signal is true;
|
||||
attribute syn_keep of enb_trans_two_dtct : signal is true;
|
||||
attribute syn_keep of phase_cnt : signal is true;
|
||||
attribute syn_keep of tapfordqs_val : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
dbg_phase_cnt <= phase_cnt;
|
||||
dbg_cnt <= cnt1;
|
||||
dbg_trans_onedtct <= trans_onedtct;
|
||||
dbg_trans_twodtct <= trans_twodtct;
|
||||
dbg_enb_trans_two_dtct <= enb_trans_two_dtct;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
tapfordqs <= tapfordqs_val;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------For Successive Transition-------------------
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if (clk'event and clk = '1') then
|
||||
if(reset_r = '1') then
|
||||
enb_trans_two_dtct <= '0';
|
||||
elsif(phase_cnt >= "00001") then
|
||||
enb_trans_two_dtct <= '1';
|
||||
else
|
||||
enb_trans_two_dtct <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1') then
|
||||
tap_dly_reg <= "00000000000000000000000000000000";
|
||||
elsif(cnt(5) = '1') then
|
||||
tap_dly_reg <= flop2;
|
||||
else
|
||||
tap_dly_reg <= tap_dly_reg;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------Free Running Counter For Counting 32 States ----------------------
|
||||
------- Two parallel counters are used to fix the timing ------------------
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1' or cnt(5) = '1') then
|
||||
cnt(5 downto 0) <= "000000";
|
||||
else
|
||||
cnt(5 downto 0) <= cnt(5 downto 0) + "000001";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
if(reset_r = '1' or cnt1(5) = '1') then
|
||||
cnt1(5 downto 0) <= "000000";
|
||||
else
|
||||
cnt1(5 downto 0) <= cnt1(5 downto 0) + "000001";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if(reset_r = '1' or cnt(5) = '1') then
|
||||
phase_cnt <= "00000";
|
||||
elsif (trans_onedtct = '1' and trans_twodtct = '0') then
|
||||
phase_cnt <= phase_cnt + "00001";
|
||||
else
|
||||
phase_cnt <= phase_cnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------- Checking For The First Transition ------------------
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if (reset_r = '1' or cnt(5) = '1') then
|
||||
trans_onedtct <= '0';
|
||||
trans_twodtct <= '0';
|
||||
elsif (cnt(4 downto 0) = "00000" and tap_dly_reg(0) = '1') then
|
||||
trans_onedtct <= '1';
|
||||
trans_twodtct <= '0';
|
||||
elsif (tap_dly_reg(cnt_val) = '1' and trans_twodtct = '0') then
|
||||
if(trans_onedtct = '1' and enb_trans_two_dtct = '1') then
|
||||
trans_twodtct <= '1';
|
||||
else
|
||||
trans_onedtct <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_val <= conv_integer(cnt(4 downto 0));
|
||||
|
||||
-- Tap values for Left/Right banks
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if(reset_r = '1') then
|
||||
tapfordqs_val <= default_tap;
|
||||
elsif(cnt1(4) = '1' and cnt1(3) = '1' and cnt1(2) = '1' and cnt1(1) = '1'
|
||||
and cnt1(0) = '1') then
|
||||
if ((trans_onedtct = '0') or (trans_twodtct = '0')
|
||||
or (phase_cnt > "01100")) then
|
||||
tapfordqs_val <= tap6;
|
||||
elsif (phase_cnt > "01001") then
|
||||
tapfordqs_val <= tap4;
|
||||
elsif (phase_cnt > "00111") then
|
||||
tapfordqs_val <= tap3;
|
||||
elsif (phase_cnt > "00100") then
|
||||
tapfordqs_val <= tap2;
|
||||
else
|
||||
tapfordqs_val <= tap1;
|
||||
end if;
|
||||
else
|
||||
tapfordqs_val <= tapfordqs_val;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc_cal_ctl;
|
||||
134
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd
Executable file
134
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd
Executable file
@@ -0,0 +1,134 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cal_to.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations cal_ctl and tap_dly.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_cal_top is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk0dcmlock : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end vhdl_bl4_cal_top;
|
||||
|
||||
architecture arc of vhdl_bl4_cal_top is
|
||||
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
|
||||
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_3_ddr2_sp3, Coregen 11.4";
|
||||
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_3,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000}";
|
||||
|
||||
component vhdl_bl4_cal_ctl
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
flop2 : in std_logic_vector(31 downto 0);
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_tap_dly
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapin : in std_logic;
|
||||
flop2 : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal fpga_rst : std_logic;
|
||||
signal flop2_val : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
fpga_rst <= (not reset) or (not clk0dcmlock);
|
||||
|
||||
cal_ctl0 : vhdl_bl4_cal_ctl
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => fpga_rst,
|
||||
flop2 => flop2_val,
|
||||
tapfordqs => tapfordqs,
|
||||
dbg_phase_cnt => dbg_phase_cnt,
|
||||
dbg_cnt => dbg_cnt,
|
||||
dbg_trans_onedtct => dbg_trans_onedtct,
|
||||
dbg_trans_twodtct => dbg_trans_twodtct,
|
||||
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
|
||||
);
|
||||
|
||||
tap_dly0 : vhdl_bl4_tap_dly
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => fpga_rst,
|
||||
tapin => clk,
|
||||
flop2 => flop2_val
|
||||
);
|
||||
|
||||
end arc;
|
||||
127
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd
Executable file
127
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd
Executable file
@@ -0,0 +1,127 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_clk_dcm.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates the system clock for controller block
|
||||
-- This also generates the recapture clock, clock for the
|
||||
-- Refresh counter and also for the data path
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
entity vhdl_bl4_clk_dcm is
|
||||
port(
|
||||
input_clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
clk : out std_logic;
|
||||
clk90 : out std_logic;
|
||||
dcm_lock : out std_logic
|
||||
);
|
||||
end vhdl_bl4_clk_dcm;
|
||||
|
||||
architecture arc of vhdl_bl4_clk_dcm is
|
||||
|
||||
signal clk0dcm : std_logic;
|
||||
signal clk90dcm : std_logic;
|
||||
signal clk0_buf : std_logic;
|
||||
signal clk90_buf : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal dcm1_lock : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
clk <= clk0_buf;
|
||||
clk90 <= clk90_buf;
|
||||
|
||||
DCM_INST1 : DCM
|
||||
generic map(
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => true
|
||||
)
|
||||
port map (
|
||||
CLKIN => input_clk,
|
||||
CLKFB => clk0_buf,
|
||||
DSSEN => gnd,
|
||||
PSINCDEC => gnd,
|
||||
PSEN => gnd,
|
||||
PSCLK => gnd,
|
||||
RST => rst,
|
||||
CLK0 => clk0dcm,
|
||||
CLK90 => clk90dcm,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLKDV => open,
|
||||
CLKFX => open,
|
||||
CLKFX180 => open,
|
||||
LOCKED => dcm1_lock,
|
||||
PSDONE => open,
|
||||
STATUS => open
|
||||
);
|
||||
|
||||
BUFG_CLK0 : BUFG
|
||||
port map (
|
||||
O => clk0_buf,
|
||||
I => clk0dcm
|
||||
);
|
||||
|
||||
BUFG_CLK90 : BUFG
|
||||
port map (
|
||||
O => clk90_buf,
|
||||
I => clk90dcm
|
||||
);
|
||||
|
||||
dcm_lock <= dcm1_lock;
|
||||
|
||||
end arc;
|
||||
272
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmd_fsm_0.vhd
Executable file
272
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmd_fsm_0.vhd
Executable file
@@ -0,0 +1,272 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cmd_fsm_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module consists of s/m which will generate user commands
|
||||
-- like initialization, write and read.It also generates control
|
||||
-- signals addr_inc,addr_rst,data_rst for addr_gen and data_gen
|
||||
-- modules.This control signals are used to generate address
|
||||
-- during write and read commands and data for write command.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_cmd_fsm_0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
cmd_ack : in std_logic;
|
||||
cnt_roll : in std_logic;
|
||||
r_w : out std_logic;
|
||||
refresh_done : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
rst90 : in std_logic;
|
||||
init_val : in std_logic;
|
||||
addr_inc : out std_logic;
|
||||
addr_rst : out std_logic;
|
||||
u_cmd : out std_logic_vector(2 downto 0);
|
||||
data_rst : out std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_cmd_fsm_0;
|
||||
|
||||
architecture arc of vhdl_bl4_cmd_fsm_0 is
|
||||
|
||||
type s_m is (rst_state, init_start, init, wr, rd, dly);
|
||||
|
||||
signal next_state, next_state1 : s_m;
|
||||
|
||||
signal init_dly : std_logic_vector(5 downto 0);
|
||||
signal init_dly_p : std_logic_vector(5 downto 0);
|
||||
signal u_cmd_p : std_logic_vector(2 downto 0);
|
||||
signal addr_inc_p : std_logic;
|
||||
signal data_rst_p : std_logic;
|
||||
signal data_rst_180 : std_logic;
|
||||
signal data_rst_90 : std_logic;
|
||||
signal init_done : std_logic;
|
||||
signal next_cmd : std_logic;
|
||||
signal r_w1 : std_logic;
|
||||
signal r_w2 : std_logic;
|
||||
signal rst_flag : std_logic;
|
||||
signal temp : std_logic;
|
||||
signal rst180_r : std_logic;
|
||||
signal rst90_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
data_rst <= data_rst_90;
|
||||
u_cmd_p <= "110" when (next_state = rd) else "100"
|
||||
when (next_state = wr) else "010"
|
||||
when (next_state = init_start) else "000";
|
||||
addr_inc_p <= '1' when ((cmd_ack = '1') and (next_state = WR or
|
||||
next_state = RD)) else '0';
|
||||
addr_rst <= rst_flag;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '0') then
|
||||
rst180_r <= rst180;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if(clk90'event and clk90 = '1') then
|
||||
rst90_r <= rst90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '0') then
|
||||
rst_flag <= (not(rst180_r) and not(cmd_ack) and not(temp));
|
||||
temp <= (not(rst180_r) and not(cmd_ack));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_rst_p <= '1' when (r_w2 = '1') else '0';
|
||||
init_dly_p <= "111111" when (next_state = init_start) else
|
||||
init_dly - "000001" when init_dly /= "000000" else
|
||||
"000000";
|
||||
next_cmd <= '1' when (cmd_ack = '0' and next_state = dly) else '0';
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '0') then
|
||||
if(rst180_r = '1') then
|
||||
r_w1 <= '0';
|
||||
else
|
||||
if(cmd_ack = '0' and next_state = rd) then
|
||||
r_w1 <= '1';
|
||||
elsif(cmd_ack = '0' and next_state = wr) then
|
||||
r_w1 <= '0';
|
||||
else
|
||||
r_w1 <= r_w1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
r_w2 <= r_w1;
|
||||
r_w <= r_w1;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if rst180_r = '1' then
|
||||
data_rst_180 <= '0';
|
||||
else
|
||||
data_rst_180 <= data_rst_p;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if rst90_r = '1' then
|
||||
data_rst_90 <= '0';
|
||||
else
|
||||
data_rst_90 <= data_rst_180;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if rst180_r = '1' then
|
||||
u_cmd <= "000";
|
||||
else
|
||||
u_cmd <= u_cmd_p;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if rst180_r = '1' then
|
||||
addr_inc <= '0';
|
||||
init_dly <= "000000";
|
||||
else
|
||||
addr_inc <= addr_inc_p;
|
||||
init_dly <= init_dly_p;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if rst180_r = '1' then
|
||||
init_done <= '0';
|
||||
else
|
||||
init_done <= init_val;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- state machine to generate user commands
|
||||
process(rst180_r, cnt_roll, r_w2, refresh_done, init_done, next_cmd, next_state)
|
||||
begin
|
||||
if rst180_r = '1' then
|
||||
next_state1 <= rst_state;
|
||||
else
|
||||
case(next_state) is
|
||||
when rst_state =>
|
||||
next_state1 <= init_start;
|
||||
when init_start =>
|
||||
next_state1 <= init;
|
||||
when init =>
|
||||
if init_done = '1' then
|
||||
next_state1 <= wr;
|
||||
else
|
||||
next_state1 <= init;
|
||||
end if;
|
||||
when wr =>
|
||||
if cnt_roll = '0' then
|
||||
next_state1 <= wr;
|
||||
else
|
||||
next_state1 <= dly;
|
||||
end if;
|
||||
when dly =>
|
||||
if(next_cmd = '1' and r_w2 = '0') then
|
||||
next_state1 <= rd;
|
||||
elsif(next_cmd = '1' and r_w2 = '1') then
|
||||
next_state1 <= wr;
|
||||
else
|
||||
next_state1 <= dly;
|
||||
end if;
|
||||
when rd =>
|
||||
if cnt_roll = '0' then
|
||||
next_state1 <= rd;
|
||||
else
|
||||
next_state1 <= dly;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk = '0' then
|
||||
if rst180_r = '1' then
|
||||
next_state <= rst_state;
|
||||
else
|
||||
next_state <= next_state1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
176
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmp_data_0.vhd
Executable file
176
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cmp_data_0.vhd
Executable file
@@ -0,0 +1,176 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_cmp_data_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module compare the read data with compare data and
|
||||
-- generates the error signal in case of data mismatch.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_cmp_data_0 is
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
data_valid : in std_logic;
|
||||
cmp_data : in std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
read_data : in std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
rst90 : in std_logic;
|
||||
led_error_output : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
dbg_cmp_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
dbg_led_error_output : out std_logic;
|
||||
dbg_data_valid_out : out std_logic
|
||||
);
|
||||
end vhdl_bl4_cmp_data_0;
|
||||
|
||||
architecture arc of vhdl_bl4_cmp_data_0 is
|
||||
|
||||
signal led_state : std_logic;
|
||||
signal error : std_logic;
|
||||
signal byte_err_fall : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
|
||||
signal byte_err_rise : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
|
||||
signal valid : std_logic;
|
||||
signal val_reg : std_logic;
|
||||
signal read_data_reg : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal rst90_r : std_logic;
|
||||
signal led_error_output1 : std_logic;
|
||||
|
||||
begin
|
||||
dbg_data_valid_out <= valid;
|
||||
dbg_led_error_output <= led_error_output1;
|
||||
dbg_cmp_data <= read_data_reg;
|
||||
|
||||
data_valid_out <= valid;
|
||||
led_error_output1 <= '1' when (led_state = '1') else '0';
|
||||
led_error_output <= led_error_output1;
|
||||
error <= ((byte_err_fall(0) or byte_err_fall(1)) or (byte_err_rise(0) or byte_err_rise(1))) and val_reg;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
rst90_r <= rst90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
read_data_reg <= read_data;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if rst90_r = '1' then
|
||||
valid <= '0';
|
||||
else
|
||||
valid <= data_valid;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if (rst90_r = '1') then
|
||||
val_reg <= '0';
|
||||
else
|
||||
val_reg <= valid;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
gen_err : for err_i in 0 to (DATA_WIDTH/8)-1 generate
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if (read_data_reg((err_i*8-1)+8 downto err_i*8) /=
|
||||
cmp_data((err_i*8-1)+8 downto err_i*8)) then
|
||||
byte_err_fall(err_i) <= '1';
|
||||
else
|
||||
byte_err_fall(err_i) <= '0';
|
||||
end if;
|
||||
if (read_data_reg(((err_i*8)+DATA_WIDTH-1)+8 downto ((err_i*8)+DATA_WIDTH)) /=
|
||||
cmp_data(((err_i*8)+DATA_WIDTH-1)+8 downto ((err_i*8)+DATA_WIDTH))) then
|
||||
byte_err_rise(err_i) <= '1';
|
||||
else
|
||||
byte_err_rise(err_i) <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate gen_err;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
led_state <= (not rst90_r and ( error or led_state));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- DATA ERROR
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if (rst90_r = '0') then
|
||||
--synthesis translate_off
|
||||
assert (led_state = '0') report " DATA ERROR at time " & time'image(now);
|
||||
--synthesis translate_on
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end arc;
|
||||
1382
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd
Executable file
1382
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd
Executable file
File diff suppressed because it is too large
Load Diff
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd
Executable file
255
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd
Executable file
@@ -0,0 +1,255 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_controller_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the IOB instantiations to address and control
|
||||
-- signals.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_controller_iobs_0 is
|
||||
port(
|
||||
clk0 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
rst_dqs_div_int : in std_logic;
|
||||
ddr_odt : out std_logic;
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic
|
||||
);
|
||||
end vhdl_bl4_controller_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_controller_iobs_0 is
|
||||
|
||||
signal ddr_web_q : std_logic;
|
||||
signal ddr_rasb_q : std_logic;
|
||||
signal ddr_casb_q : std_logic;
|
||||
signal ddr_cke_q : std_logic;
|
||||
signal ddr_cke_int : std_logic;
|
||||
signal ddr_address_reg : std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
signal ddr_ba_reg : std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
signal ddr_odt_reg : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
attribute iob : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute iob of iob_rasb : label is "FORCE";
|
||||
attribute iob of iob_casb : label is "FORCE";
|
||||
attribute iob of iob_web : label is "FORCE";
|
||||
attribute iob of iob_cke : label is "FORCE";
|
||||
attribute iob of iob_odt : label is "FORCE";
|
||||
attribute syn_useioff of iob_rasb : label is true;
|
||||
attribute syn_useioff of iob_casb : label is true;
|
||||
attribute syn_useioff of iob_web : label is true;
|
||||
attribute syn_useioff of iob_cke : label is true;
|
||||
attribute syn_useioff of iob_odt : label is true;
|
||||
|
||||
begin
|
||||
|
||||
clk180 <= not clk0;
|
||||
|
||||
---- ******************************************* ----
|
||||
---- Includes the instantiation of FD for cntrl ----
|
||||
---- signals ----
|
||||
---- ******************************************* ----
|
||||
|
||||
iob_web : FD
|
||||
port map (
|
||||
Q => ddr_web_q,
|
||||
D => ddr_web_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
iob_rasb : FD
|
||||
port map (
|
||||
Q => ddr_rasb_q,
|
||||
D => ddr_rasb_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
iob_casb : FD
|
||||
port map (
|
||||
Q => ddr_casb_q,
|
||||
D => ddr_casb_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
---- ************************************* ----
|
||||
---- Output buffers for control signals ----
|
||||
---- ************************************* ----
|
||||
|
||||
r16 : OBUF
|
||||
port map (
|
||||
I => ddr_web_q,
|
||||
O => ddr_web
|
||||
);
|
||||
|
||||
r17 : OBUF
|
||||
port map (
|
||||
I => ddr_rasb_q,
|
||||
O => ddr_rasb
|
||||
);
|
||||
|
||||
r18 : OBUF
|
||||
port map (
|
||||
I => ddr_casb_q,
|
||||
O => ddr_casb
|
||||
);
|
||||
|
||||
r19 : OBUF
|
||||
port map (
|
||||
I => ddr_csb_cntrl,
|
||||
O => ddr_csb
|
||||
);
|
||||
|
||||
iob_cke1 : FD
|
||||
port map(
|
||||
Q => ddr_cke_int,
|
||||
D => ddr_cke_cntrl,
|
||||
C => clk0
|
||||
);
|
||||
|
||||
iob_cke : FD
|
||||
port map(
|
||||
Q => ddr_cke_q,
|
||||
D => ddr_cke_int,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
r20 : OBUF
|
||||
port map (
|
||||
I => ddr_cke_q,
|
||||
O => ddr_cke
|
||||
);
|
||||
|
||||
iob_odt : FD
|
||||
port map (
|
||||
Q => ddr_ODT_reg,
|
||||
D => ddr_ODT_cntrl,
|
||||
C => clk180
|
||||
);
|
||||
|
||||
ODT_iob_obuf : OBUF
|
||||
port map (
|
||||
I => ddr_ODT_reg,
|
||||
O => ddr_ODT
|
||||
);
|
||||
|
||||
---- ******************************************* ----
|
||||
---- Includes the instantiation of FD and OBUF ----
|
||||
---- for row address and bank address ----
|
||||
---- ******************************************* ----
|
||||
|
||||
gen_addr : for i in (ROW_ADDRESS -1) downto 0 generate
|
||||
attribute IOB of iob_addr : label is "FORCE";
|
||||
attribute syn_useioff of iob_addr : label is true;
|
||||
begin
|
||||
iob_addr : FD
|
||||
port map (
|
||||
Q => ddr_address_reg(i),
|
||||
D => ddr_address_cntrl(i),
|
||||
C => clk180
|
||||
);
|
||||
r : OBUF
|
||||
port map (
|
||||
I => ddr_address_reg(i),
|
||||
O => ddr_address(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
gen_ba : for i in (BANK_ADDRESS -1) downto 0 generate
|
||||
attribute IOB of iob_ba : label is "FORCE";
|
||||
attribute syn_useioff of iob_ba : label is true;
|
||||
begin
|
||||
iob_ba : FD
|
||||
port map (
|
||||
Q => ddr_ba_reg(i),
|
||||
D => ddr_ba_cntrl(i),
|
||||
C => clk180
|
||||
);
|
||||
r : OBUF
|
||||
port map (
|
||||
I => ddr_ba_reg(i),
|
||||
O => ddr_ba(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
rst_iob_inbuf : IBUF
|
||||
port map(
|
||||
I => rst_dqs_div_in,
|
||||
O => rst_dqs_div
|
||||
);
|
||||
|
||||
rst_iob_outbuf : OBUF
|
||||
port map (
|
||||
I => rst_dqs_div_int,
|
||||
O => rst_dqs_div_out
|
||||
);
|
||||
|
||||
end arc;
|
||||
122
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_gen_0.vhd
Executable file
122
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_gen_0.vhd
Executable file
@@ -0,0 +1,122 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_gen_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate write data during the write command
|
||||
-- and compare data during read command. For write command,
|
||||
-- mask data is also generated. Mask data is tied to low.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use IEEE.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_gen_0 is
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
rst90 : in std_logic;
|
||||
data_rst : in std_logic;
|
||||
data_ena : in std_logic;
|
||||
mask_data : out std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
data_out : out std_logic_vector((2*DATA_WIDTH-1) downto 0));
|
||||
end vhdl_bl4_data_gen_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_gen_0 is
|
||||
|
||||
signal rise_data : std_logic_vector(7 downto 0);
|
||||
signal fall_data : std_logic_vector(7 downto 0);
|
||||
signal rst90_r : std_logic;
|
||||
|
||||
signal rise_data_xnor : std_logic;
|
||||
signal rise_data1 : std_logic_vector(7 downto 0);
|
||||
constant PATTERN : std_logic_vector(7 downto 0) := "10010110"; -- 96
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of rise_data : signal is true;
|
||||
attribute syn_preserve of fall_data : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if rising_edge(clk90) then
|
||||
rst90_r <= rst90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
rise_data_xnor <= rise_data(7) xnor rise_data(5);
|
||||
rise_data1 <= (rise_data(6 downto 0) & rise_data_xnor);
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if rising_edge(clk90) then
|
||||
if (rst90_r = '1') then
|
||||
rise_data <= PATTERN;
|
||||
fall_data <= not PATTERN;
|
||||
else
|
||||
if data_rst = '1' then
|
||||
rise_data <= PATTERN;
|
||||
fall_data <= not PATTERN;
|
||||
elsif data_ena = '1' then
|
||||
rise_data <= rise_data1;
|
||||
fall_data <= not rise_data1;
|
||||
else
|
||||
rise_data <= rise_data;
|
||||
fall_data <= fall_data;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_out <= rise_data & rise_data & fall_data & fall_data ;
|
||||
|
||||
mask_data <= (others => '0');
|
||||
|
||||
end arc;
|
||||
210
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd
Executable file
210
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd
Executable file
@@ -0,0 +1,210 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_path_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the write and read data paths for the
|
||||
-- DDR2 memory interface. The write data along with write enable
|
||||
-- signals are forwarded to the DDR IOB FFs. The read data is
|
||||
-- captured in CLB FFs and finally input to FIFOs.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_path_0 is
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
reset : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic; -- Added new signal
|
||||
-- debug signals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end vhdl_bl4_data_path_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_path_0 is
|
||||
|
||||
component vhdl_bl4_data_read_0
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
u_data_val : out std_logic
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_read_controller_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_write_0
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal read_valid_data_1 : std_logic;
|
||||
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col1 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
begin
|
||||
|
||||
data_read0 : vhdl_bl4_data_read_0
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
ddr_dq_in => dq,
|
||||
fifo_0_wr_en => fifo_0_wr_en,
|
||||
fifo_1_wr_en => fifo_1_wr_en,
|
||||
fifo_0_wr_addr => fifo_0_wr_addr,
|
||||
fifo_1_wr_addr => fifo_1_wr_addr,
|
||||
dqs_delayed_col0 => dqs_delayed_col0,
|
||||
dqs_delayed_col1 => dqs_delayed_col1,
|
||||
read_fifo_rden => read_fifo_rden,
|
||||
user_output_data => user_output_data,
|
||||
u_data_val => u_data_val
|
||||
);
|
||||
|
||||
data_read_controller0 : vhdl_bl4_data_read_controller_0
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
delay_sel => delay_sel,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
fifo_0_wr_en_val => fifo_0_wr_en,
|
||||
fifo_1_wr_en_val => fifo_1_wr_en,
|
||||
fifo_0_wr_addr_val => fifo_0_wr_addr,
|
||||
fifo_1_wr_addr_val => fifo_1_wr_addr,
|
||||
dqs_delayed_col0_val => dqs_delayed_col0,
|
||||
dqs_delayed_col1_val => dqs_delayed_col1,
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
data_write0 : vhdl_bl4_data_write_0
|
||||
port map (
|
||||
user_input_data => user_input_data,
|
||||
user_data_mask => user_data_mask,
|
||||
clk90 => clk90,
|
||||
write_enable => write_enable,
|
||||
write_en_val => write_en_val,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r
|
||||
);
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
173
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd
Executable file
173
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd
Executable file
@@ -0,0 +1,173 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_parameters_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations s3_dq_iob, s3_dqs_iob and
|
||||
-- s3_dm_iob modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_path_iobs_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_data_path_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_path_iobs_0 is
|
||||
|
||||
component vhdl_bl4_s3_dqs_iob
|
||||
port(
|
||||
clk : in std_logic;
|
||||
ddr_dqs_reset : in std_logic;
|
||||
ddr_dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic;
|
||||
ddr_dqs_n : inout std_logic;
|
||||
dqs : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_s3_dq_iob
|
||||
port (
|
||||
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
|
||||
write_data_falling : in std_logic; --Transmit data, output on falling edge
|
||||
write_data_rising : in std_logic; --Transmit data, output on rising edge
|
||||
read_data_in : out std_logic; -- Received data
|
||||
clk90 : in std_logic;
|
||||
write_en_val : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_s3_dm_iob
|
||||
port (
|
||||
ddr_dm : out std_logic;
|
||||
mask_falling : in std_logic;
|
||||
mask_rising : in std_logic;
|
||||
clk90 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal ddr_dq_in : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
|
||||
begin
|
||||
|
||||
ddr_dq_val <= ddr_dq_in;
|
||||
|
||||
--***********************************************************************
|
||||
-- DM IOB instantiations
|
||||
--***********************************************************************
|
||||
MASK_INST : if(MASK_ENABLE = 1) generate
|
||||
begin
|
||||
gen_dm: for dm_i in 0 to DATA_MASK_WIDTH-1 generate
|
||||
s3_dm_iob_inst : vhdl_bl4_s3_dm_iob
|
||||
port map (
|
||||
ddr_dm => ddr_dm(dm_i),
|
||||
mask_falling => data_mask_f(dm_i),
|
||||
mask_rising => data_mask_r(dm_i),
|
||||
clk90 => clk90
|
||||
);
|
||||
end generate;
|
||||
end generate MASK_INST;
|
||||
|
||||
--***********************************************************************
|
||||
-- Read Data Capture Module Instantiations
|
||||
--***********************************************************************
|
||||
-- DQS IOB instantiations
|
||||
--***********************************************************************
|
||||
|
||||
gen_dqs: for dqs_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
s3_dqs_iob_inst : vhdl_bl4_s3_dqs_iob
|
||||
port map (
|
||||
clk => clk,
|
||||
ddr_dqs_reset => dqs_reset,
|
||||
ddr_dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr_dqs(dqs_i),
|
||||
ddr_dqs_n => ddr_dqs_n(dqs_i),
|
||||
dqs => dqs_int_delay_in(dqs_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
--******************************************************************************
|
||||
-- DDR Data bit instantiations
|
||||
--******************************************************************************
|
||||
|
||||
gen_dq: for dq_i in 0 to DATA_WIDTH-1 generate
|
||||
s3_dq_iob_inst : vhdl_bl4_s3_dq_iob
|
||||
port map (
|
||||
ddr_dq_inout => ddr_dq(dq_i),
|
||||
write_data_falling => write_data_falling(dq_i),
|
||||
write_data_rising => write_data_rising(dq_i),
|
||||
read_data_in => ddr_dq_in(dq_i),
|
||||
clk90 => clk90,
|
||||
write_en_val => write_en_val
|
||||
);
|
||||
end generate;
|
||||
|
||||
end arc;
|
||||
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd
Executable file
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd
Executable file
@@ -0,0 +1,274 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_read_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : ram8d modules are instantiated for Read data FIFOs. ram8d is
|
||||
-- each 8 bits or 4 bits depending on number data bits per strobe.
|
||||
-- Each strobe will have two instances, one for rising edge data
|
||||
-- and one for falling edge data.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_read_0 is
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic;
|
||||
user_output_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic
|
||||
);
|
||||
end vhdl_bl4_data_read_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_read_0 is
|
||||
|
||||
component vhdl_bl4_rd_gray_cntr
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
rgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_ram8d_0 is
|
||||
port (
|
||||
DOUT : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
WADDR : in std_logic_vector(3 downto 0);
|
||||
DIN : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
RADDR : in std_logic_vector(3 downto 0);
|
||||
WCLK0 : in std_logic;
|
||||
WCLK1 : in std_logic;
|
||||
WE : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_ram8d_1 is
|
||||
port (
|
||||
DOUT : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
WADDR : in std_logic_vector(3 downto 0);
|
||||
DIN : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
RADDR : in std_logic_vector(3 downto 0);
|
||||
WCLK0 : in std_logic;
|
||||
WCLK1 : in std_logic;
|
||||
WE : in std_logic
|
||||
);
|
||||
end component;
|
||||
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
|
||||
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
|
||||
|
||||
signal first_sdr_data : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal reset90_r : std_logic;
|
||||
signal fifo0_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo1_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_0_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_1_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_0_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal fifo_1_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
|
||||
signal read_fifo_rden_90r1 : std_logic;
|
||||
signal read_fifo_rden_90r2 : std_logic;
|
||||
signal read_fifo_rden_90r3 : std_logic;
|
||||
signal read_fifo_rden_90r4 : std_logic;
|
||||
signal read_fifo_rden_90r5 : std_logic;
|
||||
signal read_fifo_rden_90r6 : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of fifo0_rd_addr_r : signal is true;
|
||||
attribute syn_preserve of fifo1_rd_addr_r : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if(clk90'event and clk90='1') then
|
||||
reset90_r <= reset90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
|
||||
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
|
||||
end generate;
|
||||
|
||||
user_output_data <= first_sdr_data;
|
||||
u_data_val <= read_fifo_rden_90r6;
|
||||
|
||||
-- Read fifo read enable signal phase is changed from 180 to 90 clock domain
|
||||
|
||||
process (clk90)
|
||||
begin
|
||||
if (rising_edge(clk90)) then
|
||||
if reset90_r = '1' then
|
||||
read_fifo_rden_90r1 <= '0';
|
||||
read_fifo_rden_90r2 <= '0';
|
||||
read_fifo_rden_90r3 <= '0';
|
||||
read_fifo_rden_90r4 <= '0';
|
||||
read_fifo_rden_90r5 <= '0';
|
||||
read_fifo_rden_90r6<= '0';
|
||||
else
|
||||
read_fifo_rden_90r1 <= read_fifo_rden;
|
||||
read_fifo_rden_90r2 <= read_fifo_rden_90r1;
|
||||
read_fifo_rden_90r3 <= read_fifo_rden_90r2;
|
||||
read_fifo_rden_90r4 <= read_fifo_rden_90r3;
|
||||
read_fifo_rden_90r5 <= read_fifo_rden_90r4;
|
||||
read_fifo_rden_90r6 <= read_fifo_rden_90r5;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
fifo_0_data_out_r <= fifo_0_data_out;
|
||||
fifo_1_data_out_r <= fifo_1_data_out;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_addr : for addr_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
fifo0_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo0_rd_addr;
|
||||
fifo1_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo1_rd_addr;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if reset90_r = '1' then
|
||||
first_sdr_data <= (others => '0');
|
||||
elsif (read_fifo_rden_90r5 = '1') then
|
||||
first_sdr_data <= (fifo_0_data_out_r & fifo_1_data_out_r);
|
||||
else
|
||||
first_sdr_data <= first_sdr_data;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- fifo0_rd_addr and fifo1_rd_addr counters ( gray counters )
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
fifo0_rd_addr_inst : vhdl_bl4_rd_gray_cntr
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
cnt_en => read_fifo_rden_90r3,
|
||||
rgc_gcnt => fifo0_rd_addr
|
||||
);
|
||||
fifo1_rd_addr_inst : vhdl_bl4_rd_gray_cntr
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
reset90 => reset90,
|
||||
cnt_en => read_fifo_rden_90r3,
|
||||
rgc_gcnt => fifo1_rd_addr
|
||||
);
|
||||
|
||||
strobe0 : vhdl_bl4_ram8d_0
|
||||
Port Map (
|
||||
DOUT => fifo_0_data_out(7 downto 0),
|
||||
WADDR => fifo_0_wr_addr(3 downto 0),
|
||||
DIN => ddr_dq_in(7 downto 0),
|
||||
RADDR => fifo0_rd_addr_r(3 downto 0),
|
||||
WCLK0 => dqs_delayed_col0(0),
|
||||
WCLK1 => dqs_delayed_col1(0),
|
||||
WE => fifo_0_wr_en(0)
|
||||
);
|
||||
strobe0_n : vhdl_bl4_ram8d_0
|
||||
Port Map (
|
||||
DOUT => fifo_1_data_out(7 downto 0),
|
||||
WADDR => fifo_1_wr_addr(3 downto 0),
|
||||
DIN => ddr_dq_in(7 downto 0),
|
||||
RADDR => fifo1_rd_addr_r(3 downto 0),
|
||||
WCLK0 => dqs_delayed_col0_n(0),
|
||||
WCLK1 => dqs_delayed_col1_n(0),
|
||||
WE => fifo_1_wr_en(0)
|
||||
);
|
||||
|
||||
strobe1 : vhdl_bl4_ram8d_1
|
||||
Port Map (
|
||||
DOUT => fifo_0_data_out(15 downto 8),
|
||||
WADDR => fifo_0_wr_addr(7 downto 4),
|
||||
DIN => ddr_dq_in(15 downto 8),
|
||||
RADDR => fifo0_rd_addr_r(7 downto 4),
|
||||
WCLK0 => dqs_delayed_col0(1),
|
||||
WCLK1 => dqs_delayed_col1(1),
|
||||
WE => fifo_0_wr_en(1)
|
||||
);
|
||||
strobe1_n : vhdl_bl4_ram8d_1
|
||||
Port Map (
|
||||
DOUT => fifo_1_data_out(15 downto 8),
|
||||
WADDR => fifo_1_wr_addr(7 downto 4),
|
||||
DIN => ddr_dq_in(15 downto 8),
|
||||
RADDR => fifo1_rd_addr_r(7 downto 4),
|
||||
WCLK0 => dqs_delayed_col0_n(1),
|
||||
WCLK1 => dqs_delayed_col1_n(1),
|
||||
WE => fifo_1_wr_en(1)
|
||||
);
|
||||
|
||||
|
||||
end arc;
|
||||
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd
Executable file
274
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd
Executable file
@@ -0,0 +1,274 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_read_controller_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Description : This module has instantiations fifo_0_wr_en, fifo_1_wr_en,
|
||||
-- dqs_delay and wr_gray_cntr.
|
||||
--*****************************************************************************
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_read_controller_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
-- debug signals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en: in std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_data_read_controller_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_read_controller_0 is
|
||||
|
||||
component vhdl_bl4_dqs_delay
|
||||
port (
|
||||
clk_in : in std_logic;
|
||||
sel_in : in std_logic_vector(4 downto 0);
|
||||
clk_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- wr_gray_cntr is a gray counter with an ASYNC reset for fifo wr_addr
|
||||
|
||||
component vhdl_bl4_wr_gray_cntr
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
wgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
-- fifo_wr_en module generates fifo write enable signal
|
||||
-- enable is derived from rst_dqs_div signal
|
||||
|
||||
component vhdl_bl4_fifo_0_wr_en_0
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
rst_dqs_delay_n : out std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_fifo_1_wr_en_0
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_dqs_delay_n : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal dqs_delayed_col0 : std_logic_vector((data_strobe_width-1) downto 0);
|
||||
signal dqs_delayed_col1 : std_logic_vector((data_strobe_width-1) downto 0);
|
||||
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
|
||||
|
||||
-- FIFO WRITE ENABLE SIGNALS
|
||||
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
|
||||
signal rst_dqs_div : std_logic;
|
||||
signal reset_r : std_logic;
|
||||
signal rst_dqs_delay_0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal delay_sel_rst_dqs_div : std_logic_vector(4 downto 0);
|
||||
signal delay_sel_dqs : std_logic_vector(4 downto 0);
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
attribute buffer_type : string;
|
||||
attribute buffer_type of dqs_delayed_col0: signal is "none";
|
||||
attribute buffer_type of dqs_delayed_col1: signal is "none";
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk = '1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
fifo_0_wr_addr_val <= fifo_0_wr_addr;
|
||||
fifo_1_wr_addr_val <= fifo_1_wr_addr;
|
||||
fifo_0_wr_en_val <= fifo_0_wr_en;
|
||||
fifo_1_wr_en_val <= fifo_1_wr_en;
|
||||
dqs_delayed_col0_val <= dqs_delayed_col0 ;
|
||||
dqs_delayed_col1_val <= dqs_delayed_col1 ;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
|
||||
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
|
||||
debug_rst_dqs_div_ena : if (DEBUG_EN = 1) generate
|
||||
delay_sel_rst_dqs_div <= vio_out_rst_dqs_div(4 downto 0) when (vio_out_rst_dqs_div_en = '1')
|
||||
else delay_sel;
|
||||
end generate;
|
||||
|
||||
debug_rst_dqs_div_dis : if (DEBUG_EN = 0) generate
|
||||
delay_sel_rst_dqs_div <= delay_sel;
|
||||
end generate;
|
||||
|
||||
|
||||
-- delayed rst_dqs_div logic
|
||||
|
||||
rst_dqs_div_delayed : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => rst_dqs_div_in,
|
||||
sel_in => delay_sel_rst_dqs_div,
|
||||
clk_out => rst_dqs_div
|
||||
);
|
||||
|
||||
|
||||
debug_ena : if (DEBUG_EN = 1) generate
|
||||
delay_sel_dqs <= vio_out_dqs(4 downto 0) when (vio_out_dqs_en = '1')
|
||||
else delay_sel;
|
||||
end generate;
|
||||
|
||||
debug_dis : if (DEBUG_EN = 0) generate
|
||||
delay_sel_dqs <= delay_sel;
|
||||
end generate;
|
||||
|
||||
|
||||
--******************************************************************************
|
||||
-- DQS Internal Delay Circuit implemented in LUTs
|
||||
--******************************************************************************
|
||||
gen_delay: for dly_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
attribute syn_preserve of dqs_delay_col0: label is true;
|
||||
attribute syn_preserve of dqs_delay_col1: label is true;
|
||||
begin
|
||||
-- Internal Clock Delay circuit placed in the first
|
||||
-- column (for falling edge data) adjacent to IOBs
|
||||
dqs_delay_col0 : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => dqs_int_delay_in(dly_i),
|
||||
sel_in => delay_sel_dqs,
|
||||
clk_out => dqs_delayed_col0(dly_i)
|
||||
);
|
||||
-- Internal Clock Delay circuit placed in the second
|
||||
--column (for rising edge data) adjacent to IOBs
|
||||
dqs_delay_col1 : vhdl_bl4_dqs_delay
|
||||
port map (
|
||||
clk_in => dqs_int_delay_in(dly_i),
|
||||
sel_in => delay_sel_dqs,
|
||||
clk_out => dqs_delayed_col1(dly_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
gen_wr_en: for wr_en_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
fifo_0_wr_en_inst: vhdl_bl4_fifo_0_wr_en_0
|
||||
port map (
|
||||
clk => dqs_delayed_col1_n (wr_en_i),
|
||||
reset => reset_r,
|
||||
din => rst_dqs_div,
|
||||
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
|
||||
dout => fifo_0_wr_en(wr_en_i)
|
||||
);
|
||||
fifo_1_wr_en_inst: vhdl_bl4_fifo_1_wr_en_0
|
||||
port map (
|
||||
clk => dqs_delayed_col0(wr_en_i),
|
||||
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
|
||||
reset => reset_r,
|
||||
din => rst_dqs_div,
|
||||
dout => fifo_1_wr_en(wr_en_i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- write pointer gray counter instances
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
gen_wr_addr: for wr_addr_i in 0 to DATA_STROBE_WIDTH-1 generate
|
||||
fifo_0_wr_addr_inst : vhdl_bl4_wr_gray_cntr
|
||||
port map (
|
||||
clk => dqs_delayed_col1(wr_addr_i),
|
||||
reset => reset_r,
|
||||
cnt_en => fifo_0_wr_en(wr_addr_i),
|
||||
wgc_gcnt => fifo_0_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
|
||||
);
|
||||
fifo_1_wr_addr_inst : vhdl_bl4_wr_gray_cntr
|
||||
port map (
|
||||
clk => dqs_delayed_col0_n(wr_addr_i),
|
||||
reset => reset_r,
|
||||
cnt_en => fifo_1_wr_en(wr_addr_i),
|
||||
wgc_gcnt => fifo_1_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
|
||||
);
|
||||
end generate;
|
||||
|
||||
end arc;
|
||||
196
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd
Executable file
196
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd
Executable file
@@ -0,0 +1,196 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_data_write0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : Data write operation performed through the pipelines in this
|
||||
-- module.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_data_write_0 is
|
||||
port(
|
||||
user_input_data : in std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
clk90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_data_write_0;
|
||||
|
||||
architecture arc of vhdl_bl4_data_write_0 is
|
||||
|
||||
|
||||
signal write_en_P1 : std_logic; -- write enable Pipeline stage
|
||||
signal write_data0 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data1 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data2 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data3 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data4 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
signal write_data_m0 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m1 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m2 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m3 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m4 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data90 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data90_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data90_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data_m90 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m90_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m90_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data270 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data270_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data270_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
|
||||
signal write_data_m270 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m270_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_m270_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
attribute syn_preserve of write_data0 : signal is true;
|
||||
attribute syn_preserve of write_data1 : signal is true;
|
||||
attribute syn_preserve of write_data2 : signal is true;
|
||||
attribute syn_preserve of write_data3 : signal is true;
|
||||
attribute syn_preserve of write_data4 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data_m0 : signal is true;
|
||||
attribute syn_preserve of write_data_m1 : signal is true;
|
||||
attribute syn_preserve of write_data_m2 : signal is true;
|
||||
attribute syn_preserve of write_data_m3 : signal is true;
|
||||
attribute syn_preserve of write_data_m4 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data90 : signal is true;
|
||||
attribute syn_preserve of write_data90_1 : signal is true;
|
||||
attribute syn_preserve of write_data90_2 : signal is true;
|
||||
|
||||
attribute syn_preserve of write_data270 : signal is true;
|
||||
attribute syn_preserve of write_data270_1 : signal is true;
|
||||
attribute syn_preserve of write_data270_2 : signal is true;
|
||||
|
||||
begin
|
||||
|
||||
write_data0 <= user_input_data;
|
||||
write_data_m0 <= user_data_mask;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_data1 <= write_data0;
|
||||
write_data_m1 <= write_data_m0;
|
||||
write_data2 <= write_data1;
|
||||
write_data_m2 <= write_data_m1;
|
||||
write_data3 <= write_data2;
|
||||
write_data_m3 <= write_data_m2;
|
||||
write_data4 <= write_data3;
|
||||
write_data_m4 <= write_data_m3;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_data90 <= write_data4((DATA_WIDTH-1) downto 0);
|
||||
write_data_m90 <= write_data_m4((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data90_1 <= write_data90;
|
||||
write_data_m90_1 <= write_data_m90;
|
||||
write_data90_2 <= write_data90_1;
|
||||
write_data_m90_2 <= write_data_m90_1;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '0' then
|
||||
write_data270 <= write_data4((DATA_WIDTH*2-1) downto DATA_WIDTH);
|
||||
write_data_m270 <= write_data_m4((DATA_MASK_WIDTH*2-1) downto DATA_MASK_WIDTH);
|
||||
write_data270_1 <= write_data270;
|
||||
write_data270_2 <= write_data270_1;
|
||||
write_data_m270_1 <= write_data_m270;
|
||||
write_data_m270_2 <= write_data_m270_1;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
write_data_rising <= write_data270_2;
|
||||
write_data_falling <= write_data90_2;
|
||||
data_mask_r <= write_data_m270_2;
|
||||
data_mask_f <= write_data_m90_2;
|
||||
|
||||
-- write enable for data path
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
write_en_P1 <= write_enable;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- write enable for data path
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '0' then
|
||||
write_en_val <= write_en_P1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
144
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
Executable file
144
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
Executable file
@@ -0,0 +1,144 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_dqs_delay_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the delay in the dqs signal.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_dqs_delay is
|
||||
port (
|
||||
clk_in : in std_logic;
|
||||
sel_in : in std_logic_vector(4 downto 0);
|
||||
clk_out : out std_logic
|
||||
);
|
||||
end vhdl_bl4_dqs_delay;
|
||||
|
||||
architecture arc_dqs_delay of vhdl_bl4_dqs_delay is
|
||||
|
||||
signal delay1 : std_logic;
|
||||
signal delay2 : std_logic;
|
||||
signal delay3 : std_logic;
|
||||
signal delay4 : std_logic;
|
||||
signal delay5 : std_logic;
|
||||
signal high : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of one : label is true;
|
||||
attribute syn_preserve of two : label is true;
|
||||
attribute syn_preserve of three : label is true;
|
||||
attribute syn_preserve of four : label is true;
|
||||
attribute syn_preserve of five : label is true;
|
||||
attribute syn_preserve of six : label is true;
|
||||
|
||||
begin
|
||||
|
||||
high <= '1';
|
||||
|
||||
one : LUT4 generic map (INIT => x"f3c0")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => sel_in(4),
|
||||
I2 => delay5,
|
||||
I3 => clk_in,
|
||||
O => clk_out
|
||||
);
|
||||
|
||||
two : LUT4 generic map (INIT => x"ee22")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(2),
|
||||
I2 => high,
|
||||
I3 => delay3,
|
||||
O => delay4
|
||||
);
|
||||
|
||||
three : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(0),
|
||||
I2 => delay1,
|
||||
I3 => high,
|
||||
O => delay2
|
||||
);
|
||||
|
||||
four : LUT4 generic map (INIT => x"ff00")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => high,
|
||||
I2 => high,
|
||||
I3 => clk_in,
|
||||
O => delay1
|
||||
);
|
||||
|
||||
five : LUT4 generic map (INIT => x"f3c0")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => sel_in(3),
|
||||
I2 => delay4,
|
||||
I3 => clk_in,
|
||||
O => delay5
|
||||
);
|
||||
|
||||
six : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => clk_in,
|
||||
I1 => sel_in(1),
|
||||
I2 => delay2,
|
||||
I3 => high,
|
||||
O => delay3
|
||||
);
|
||||
|
||||
end arc_dqs_delay;
|
||||
92
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd
Executable file
92
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd
Executable file
@@ -0,0 +1,92 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_fifo_0_wr_en_0.v
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the write enable signal to the fifos,
|
||||
-- which are driven by negedge of data strobe
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_fifo_0_wr_en_0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
rst_dqs_delay_n : out std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_fifo_0_wr_en_0;
|
||||
|
||||
architecture arc of vhdl_bl4_fifo_0_wr_en_0 is
|
||||
|
||||
signal din_delay : std_ulogic;
|
||||
signal tie_high : std_ulogic;
|
||||
|
||||
begin
|
||||
|
||||
rst_dqs_delay_n <= not din_delay;
|
||||
dout <= din or din_delay;
|
||||
tie_high <= '1';
|
||||
|
||||
delay_ff : FDCE
|
||||
port map (
|
||||
Q => din_delay,
|
||||
C => clk,
|
||||
CE => tie_high,
|
||||
CLR => reset,
|
||||
D => din
|
||||
);
|
||||
|
||||
end arc;
|
||||
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd
Executable file
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_fifo_0_wr_en_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the write enable signal to the fifos,
|
||||
-- which are driven by posedge of data strobe
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_fifo_1_wr_en_0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst_dqs_delay_n : in std_logic;
|
||||
reset : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic
|
||||
);
|
||||
end vhdl_bl4_fifo_1_wr_en_0;
|
||||
|
||||
architecture arc of vhdl_bl4_fifo_1_wr_en_0 is
|
||||
|
||||
signal din_delay : std_ulogic;
|
||||
signal tie_high : std_ulogic;
|
||||
signal dout0 : std_ulogic;
|
||||
signal rst_dqs_delay : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
rst_dqs_delay <= not rst_dqs_delay_n;
|
||||
dout0 <= din and rst_dqs_delay_n;
|
||||
dout <= rst_dqs_delay or din_delay;
|
||||
tie_high <= '1';
|
||||
|
||||
delay_ff_1 : FDCE
|
||||
port map (
|
||||
Q => din_delay,
|
||||
C => clk,
|
||||
CE => tie_high,
|
||||
CLR => reset,
|
||||
D => dout0
|
||||
);
|
||||
|
||||
end arc;
|
||||
110
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd
Executable file
110
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd
Executable file
@@ -0,0 +1,110 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_infrastructure is
|
||||
port(
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
rst_calib1 : in std_logic;
|
||||
clk_int : in std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic
|
||||
);
|
||||
end vhdl_bl4_infrastructure;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure is
|
||||
|
||||
signal delay_sel_val1 : std_logic_vector(4 downto 0);
|
||||
signal rst_calib1_r1 : std_logic;
|
||||
signal rst_calib1_r2 : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
delay_sel_val1_val <= delay_sel_val1;
|
||||
dbg_delay_sel <= delay_sel_val1;
|
||||
dbg_rst_calib <= rst_calib1_r2;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '0' then
|
||||
rst_calib1_r1 <= rst_calib1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '1' then
|
||||
rst_calib1_r2 <= rst_calib1_r1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int)
|
||||
begin
|
||||
if clk_int 'event and clk_int = '1' then
|
||||
if (rst_calib1_r2 = '0') then
|
||||
delay_sel_val1 <= delay_sel_val;
|
||||
else
|
||||
delay_sel_val1 <= delay_sel_val1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arc;
|
||||
125
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd
Executable file
125
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd
Executable file
@@ -0,0 +1,125 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the FDDRRSE instantiations to the clocks.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_infrastructure_iobs_0 is
|
||||
port(
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
clk0 : in std_logic
|
||||
);
|
||||
end vhdl_bl4_infrastructure_iobs_0;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure_iobs_0 is
|
||||
|
||||
signal ddr2_clk_q : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
---- **************************************************
|
||||
---- iob attributes for instantiated FDDRRSE components
|
||||
---- **************************************************
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
vcc <= '1';
|
||||
clk180 <= not clk0;
|
||||
|
||||
--- ***********************************
|
||||
---- This includes instantiation of the output DDR flip flop
|
||||
---- for ddr clk's and dimm clk's
|
||||
---- ***********************************************************
|
||||
|
||||
|
||||
|
||||
|
||||
U_clk_i : FDDRRSE
|
||||
port map (
|
||||
Q => ddr2_clk_q,
|
||||
C0 => clk0,
|
||||
C1 => clk180,
|
||||
CE => vcc,
|
||||
D0 => vcc,
|
||||
D1 => gnd,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
---- ******************************************
|
||||
---- Ouput BUffers for ddr clk's and dimm clk's
|
||||
---- ******************************************
|
||||
|
||||
|
||||
|
||||
|
||||
r_inst : OBUFDS
|
||||
port map (
|
||||
I => ddr2_clk_q,
|
||||
O => ddr2_ck(0),
|
||||
OB => ddr2_ck_n(0)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
293
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd
Executable file
293
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd
Executable file
@@ -0,0 +1,293 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_infrastructure_top.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has instantiations clk_dcm,cal_top and generate
|
||||
-- reset signals to the design
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_infrastructure_top is
|
||||
port(
|
||||
reset_in_n : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_clkb : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
sys_rst_val : out std_logic;
|
||||
sys_rst90_val : out std_logic;
|
||||
clk_int_val : out std_logic;
|
||||
clk90_int_val : out std_logic;
|
||||
sys_rst180_val : out std_logic;
|
||||
wait_200us : out std_logic;
|
||||
-- debug signals
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_infrastructure_top;
|
||||
|
||||
architecture arc of vhdl_bl4_infrastructure_top is
|
||||
|
||||
component vhdl_bl4_clk_dcm
|
||||
port(
|
||||
input_clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
clk : out std_logic;
|
||||
clk90 : out std_logic;
|
||||
dcm_lock : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_cal_top
|
||||
port (
|
||||
clk : in std_logic;
|
||||
clk0dcmlock : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapfordqs : out std_logic_vector(4 downto 0);
|
||||
dbg_phase_cnt : out std_logic_vector(4 downto 0);
|
||||
dbg_cnt : out std_logic_vector(5 downto 0);
|
||||
dbg_trans_onedtct : out std_logic;
|
||||
dbg_trans_twodtct : out std_logic;
|
||||
dbg_enb_trans_two_dtct : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal user_rst : std_logic;
|
||||
signal user_cal_rst : std_logic;
|
||||
signal clk_int : std_logic;
|
||||
signal clk90_int : std_logic;
|
||||
signal dcm_lock : std_logic;
|
||||
signal sys_rst_o : std_logic;
|
||||
signal sys_rst_1 : std_logic := '1';
|
||||
signal sys_rst : std_logic;
|
||||
signal sys_rst90_o : std_logic;
|
||||
signal sys_rst90_1 : std_logic := '1';
|
||||
signal sys_rst90 : std_logic;
|
||||
signal sys_rst180_o : std_logic;
|
||||
signal sys_rst180_1 : std_logic := '1';
|
||||
signal sys_rst180 : std_logic;
|
||||
signal delay_sel_val1 : std_logic_vector(4 downto 0);
|
||||
signal clk_int_val1 : std_logic;
|
||||
signal clk_int_val2 : std_logic;
|
||||
signal clk90_int_val1 : std_logic;
|
||||
signal clk90_int_val2 : std_logic;
|
||||
signal wait_200us_i : std_logic;
|
||||
signal wait_200us_int : std_logic;
|
||||
signal wait_clk90 : std_logic;
|
||||
signal wait_clk270 : std_logic;
|
||||
signal counter200 : std_logic_vector(15 downto 0);
|
||||
signal sys_clk_ibuf : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
DIFF_ENDED_CLKS_INST : if(CLK_TYPE = "DIFFERENTIAL") generate
|
||||
begin
|
||||
SYS_CLK_INST : IBUFGDS_LVDS_25
|
||||
port map(
|
||||
I => sys_clk,
|
||||
IB => sys_clkb,
|
||||
O => sys_clk_ibuf
|
||||
);
|
||||
end generate;
|
||||
|
||||
SINGLE_ENDED_CLKS_INST : if(CLK_TYPE = "SINGLE_ENDED") generate
|
||||
begin
|
||||
SYS_CLK_INST : IBUFG
|
||||
port map(
|
||||
I => sys_clk_in,
|
||||
O => sys_clk_ibuf
|
||||
);
|
||||
end generate;
|
||||
|
||||
clk_int_val <= clk_int;
|
||||
clk90_int_val <= clk90_int;
|
||||
sys_rst_val <= sys_rst;
|
||||
sys_rst90_val <= sys_rst90;
|
||||
sys_rst180_val <= sys_rst180;
|
||||
delay_sel_val1_val <= delay_sel_val1;
|
||||
|
||||
|
||||
-- To remove delta delays in the clock signals observed during simulation
|
||||
-- ,Following signals are used
|
||||
|
||||
clk_int_val1 <= clk_int;
|
||||
clk90_int_val1 <= clk90_int;
|
||||
clk_int_val2 <= clk_int_val1;
|
||||
clk90_int_val2 <= clk90_int_val1;
|
||||
user_rst <= not reset_in_n when RESET_ACTIVE_LOW = '1' else reset_in_n;
|
||||
user_cal_rst <= reset_in_n when RESET_ACTIVE_LOW = '1' else not reset_in_n;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' then
|
||||
wait_200us_i <= '1';
|
||||
counter200 <= (others => '0');
|
||||
else
|
||||
if( counter200 < 33400) then
|
||||
wait_200us_i <= '1';
|
||||
counter200 <= counter200 + 1;
|
||||
else
|
||||
counter200 <= counter200;
|
||||
wait_200us_i <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
wait_200us <= wait_200us_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
wait_200us_int <= wait_200us_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '0' then
|
||||
if user_rst = '1' or dcm_lock = '0' then
|
||||
wait_clk270 <= '1';
|
||||
else
|
||||
wait_clk270 <= wait_200us_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '1' then
|
||||
wait_clk90 <= wait_clk270;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_200us_int = '1' then
|
||||
sys_rst_o <= '1';
|
||||
sys_rst_1 <= '1';
|
||||
sys_rst <= '1';
|
||||
else
|
||||
sys_rst_o <= '0';
|
||||
sys_rst_1 <= sys_rst_o;
|
||||
sys_rst <= sys_rst_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90_int_val2)
|
||||
begin
|
||||
if clk90_int_val2'event and clk90_int_val2 = '1' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_clk90 = '1' then
|
||||
sys_rst90_o <= '1';
|
||||
sys_rst90_1 <= '1';
|
||||
sys_rst90 <= '1';
|
||||
else
|
||||
sys_rst90_o <= '0';
|
||||
sys_rst90_1 <= sys_rst90_o;
|
||||
sys_rst90 <= sys_rst90_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_int_val2)
|
||||
begin
|
||||
if clk_int_val2'event and clk_int_val2 = '0' then
|
||||
if user_rst = '1' or dcm_lock = '0' or wait_clk270 = '1' then
|
||||
sys_rst180_o <= '1';
|
||||
sys_rst180_1 <= '1';
|
||||
sys_rst180 <= '1';
|
||||
else
|
||||
sys_rst180_o <= '0';
|
||||
sys_rst180_1 <= sys_rst180_o;
|
||||
sys_rst180 <= sys_rst180_1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
clk_dcm0 : vhdl_bl4_clk_dcm
|
||||
port map (
|
||||
input_clk => sys_clk_ibuf,
|
||||
rst => user_rst,
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
dcm_lock => dcm_lock
|
||||
);
|
||||
|
||||
cal_top0 : vhdl_bl4_cal_top
|
||||
port map (
|
||||
clk => clk_int_val2,
|
||||
clk0dcmlock => dcm_lock,
|
||||
reset => user_cal_rst,
|
||||
tapfordqs => delay_sel_val1,
|
||||
dbg_phase_cnt => dbg_phase_cnt,
|
||||
dbg_cnt => dbg_cnt,
|
||||
dbg_trans_onedtct => dbg_trans_onedtct,
|
||||
dbg_trans_twodtct => dbg_trans_twodtct,
|
||||
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
|
||||
);
|
||||
|
||||
end arc;
|
||||
225
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd
Executable file
225
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd
Executable file
@@ -0,0 +1,225 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_iobs_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the instantiations infrastructure_iobs,
|
||||
-- data_path_iobs and controller_iobs modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_iobs_0 is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
rst_dqs_div_int : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end vhdl_bl4_iobs_0;
|
||||
|
||||
|
||||
architecture arc of vhdl_bl4_iobs_0 is
|
||||
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
|
||||
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_3_ddr2_sp3, Coregen 11.4";
|
||||
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_3,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000}";
|
||||
|
||||
component vhdl_bl4_infrastructure_iobs_0
|
||||
port(
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
clk0 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_controller_iobs_0
|
||||
port(
|
||||
clk0 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_odt_cntrl : in std_logic;
|
||||
rst_dqs_div_int : in std_logic;
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
ddr_ODT : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_path_iobs_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
infrastructure_iobs0 : vhdl_bl4_infrastructure_iobs_0
|
||||
port map (
|
||||
clk0 => clk,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n
|
||||
);
|
||||
|
||||
controller_iobs0 : vhdl_bl4_controller_iobs_0
|
||||
port map (
|
||||
clk0 => clk,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl((ROW_ADDRESS -1) downto 0),
|
||||
ddr_ba_cntrl => ddr_ba_cntrl((BANK_ADDRESS -1) downto 0),
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
ddr_rasb => ddr_rasb,
|
||||
ddr_casb => ddr_casb,
|
||||
ddr_web => ddr_web,
|
||||
ddr_ba => ddr_ba((BANK_ADDRESS -1) downto 0),
|
||||
ddr_address => ddr_address((ROW_ADDRESS -1) downto 0),
|
||||
ddr_cke => ddr_cke,
|
||||
ddr_csb => ddr_csb,
|
||||
ddr_odt => ddr_odt,
|
||||
rst_dqs_div => rst_dqs_div,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out
|
||||
);
|
||||
|
||||
datapath_iobs0 : vhdl_bl4_data_path_iobs_0
|
||||
port map (
|
||||
clk => clk,
|
||||
clk90 => clk90,
|
||||
dqs_reset => dqs_reset,
|
||||
dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr_dqs,
|
||||
ddr_dqs_n => ddr_dqs_n,
|
||||
ddr_dq => ddr_dq,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
ddr_dm => ddr_dm,
|
||||
ddr_dq_val => dq
|
||||
);
|
||||
|
||||
end arc;
|
||||
271
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_main_0.vhd
Executable file
271
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_main_0.vhd
Executable file
@@ -0,0 +1,271 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_main_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This modules has the instantiations top and test_bench.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_main_0 is
|
||||
port(
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
clk_int : in std_logic;
|
||||
wait_200us : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_a : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
ddr2_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
|
||||
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
led_error_output1 : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
init_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
dbg_cmp_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
dbg_test_bench : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end vhdl_bl4_main_0;
|
||||
|
||||
architecture arc of vhdl_bl4_main_0 is
|
||||
|
||||
component vhdl_bl4_test_bench_0
|
||||
port(
|
||||
fpga_clk : in std_logic;
|
||||
fpga_rst90 : in std_logic;
|
||||
fpga_rst180 : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
burst_done : out std_logic;
|
||||
init_done : in std_logic;
|
||||
auto_ref_req : in std_logic;
|
||||
ar_done : in std_logic;
|
||||
u_ack : in std_logic;
|
||||
u_data_val : in std_logic;
|
||||
u_data_o : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
u_addr : out std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)- 1) downto 0);
|
||||
u_cmd : out std_logic_vector(2 downto 0);
|
||||
u_data_m : out std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
u_data_i : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
led_error_output : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
dbg_cmp_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
dbg_test_bench : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
component vhdl_bl4_top_0
|
||||
port(
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
|
||||
downto 0) := (others => 'Z');
|
||||
user_data_valid : out std_logic;
|
||||
user_input_address : in std_logic_vector(((ROW_ADDRESS +
|
||||
COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)-1) downto 0);
|
||||
user_command_register : in std_logic_vector(2 downto 0);
|
||||
user_cmd_ack : out std_logic;
|
||||
burst_done : in std_logic;
|
||||
init_done : out std_logic;
|
||||
auto_ref_req : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0):=(others => 'Z');
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
clk_int : in std_logic;
|
||||
wait_200us : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
DDR2_ODT : out std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal user_output_data : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal u1_address : std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)-1) downto 0);
|
||||
signal user_data_val1 : std_logic;
|
||||
signal user_cmd1 : std_logic_vector(2 downto 0);
|
||||
signal auto_ref_req : std_logic;
|
||||
signal user_ack1 : std_logic;
|
||||
signal u1_data_i : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal u1_data_m : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal burst_done_val1 : std_logic;
|
||||
signal ar_done_val1 : std_logic;
|
||||
signal init_done_int : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
init_done <= init_done_int;
|
||||
|
||||
top0 : vhdl_bl4_top_0
|
||||
port map(
|
||||
auto_ref_req => auto_ref_req,
|
||||
wait_200us => wait_200us,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
user_input_data => u1_data_i,
|
||||
user_data_mask => u1_data_m,
|
||||
user_output_data => user_output_data,
|
||||
user_data_valid => user_data_val1,
|
||||
user_input_address => u1_address,
|
||||
user_command_register => user_cmd1,
|
||||
user_cmd_ack => user_ack1,
|
||||
burst_done => burst_done_val1,
|
||||
init_done => init_done_int,
|
||||
ar_done => ar_done_val1,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_dm => ddr2_dm,
|
||||
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
clk90_int => clk90_int,
|
||||
clk_int => clk_int,
|
||||
delay_sel_val => delay_sel_val,
|
||||
sys_rst => sys_rst,
|
||||
sys_rst90 => sys_rst90,
|
||||
sys_rst180 => sys_rst180,
|
||||
dbg_delay_sel => dbg_delay_sel,
|
||||
dbg_rst_calib => dbg_rst_calib,
|
||||
dbg_controller => dbg_controller,
|
||||
--debug signals
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
test_bench0 : vhdl_bl4_test_bench_0
|
||||
port map (
|
||||
auto_ref_req => auto_ref_req,
|
||||
fpga_clk => clk_int,
|
||||
fpga_rst90 => sys_rst90,
|
||||
fpga_rst180 => sys_rst180,
|
||||
clk90 => clk90_int,
|
||||
burst_done => burst_done_val1,
|
||||
init_done => init_done_int,
|
||||
ar_done => ar_done_val1,
|
||||
u_ack => user_ack1,
|
||||
u_data_val => user_data_val1,
|
||||
u_data_o => user_output_data,
|
||||
u_addr => u1_address,
|
||||
u_cmd => user_cmd1,
|
||||
u_data_i => u1_data_i ,
|
||||
u_data_m => u1_data_m,
|
||||
led_error_output => led_error_output1,
|
||||
data_valid_out => data_valid_out,
|
||||
dbg_cmp_data => dbg_cmp_data,
|
||||
dbg_test_bench => dbg_test_bench
|
||||
);
|
||||
|
||||
end arc;
|
||||
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd
Executable file
94
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_parameters_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module has the parameters used in the design
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
package vhdl_bl4_parameters_0 is
|
||||
|
||||
-- The reset polarity is set to active low by default.
|
||||
-- You can change this by editing the parameter RESET_ACTIVE_LOW.
|
||||
-- Please do not change any of the other parameters directly by editing the RTL.
|
||||
-- All other changes should be done through the GUI.
|
||||
|
||||
constant DATA_WIDTH : INTEGER := 16;
|
||||
constant DATA_STROBE_WIDTH : INTEGER := 2;
|
||||
constant DATA_MASK_WIDTH : INTEGER := 2;
|
||||
constant CLK_WIDTH : INTEGER := 1;
|
||||
constant CKE_WIDTH : INTEGER := 1;
|
||||
constant ROW_ADDRESS : INTEGER := 13;
|
||||
constant MEMORY_WIDTH : INTEGER := 8;
|
||||
constant REGISTERED : INTEGER := 0;
|
||||
constant DATABITSPERSTROBE : INTEGER := 8;
|
||||
constant RESET_PORT : INTEGER := 0;
|
||||
constant MASK_ENABLE : INTEGER := 1;
|
||||
constant USE_DM_PORT : INTEGER := 1;
|
||||
constant COLUMN_ADDRESS : INTEGER := 10;
|
||||
constant BANK_ADDRESS : INTEGER := 2;
|
||||
constant DEBUG_EN : INTEGER := 1;
|
||||
constant CLK_TYPE : string := "SINGLE_ENDED";
|
||||
constant LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0010100110010";
|
||||
|
||||
constant EXT_LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0000000000000";
|
||||
|
||||
constant RESET_ACTIVE_LOW : std_logic := '0';
|
||||
constant RAS_COUNT_VALUE : std_logic_vector(4 downto 0) := "00101";
|
||||
constant RP_COUNT_VALUE : std_logic_vector(2 downto 0) := "001";
|
||||
constant RFC_COUNT_VALUE : std_logic_vector(7 downto 0) := "00001101";
|
||||
constant TWR_COUNT_VALUE : std_logic_vector(2 downto 0) := "010";
|
||||
constant MAX_REF_WIDTH : INTEGER := 10;
|
||||
constant MAX_REF_CNT : std_logic_vector(9 downto 0) := "1111100111";
|
||||
|
||||
end vhdl_bl4_parameters_0 ;
|
||||
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd
Executable file
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd
Executable file
@@ -0,0 +1,215 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_ram8d_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates RAM16X1 premitives. There will be 8 or 4 RAM16X1
|
||||
-- instances depending on the number of data bits per strobe.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
library UNISIM;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.STD_LOGIC_ARITH.all;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_ram8d_0 is
|
||||
port (
|
||||
dout : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
waddr : in std_logic_vector(3 downto 0);
|
||||
din : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
raddr : in std_logic_vector(3 downto 0);
|
||||
wclk0 : in std_logic;
|
||||
wclk1 : in std_logic;
|
||||
we : in std_logic
|
||||
);
|
||||
end vhdl_bl4_ram8d_0;
|
||||
|
||||
architecture arc of vhdl_bl4_ram8d_0 is
|
||||
|
||||
begin
|
||||
|
||||
fifo_bit0 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(0),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(0),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit1 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(1),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(1),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit2 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(2),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(2),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit3 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(3),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(3),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit4 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(4),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(4),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit5 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(5),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(5),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit6 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(6),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(6),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit7 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(7),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(7),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
end arc;
|
||||
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd
Executable file
215
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd
Executable file
@@ -0,0 +1,215 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_ram8d_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:57 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates RAM16X1 premitives. There will be 8 or 4 RAM16X1
|
||||
-- instances depending on the number of data bits per strobe.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
library UNISIM;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.STD_LOGIC_ARITH.all;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_ram8d_1 is
|
||||
port (
|
||||
dout : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
waddr : in std_logic_vector(3 downto 0);
|
||||
din : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
|
||||
raddr : in std_logic_vector(3 downto 0);
|
||||
wclk0 : in std_logic;
|
||||
wclk1 : in std_logic;
|
||||
we : in std_logic
|
||||
);
|
||||
end vhdl_bl4_ram8d_1;
|
||||
|
||||
architecture arc of vhdl_bl4_ram8d_1 is
|
||||
|
||||
begin
|
||||
|
||||
fifo_bit0 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(0),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(0),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit1 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(1),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(1),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit2 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(2),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(2),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit3 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(3),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(3),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit4 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(4),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(4),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit5 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(5),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(5),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk0,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit6 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(6),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(6),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
fifo_bit7 : RAM16X1D
|
||||
port map (
|
||||
DPO => dout(7),
|
||||
A0 => waddr(0),
|
||||
A1 => waddr(1),
|
||||
A2 => waddr(2),
|
||||
A3 => waddr(3),
|
||||
D => din(7),
|
||||
DPRA0 => raddr(0),
|
||||
DPRA1 => raddr(1),
|
||||
DPRA2 => raddr(2),
|
||||
DPRA3 => raddr(3),
|
||||
WCLK => wclk1,
|
||||
SPO => OPEN,
|
||||
WE => we
|
||||
);
|
||||
|
||||
end arc;
|
||||
147
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd
Executable file
147
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd
Executable file
@@ -0,0 +1,147 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_rd_gray_cntr.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generates read address for the FIFOs.
|
||||
--*****************************************************************************
|
||||
|
||||
-- fifo_rd_addr gray counter with synchronous reset
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_rd_gray_cntr is
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
rgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end vhdl_bl4_rd_gray_cntr;
|
||||
|
||||
architecture arc of vhdl_bl4_rd_gray_cntr is
|
||||
|
||||
signal gc_int : std_logic_vector(3 downto 0);
|
||||
signal d_in : std_logic_vector(3 downto 0);
|
||||
signal reset90_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
rgc_gcnt <= gc_int(3 downto 0);
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if(clk90'event and clk90 = '1') then
|
||||
reset90_r <= reset90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(gc_int)
|
||||
begin
|
||||
case gc_int is
|
||||
when "0000" => d_in <= "0001"; --0 > 1
|
||||
when "0001" => d_in <= "0011"; --1 > 3
|
||||
when "0010" => d_in <= "0110"; --2 > 6
|
||||
when "0011" => d_in <= "0010"; --3 > 2
|
||||
when "0100" => d_in <= "1100"; --4 > c
|
||||
when "0101" => d_in <= "0100"; --5 > 4
|
||||
when "0110" => d_in <= "0111"; --6 > 7
|
||||
when "0111" => d_in <= "0101"; --7 > 5
|
||||
when "1000" => d_in <= "0000"; --8 > 0
|
||||
when "1001" => d_in <= "1000"; --9 > 8
|
||||
when "1010" => d_in <= "1011"; --10 > b
|
||||
when "1011" => d_in <= "1001"; --11 > 9
|
||||
when "1100" => d_in <= "1101"; --12 > d
|
||||
when "1101" => d_in <= "1111"; --13 > f
|
||||
when "1110" => d_in <= "1010"; --14 > a
|
||||
when "1111" => d_in <= "1110"; --15 > e
|
||||
when others => d_in <= "0001"; --0 > 1
|
||||
end case;
|
||||
end process;
|
||||
|
||||
bit0 : FDRE
|
||||
port map (
|
||||
Q => gc_int(0),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(0),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit1 : FDRE
|
||||
port map (
|
||||
Q => gc_int(1),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(1),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit2 : FDRE
|
||||
port map (
|
||||
Q => gc_int(2),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(2),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
bit3 : FDRE
|
||||
port map (
|
||||
Q => gc_int(3),
|
||||
C => clk90,
|
||||
CE => cnt_en,
|
||||
D => d_in(3),
|
||||
R => reset90_r
|
||||
);
|
||||
|
||||
end arc;
|
||||
106
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd
Executable file
106
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd
Executable file
@@ -0,0 +1,106 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dm_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates DDR IOB output flip-flops, and an
|
||||
-- output buffer for the data mask bits.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dm_iob is
|
||||
port (
|
||||
ddr_dm : out std_logic; --Data mask output
|
||||
mask_falling : in std_logic; --Mask output on falling edge
|
||||
mask_rising : in std_logic; --Mask output on rising edge
|
||||
clk90 : in std_logic
|
||||
);
|
||||
end vhdl_bl4_s3_dm_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dm_iob is
|
||||
|
||||
--***********************************************************************\
|
||||
-- Internal signal declaration
|
||||
--***********************************************************************/
|
||||
|
||||
signal mask_o : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
begin
|
||||
|
||||
gnd <= '0';
|
||||
vcc <= '1';
|
||||
clk270 <= not clk90;
|
||||
|
||||
-- Data Mask Output during a write command
|
||||
|
||||
DDR_DM0_OUT : FDDRRSE
|
||||
port map (
|
||||
Q => mask_o,
|
||||
C0 => clk270,
|
||||
C1 => clk90,
|
||||
CE => vcc,
|
||||
D0 => mask_rising,
|
||||
D1 => mask_falling,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
DM1_OBUF : OBUF
|
||||
port map (
|
||||
I => mask_o,
|
||||
O => ddr_dm
|
||||
);
|
||||
|
||||
end arc;
|
||||
135
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd
Executable file
135
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd
Executable file
@@ -0,0 +1,135 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dq_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiate DDR IOB output flip-flops, an
|
||||
-- output buffer with registered tri-state, and an input buffer
|
||||
-- for a single data/dq bit. The DDR IOB output flip-flops
|
||||
-- are used to forward data to memory during a write.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dq_iob is
|
||||
port (
|
||||
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
|
||||
write_data_falling : in std_logic; --Transmit data, output on falling edge
|
||||
write_data_rising : in std_logic; --Transmit data, output on rising edge
|
||||
read_data_in : out std_logic; -- Received data
|
||||
clk90 : in std_logic; --Clock 90
|
||||
write_en_val : in std_logic
|
||||
);
|
||||
end vhdl_bl4_s3_dq_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dq_iob is
|
||||
|
||||
--***********************************************************************\
|
||||
-- Internal signal declaration
|
||||
--***********************************************************************/
|
||||
signal ddr_en : std_logic; -- Tri-state enable signal
|
||||
signal ddr_dq_q : std_logic; -- Data output intermediate signal
|
||||
signal gnd : std_logic;
|
||||
signal clock_en : std_logic;
|
||||
signal enable_b : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
|
||||
attribute iob : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute iob of DQ_T : label is "FORCE";
|
||||
attribute syn_useioff of DQ_T : label is true;
|
||||
|
||||
begin
|
||||
|
||||
clk270 <= not clk90;
|
||||
gnd <= '0';
|
||||
enable_b <= not write_en_val;
|
||||
clock_en <= '1';
|
||||
|
||||
-- Transmission data path
|
||||
|
||||
DDR_OUT : FDDRRSE
|
||||
port map (
|
||||
Q => ddr_dq_q,
|
||||
C0 => clk270,
|
||||
C1 => clk90,
|
||||
CE => clock_en,
|
||||
D0 => write_data_rising,
|
||||
D1 => write_data_falling,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
DQ_T : FD
|
||||
port map (
|
||||
D => enable_b,
|
||||
C => clk270,
|
||||
Q => ddr_en
|
||||
);
|
||||
|
||||
DQ_OBUFT : OBUFT
|
||||
port map (
|
||||
I => ddr_dq_q,
|
||||
T => ddr_en,
|
||||
O => ddr_dq_inout
|
||||
);
|
||||
|
||||
-- Receive data path
|
||||
|
||||
DQ_IBUF : IBUF
|
||||
port map(
|
||||
I => ddr_dq_inout,
|
||||
O => read_data_in
|
||||
);
|
||||
|
||||
end arc;
|
||||
148
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd
Executable file
148
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd
Executable file
@@ -0,0 +1,148 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_s3_dqs_iob.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module instantiates DDR IOB output flip-flops, an
|
||||
-- output buffer with registered tri-state, and an input buffer
|
||||
-- for a single strobe/dqs bit. The DDR IOB output flip-flops
|
||||
-- are used to forward strobe to memory during a write. During
|
||||
-- a read, the output of the IBUF is routed to the internal
|
||||
-- delay module, dqs_delay.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_s3_dqs_iob is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
ddr_dqs_reset : in std_logic;
|
||||
ddr_dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic;
|
||||
ddr_dqs_n : inout std_logic;
|
||||
dqs : out std_logic);
|
||||
end vhdl_bl4_s3_dqs_iob;
|
||||
|
||||
architecture arc of vhdl_bl4_s3_dqs_iob is
|
||||
|
||||
|
||||
signal dqs_q : std_logic;
|
||||
signal ddr_dqs_enable1 : std_logic;
|
||||
signal vcc : std_logic;
|
||||
signal gnd : std_logic;
|
||||
signal ddr_dqs_enable_b : std_logic;
|
||||
signal data1 : std_logic;
|
||||
signal clk180 : std_logic;
|
||||
|
||||
attribute IOB : string;
|
||||
attribute syn_useioff : boolean;
|
||||
|
||||
attribute IOB of U1 : label is "FORCE";
|
||||
attribute syn_useioff of U1 : label is true;
|
||||
|
||||
begin
|
||||
|
||||
--******************************************************************************
|
||||
-- Output DDR generation. This includes instantiation of the output DDR flip flop.
|
||||
-- Additionally, to keep synthesis tools from register sharing, manually
|
||||
-- instantiate the output tri-state flip-flop.
|
||||
--******************************************************************************
|
||||
vcc <= '1';
|
||||
gnd <= '0';
|
||||
clk180 <= not clk;
|
||||
ddr_dqs_enable_b <= not ddr_dqs_enable;
|
||||
data1 <= '0' when ddr_dqs_reset = '1' else
|
||||
'1';
|
||||
|
||||
U1 : FD
|
||||
port map (
|
||||
D => ddr_dqs_enable_b,
|
||||
Q => ddr_dqs_enable1,
|
||||
C => clk
|
||||
);
|
||||
|
||||
|
||||
U2 : FDDRRSE
|
||||
port map (
|
||||
Q => dqs_q,
|
||||
C0 => clk,
|
||||
C1 => clk180,
|
||||
CE => vcc,
|
||||
D0 => data1,
|
||||
D1 => gnd,
|
||||
R => gnd,
|
||||
S => gnd
|
||||
);
|
||||
|
||||
|
||||
|
||||
--***********************************************************************
|
||||
-- IO buffer for dqs signal. Allows for distribution of dqs
|
||||
-- to the data (DQ) loads.
|
||||
--***********************************************************************
|
||||
|
||||
|
||||
U3 : OBUFTDS port map (
|
||||
I => dqs_q,
|
||||
T => ddr_dqs_enable1,
|
||||
O => ddr_dqs,
|
||||
OB => ddr_dqs_n
|
||||
);
|
||||
|
||||
U4 : IBUFDS port map(
|
||||
I => ddr_dqs,
|
||||
IB => ddr_dqs_n,
|
||||
O => dqs
|
||||
);
|
||||
|
||||
|
||||
|
||||
end arc;
|
||||
386
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd
Executable file
386
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd
Executable file
@@ -0,0 +1,386 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_tap_dly.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :This module generates a 32 bit tap delay register used by the
|
||||
-- cal_ctl module to find out the phase transitions.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
|
||||
entity vhdl_bl4_tap_dly is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
tapin : in std_logic;
|
||||
flop2 : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end vhdl_bl4_tap_dly;
|
||||
|
||||
architecture arc_tap_dly of vhdl_bl4_tap_dly is
|
||||
|
||||
signal tap : std_logic_vector(31 downto 0);
|
||||
signal flop1 : std_logic_vector(31 downto 0);
|
||||
signal high : std_logic;
|
||||
signal low : std_logic;
|
||||
signal flop2_xnor : std_logic_vector(30 downto 0);
|
||||
signal reset_r : std_logic;
|
||||
|
||||
attribute syn_preserve : boolean;
|
||||
|
||||
attribute syn_preserve of tap : signal is true;
|
||||
attribute syn_preserve of flop1 : signal is true;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if(clk'event and clk='1') then
|
||||
reset_r <= reset;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
high <= '1';
|
||||
low <= '0';
|
||||
|
||||
l0 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tapin,
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(0)
|
||||
);
|
||||
|
||||
l1 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(0),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(1)
|
||||
);
|
||||
l2 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(1),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(2)
|
||||
);
|
||||
l3 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(2),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(3)
|
||||
);
|
||||
l4 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(3),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(4)
|
||||
);
|
||||
l5 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(4),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(5)
|
||||
);
|
||||
l6 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(5),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(6)
|
||||
);
|
||||
l7 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(6),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(7)
|
||||
);
|
||||
l8 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(7),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(8)
|
||||
);
|
||||
l9 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(8),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(9)
|
||||
);
|
||||
l10 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(9),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(10)
|
||||
);
|
||||
l11 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(10),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(11)
|
||||
);
|
||||
l12 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(11),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(12)
|
||||
);
|
||||
l13 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(12),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(13)
|
||||
);
|
||||
l14 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(13),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(14)
|
||||
);
|
||||
l15 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(14),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(15)
|
||||
);
|
||||
l16 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(15),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(16)
|
||||
);
|
||||
l17 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(16),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(17)
|
||||
);
|
||||
l18 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(17),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(18)
|
||||
);
|
||||
l19 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(18),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(19)
|
||||
);
|
||||
l20 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(19),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(20)
|
||||
);
|
||||
l21 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(20),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(21)
|
||||
);
|
||||
l22 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(21),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(22)
|
||||
);
|
||||
l23 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(22),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(23)
|
||||
);
|
||||
l24 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(23),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(24)
|
||||
);
|
||||
l25 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(24),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(25)
|
||||
);
|
||||
l26 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(25),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(26)
|
||||
);
|
||||
l27 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(26),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(27)
|
||||
);
|
||||
l28 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(27),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(28)
|
||||
);
|
||||
l29 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(28),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(29)
|
||||
);
|
||||
l30 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(29),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(30)
|
||||
);
|
||||
l31 : LUT4 generic map (INIT => x"e2e2")
|
||||
port map (
|
||||
I0 => high,
|
||||
I1 => tap(30),
|
||||
I2 => low,
|
||||
I3 => high,
|
||||
O => tap(31)
|
||||
);
|
||||
|
||||
gen_tap1 : for tap1_i in 0 to 31 generate
|
||||
r : FDR port map (
|
||||
Q => flop1(tap1_i),
|
||||
C => clk,
|
||||
D => tap(tap1_i),
|
||||
R => reset_r
|
||||
);
|
||||
end generate;
|
||||
|
||||
gen_asgn : for asgn_i in 0 to 30 generate
|
||||
flop2_xnor(asgn_i) <= flop1(asgn_i) xnor flop1(asgn_i+1);
|
||||
end generate;
|
||||
|
||||
gen_tap2 : for tap2_i in 0 to 30 generate
|
||||
u : FDR port map (
|
||||
Q => flop2(tap2_i),
|
||||
C => clk,
|
||||
D => flop2_xnor(tap2_i),
|
||||
R => reset_r
|
||||
);
|
||||
end generate;
|
||||
|
||||
u31 : FDR
|
||||
port map (
|
||||
Q => flop2(31),
|
||||
C => clk,
|
||||
D => flop1(31),
|
||||
R => reset_r
|
||||
);
|
||||
|
||||
end arc_tap_dly;
|
||||
398
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_test_bench_0.vhd
Executable file
398
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_test_bench_0.vhd
Executable file
@@ -0,0 +1,398 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_test_bench_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This module generate the commands, address and data associated
|
||||
-- with a write and a read command. This module consists of
|
||||
-- addr_gen, data_gen, cmd_fsm and cmp_data modules.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
entity vhdl_bl4_test_bench_0 is
|
||||
port(
|
||||
fpga_clk : in std_logic;
|
||||
fpga_rst90 : in std_logic;
|
||||
fpga_rst180 : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
burst_done : out std_logic;
|
||||
init_done : in std_logic;
|
||||
auto_ref_req : in std_logic;
|
||||
ar_done : in std_logic;
|
||||
u_ack : in std_logic;
|
||||
u_data_val : in std_logic;
|
||||
u_data_o : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
u_addr : out std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)- 1) downto 0);
|
||||
u_cmd : out std_logic_vector(2 downto 0);
|
||||
u_data_m : out std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
u_data_i : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
led_error_output : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
dbg_cmp_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
dbg_test_bench : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end vhdl_bl4_test_bench_0;
|
||||
|
||||
architecture arc of vhdl_bl4_test_bench_0 is
|
||||
|
||||
component vhdl_bl4_addr_gen_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
addr_rst : in std_logic;
|
||||
addr_inc : in std_logic;
|
||||
r_w : in std_logic;
|
||||
addr_out : out std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)- 1) downto 0);
|
||||
burst_done : out std_logic;
|
||||
cnt_roll : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_cmd_fsm_0
|
||||
port (
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
cmd_ack : in std_logic;
|
||||
cnt_roll : in std_logic;
|
||||
r_w : out std_logic;
|
||||
refresh_done : in std_logic;
|
||||
rst90 : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
init_val : in std_logic;
|
||||
addr_inc : out std_logic;
|
||||
addr_rst : out std_logic;
|
||||
u_cmd : out std_logic_vector(2 downto 0);
|
||||
data_rst : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_cmp_data_0
|
||||
port(
|
||||
clk90 : in std_logic;
|
||||
data_valid : in std_logic;
|
||||
cmp_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
read_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
rst90 : in std_logic;
|
||||
led_error_output : out std_logic;
|
||||
data_valid_out : out std_logic;
|
||||
dbg_cmp_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
|
||||
dbg_led_error_output : out std_logic;
|
||||
dbg_data_valid_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_gen_0
|
||||
port (
|
||||
clk90 : in std_logic;
|
||||
rst90 : in std_logic;
|
||||
data_rst : in std_logic;
|
||||
data_ena : in std_logic;
|
||||
mask_data : out std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
data_out : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal clk : std_logic;
|
||||
signal rst90_r : std_logic;
|
||||
signal addr_inc : std_logic;
|
||||
signal addr_rst : std_logic;
|
||||
signal cmd_ack : std_logic;
|
||||
signal cnt_roll : std_logic;
|
||||
signal data_valid : std_logic;
|
||||
signal data_ena_r : std_logic;
|
||||
signal data_ena_w : std_logic;
|
||||
signal data_rst_r : std_logic;
|
||||
signal data_rst_r1 : std_logic;
|
||||
signal data_rst_w : std_logic;
|
||||
signal r_w : std_logic;
|
||||
signal cmp_data_r : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal cmp_data_m_r : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal app_data_w0 : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal app_data_w1 : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal app_data_w2 : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal app_data_w3 : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal app_data_w4 : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
signal app_data_m_w0 : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal app_data_m_w1 : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal app_data_m_w2 : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal app_data_m_w3 : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal app_data_m_w4 : std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
signal addr_out : std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS + BANK_ADDRESS)- 1) downto 0);
|
||||
signal u_dat_flag : std_logic;
|
||||
signal u_dat_fl : std_logic;
|
||||
signal dbg_led_error_output : std_logic;
|
||||
signal dbg_data_valid_out : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Current test bench generates consecutive five write bursts followed by five
|
||||
-- read burst commands. For every consecutive of five write/read commands,
|
||||
-- controller issues active command followed by five write/read commands
|
||||
-- and then a precharge command to the memory. For all five burst commands
|
||||
-- it takes maximum of 20 clock cycles. So within 20 clocks,test bench will
|
||||
-- issue burst_done signal to stop write of read commands to the controller.
|
||||
-- After every precharge command controller s/m will go to idle state and looks
|
||||
-- for auto_ref_req. When auto_ref_req is asserted controller will issue an auto
|
||||
-- refresh command to the memory if it is in idle state. Worst case the controller
|
||||
-- will take 20 clocks from burst_done to auto refresh command to the memory.
|
||||
-- So total number of clocks from auto_ref_req to auto refresh command to memmory
|
||||
-- is 40.The test bench is not required to use the auto_ref_req and ar_done signals
|
||||
-- inorder to terminate the read or write transactions since it takes maximum of 20
|
||||
-- clock cycles for any transaction.
|
||||
|
||||
-- Example:
|
||||
-- At 125Mhz the auto_ref_req will be generated for every 7.492us and for 166Mhz it
|
||||
-- will be generated for every 7.572us which will take care of 40 clocks as shown
|
||||
-- in the below expression
|
||||
--
|
||||
-- Average periodic refresh = 7.8125us
|
||||
-- MAX_REF_CNT = (7812.5ns - 40*clk_period)/clk_period
|
||||
-- At 125Mhz(8ns) MAX_REF_CNT = (7812.5ns - 40*8)/8 = 7492.5/8 = 937
|
||||
-- At 166Mhz(6ns) MAX_REF_CNT = (7812.5ns - 40*6)/6 = 7572.5/6 = 1262
|
||||
|
||||
-- User need to use the auto_ref_req and ar_done input signals in their
|
||||
-- application in order to terminate the ongoing transaction by asserting
|
||||
-- a burst_done signal, when the nunber of clocks is more then 20 between
|
||||
-- auto_ref_req and burst_done signal. The ar_done signal is asserted for
|
||||
-- one clock period by the controller on completion of auto refresh
|
||||
-- command(i.e after tRFC time). User can issue normal read/write commands
|
||||
-- to the controller any time after ar_done is asserted.
|
||||
|
||||
|
||||
-- Test_bench uses two clock phases clk180 and clk90. User write
|
||||
-- data is generated with clk90 phase, for memory write command
|
||||
-- data and strobe are center aligned. Write data to the memory
|
||||
-- is clk90 phase w.r.t strobe. So user write data is generated
|
||||
-- with clk90 phase.Address and commands are generated w.r.t
|
||||
-- clk180. To meet the setup/hold time for memory, memory clk is
|
||||
-- clk0 and all the commands and address are generated with
|
||||
-- clk180 phase.
|
||||
|
||||
|
||||
-- Output : COMMAND REGISTER FORMAT
|
||||
-- 000 - NOP
|
||||
-- 010 - Initialize memory
|
||||
-- 100 - Write Request
|
||||
-- 110 - Read request
|
||||
|
||||
-- Output : Address format
|
||||
-- row address = address(ROW_ADDRESS + COLUMN_ADDRESS + BANK_ADDRESS -1 downto COLUMN_ADDRESS)
|
||||
-- (COLUMN_ADDRESS + BANK_ADDRESS))
|
||||
-- column address = address(COLUMN_ADDRESS + BANK_ADDRESS-1 downto BANK_ADDRESS)
|
||||
dbg_test_bench(2) <= dbg_data_valid_out;
|
||||
dbg_test_bench(1) <= dbg_led_error_output;
|
||||
dbg_test_bench(0) <= init_done;
|
||||
|
||||
clk <= fpga_clk;
|
||||
cmd_ack <= u_ack;
|
||||
data_valid <= u_data_val;
|
||||
u_addr <= addr_out;
|
||||
|
||||
u_data_i <= app_data_w0;
|
||||
u_data_m <= app_data_m_w0;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
rst90_r <= fpga_rst90;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if rst90_r = '1' then
|
||||
app_data_w1 <= (others => '0');
|
||||
app_data_w2 <= (others => '0');
|
||||
app_data_w3 <= (others => '0');
|
||||
app_data_w4 <= (others => '0');
|
||||
app_data_m_w1 <= (others => '0');
|
||||
app_data_m_w2 <= (others => '0');
|
||||
app_data_m_w3 <= (others => '0');
|
||||
app_data_m_w4 <= (others => '0');
|
||||
else
|
||||
app_data_w1 <= app_data_w0;
|
||||
app_data_w2 <= app_data_w1;
|
||||
app_data_w3 <= app_data_w2;
|
||||
app_data_w4 <= app_data_w3;
|
||||
app_data_m_w1 <= app_data_m_w0;
|
||||
app_data_m_w2 <= app_data_m_w1;
|
||||
app_data_m_w3 <= app_data_m_w2;
|
||||
app_data_m_w4 <= app_data_m_w3;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--*********************************************************
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if rst90_r = '1' then
|
||||
data_ena_r <= '0';
|
||||
else
|
||||
if (u_data_val = '1') then
|
||||
data_ena_r <= '1';
|
||||
else
|
||||
data_ena_r <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if rst90_r = '1' then
|
||||
data_ena_w <= '0';
|
||||
else
|
||||
if ((r_w = '0') and (u_ack = '1')) then
|
||||
data_ena_w <= '1';
|
||||
else
|
||||
data_ena_w <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if(rst90_r = '1') then
|
||||
u_dat_flag <= '0';
|
||||
else
|
||||
u_dat_flag <= cmd_ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_dat_fl <= cmd_ack and (not u_dat_flag) and r_w;
|
||||
data_rst_r1 <= u_dat_fl;
|
||||
|
||||
process(clk90)
|
||||
begin
|
||||
if clk90'event and clk90 = '1' then
|
||||
if(rst90_r = '1') then
|
||||
data_rst_r <= '0';
|
||||
else
|
||||
data_rst_r <= data_rst_r1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--*************************************************************************
|
||||
INST1 : vhdl_bl4_addr_gen_0
|
||||
port map (
|
||||
clk => clk,
|
||||
rst180 => fpga_rst180,
|
||||
addr_rst => addr_rst,
|
||||
addr_inc => addr_inc,
|
||||
addr_out => addr_out,
|
||||
burst_done => burst_done,
|
||||
r_w => r_w,
|
||||
cnt_roll => cnt_roll
|
||||
);
|
||||
|
||||
INST_2 : vhdl_bl4_cmd_fsm_0
|
||||
port map (
|
||||
clk => clk,
|
||||
clk90 => clk90,
|
||||
cmd_ack => cmd_ack,
|
||||
cnt_roll => cnt_roll,
|
||||
r_w => r_w,
|
||||
refresh_done => ar_done,
|
||||
rst90 => fpga_rst90,
|
||||
rst180 => fpga_rst180,
|
||||
init_val => init_done,
|
||||
addr_inc => addr_inc,
|
||||
addr_rst => addr_rst,
|
||||
u_cmd => u_cmd,
|
||||
data_rst => data_rst_w
|
||||
);
|
||||
|
||||
INST3 : vhdl_bl4_cmp_data_0
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
data_valid => data_valid,
|
||||
cmp_data => cmp_data_r,
|
||||
read_data => u_data_o,
|
||||
rst90 => fpga_rst90,
|
||||
led_error_output => led_error_output,
|
||||
data_valid_out => data_valid_out,
|
||||
dbg_cmp_data => dbg_cmp_data,
|
||||
dbg_led_error_output => dbg_led_error_output,
|
||||
dbg_data_valid_out => dbg_data_valid_out
|
||||
);
|
||||
|
||||
INST5 : vhdl_bl4_data_gen_0
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
rst90 => fpga_rst90,
|
||||
data_rst => data_rst_r,
|
||||
data_ena => data_ena_r,
|
||||
mask_data => cmp_data_m_r,
|
||||
data_out => cmp_data_r
|
||||
);
|
||||
|
||||
INST7 : vhdl_bl4_data_gen_0
|
||||
port map (
|
||||
clk90 => clk90,
|
||||
rst90 => fpga_rst90,
|
||||
data_rst => data_rst_w,
|
||||
data_ena => data_ena_w,
|
||||
mask_data => app_data_m_w0,
|
||||
data_out => app_data_w0
|
||||
);
|
||||
|
||||
end arc;
|
||||
374
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd
Executable file
374
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd
Executable file
@@ -0,0 +1,374 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_top_0.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This modules has the instantiations infrastructure, iobs,
|
||||
-- controller and data_paths modules
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_top_0 is
|
||||
port(
|
||||
wait_200us : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
|
||||
downto 0) := (others => 'Z');
|
||||
user_data_valid : out std_logic;
|
||||
user_input_address : in std_logic_vector(((ROW_ADDRESS +
|
||||
COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
|
||||
user_command_register : in std_logic_vector(2 downto 0);
|
||||
burst_done : in std_logic;
|
||||
auto_ref_req : out std_logic;
|
||||
user_cmd_ack : out std_logic;
|
||||
init_done : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
|
||||
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
:= (others => 'Z');
|
||||
ddr2_cke : out std_logic;
|
||||
ddr2_cs_n : out std_logic;
|
||||
ddr2_ras_n : out std_logic;
|
||||
ddr2_cas_n : out std_logic;
|
||||
ddr2_we_n : out std_logic;
|
||||
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr2_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
|
||||
clk_int : in std_logic;
|
||||
clk90_int : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
sys_rst : in std_logic;
|
||||
sys_rst90 : in std_logic;
|
||||
sys_rst180 : in std_logic;
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic;
|
||||
dbg_controller : out std_logic_vector(2 downto 0);
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
);
|
||||
|
||||
end vhdl_bl4_top_0;
|
||||
|
||||
architecture arc of vhdl_bl4_top_0 is
|
||||
|
||||
component vhdl_bl4_controller_0
|
||||
port(
|
||||
auto_ref_req : out std_logic;
|
||||
wait_200us : in std_logic;
|
||||
clk : in std_logic;
|
||||
rst0 : in std_logic;
|
||||
rst180 : in std_logic;
|
||||
address : in std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS)-1)
|
||||
downto 0);
|
||||
bank_addr : in std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
command_register : in std_logic_vector(2 downto 0);
|
||||
burst_done : in std_logic;
|
||||
ddr_rasb_cntrl : out std_logic;
|
||||
ddr_casb_cntrl : out std_logic;
|
||||
ddr_web_cntrl : out std_logic;
|
||||
ddr_ba_cntrl : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr_address_cntrl : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_cke_cntrl : out std_logic;
|
||||
ddr_csb_cntrl : out std_logic;
|
||||
ddr_ODT_cntrl : out std_logic;
|
||||
dqs_enable : out std_logic;
|
||||
dqs_reset : out std_logic;
|
||||
write_enable : out std_logic;
|
||||
rst_calib : out std_logic;
|
||||
rst_dqs_div_int : out std_logic;
|
||||
cmd_ack : out std_logic;
|
||||
init : out std_logic;
|
||||
ar_done : out std_logic;
|
||||
read_fifo_rden : out std_logic; -- Added new signal
|
||||
dbg_controller : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_data_path_0
|
||||
port(
|
||||
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
user_data_mask : in std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
reset : in std_logic;
|
||||
reset90 : in std_logic;
|
||||
write_enable : in std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
delay_sel : in std_logic_vector(4 downto 0);
|
||||
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
u_data_val : out std_logic;
|
||||
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
|
||||
write_en_val : out std_logic;
|
||||
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
read_fifo_rden : in std_logic; -- Added new signal
|
||||
-- debug singals
|
||||
vio_out_dqs : in std_logic_vector(4 downto 0);
|
||||
vio_out_dqs_en : in std_logic;
|
||||
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
|
||||
vio_out_rst_dqs_div_en : in std_logic
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_infrastructure
|
||||
port(
|
||||
clk_int : in std_logic;
|
||||
rst_calib1 : in std_logic;
|
||||
delay_sel_val : in std_logic_vector(4 downto 0);
|
||||
delay_sel_val1_val : out std_logic_vector(4 downto 0);
|
||||
-- debug signals
|
||||
dbg_delay_sel : out std_logic_vector(4 downto 0);
|
||||
dbg_rst_calib : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vhdl_bl4_iobs_0
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk90 : in std_logic;
|
||||
ddr_rasb_cntrl : in std_logic;
|
||||
ddr_casb_cntrl : in std_logic;
|
||||
ddr_web_cntrl : in std_logic;
|
||||
ddr_cke_cntrl : in std_logic;
|
||||
ddr_csb_cntrl : in std_logic;
|
||||
ddr_ODT_cntrl : in std_logic;
|
||||
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
rst_dqs_div_int : in std_logic;
|
||||
dqs_reset : in std_logic;
|
||||
dqs_enable : in std_logic;
|
||||
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
|
||||
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
write_en_val : in std_logic;
|
||||
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
ddr_odt : out std_logic;
|
||||
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
ddr_rasb : out std_logic;
|
||||
ddr_casb : out std_logic;
|
||||
ddr_web : out std_logic;
|
||||
ddr_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
ddr_address : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
ddr_cke : out std_logic;
|
||||
ddr_csb : out std_logic;
|
||||
rst_dqs_div : out std_logic;
|
||||
rst_dqs_div_in : in std_logic;
|
||||
rst_dqs_div_out : out std_logic;
|
||||
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_calib : std_logic;
|
||||
signal delay_sel : std_logic_vector(4 downto 0);
|
||||
signal write_enable : std_logic;
|
||||
signal dqs_div_rst : std_logic;
|
||||
signal dqs_enable : std_logic;
|
||||
signal dqs_reset : std_logic;
|
||||
signal dqs_int_delay_in : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal dq : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_en_val : std_logic;
|
||||
signal data_mask_f : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal data_mask_r : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
signal write_data_falling : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal write_data_rising : std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
signal ddr_rasb_cntrl : std_logic;
|
||||
signal ddr_casb_cntrl : std_logic;
|
||||
signal ddr_web_cntrl : std_logic;
|
||||
signal ddr_ba_cntrl : std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
signal ddr_address_cntrl : std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
signal ddr_cke_cntrl : std_logic;
|
||||
signal ddr_csb_cntrl : std_logic;
|
||||
signal ddr_odt_cntrl : std_logic;
|
||||
signal rst_dqs_div_int : std_logic;
|
||||
signal read_fifo_rden : std_logic;
|
||||
begin
|
||||
|
||||
|
||||
|
||||
|
||||
controller0 : vhdl_bl4_controller_0
|
||||
port map (
|
||||
auto_ref_req => auto_ref_req,
|
||||
wait_200us => wait_200us,
|
||||
clk => clk_int,
|
||||
rst0 => sys_rst,
|
||||
rst180 => sys_rst180,
|
||||
address => user_input_address(((ROW_ADDRESS + COLUMN_ADDRESS +
|
||||
BANK_ADDRESS)-1) downto BANK_ADDRESS),
|
||||
bank_addr => user_input_address(BANK_ADDRESS-1 downto 0),
|
||||
command_register => user_command_register,
|
||||
burst_done => burst_done,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_ba_cntrl => ddr_ba_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
dqs_enable => dqs_enable,
|
||||
dqs_reset => dqs_reset,
|
||||
write_enable => write_enable,
|
||||
rst_calib => rst_calib,
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
cmd_ack => user_cmd_ack,
|
||||
init => init_done,
|
||||
ar_done => ar_done,
|
||||
read_fifo_rden => read_fifo_rden, -- Added new signal
|
||||
dbg_controller => dbg_controller
|
||||
);
|
||||
|
||||
data_path0 : vhdl_bl4_data_path_0
|
||||
port map (
|
||||
user_input_data => user_input_data,
|
||||
user_data_mask => user_data_mask,
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
reset => sys_rst,
|
||||
reset90 => sys_rst90,
|
||||
write_enable => write_enable,
|
||||
rst_dqs_div_in => dqs_div_rst,
|
||||
delay_sel => delay_sel,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
dq => dq,
|
||||
u_data_val => user_data_valid,
|
||||
user_output_data => user_output_data,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
read_fifo_rden => read_fifo_rden, -- Added new signal
|
||||
--debug signals
|
||||
vio_out_dqs => vio_out_dqs,
|
||||
vio_out_dqs_en => vio_out_dqs_en,
|
||||
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
||||
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
||||
);
|
||||
|
||||
infrastructure0 : vhdl_bl4_infrastructure
|
||||
port map (
|
||||
clk_int => clk_int,
|
||||
rst_calib1 => rst_calib,
|
||||
delay_sel_val => delay_sel_val,
|
||||
delay_sel_val1_val => delay_sel,
|
||||
dbg_delay_sel => dbg_delay_sel,
|
||||
dbg_rst_calib => dbg_rst_calib
|
||||
);
|
||||
|
||||
iobs0 : vhdl_bl4_iobs_0
|
||||
port map (
|
||||
clk => clk_int,
|
||||
clk90 => clk90_int,
|
||||
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
||||
ddr_casb_cntrl => ddr_casb_cntrl,
|
||||
ddr_odt_cntrl => ddr_odt_cntrl,
|
||||
ddr_web_cntrl => ddr_web_cntrl,
|
||||
ddr_cke_cntrl => ddr_cke_cntrl,
|
||||
ddr_csb_cntrl => ddr_csb_cntrl,
|
||||
ddr_address_cntrl => ddr_address_cntrl,
|
||||
ddr_ba_cntrl => ddr_ba_cntrl,
|
||||
rst_dqs_div_int => rst_dqs_div_int,
|
||||
dqs_reset => dqs_reset,
|
||||
dqs_enable => dqs_enable,
|
||||
ddr_dqs => ddr2_dqs,
|
||||
ddr_dqs_n => ddr2_dqs_n,
|
||||
ddr_dq => ddr2_dq,
|
||||
write_data_falling => write_data_falling,
|
||||
write_data_rising => write_data_rising,
|
||||
write_en_val => write_en_val,
|
||||
data_mask_f => data_mask_f,
|
||||
data_mask_r => data_mask_r,
|
||||
ddr_odt => ddr2_odt,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n,
|
||||
ddr_rasb => ddr2_ras_n,
|
||||
ddr_casb => ddr2_cas_n,
|
||||
ddr_web => ddr2_we_n,
|
||||
ddr_ba => ddr2_ba,
|
||||
ddr_address => ddr2_a,
|
||||
ddr_cke => ddr2_cke,
|
||||
ddr_csb => ddr2_cs_n,
|
||||
rst_dqs_div => dqs_div_rst,
|
||||
rst_dqs_div_in => rst_dqs_div_in,
|
||||
rst_dqs_div_out => rst_dqs_div_out,
|
||||
dqs_int_delay_in => dqs_int_delay_in,
|
||||
ddr_dm => ddr2_dm,
|
||||
dq => dq
|
||||
);
|
||||
|
||||
end arc;
|
||||
139
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd
Executable file
139
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd
Executable file
@@ -0,0 +1,139 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.5
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : vhdl_bl4_wr_gray_cntr.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:10 $
|
||||
-- \ \ / \ Date Created : Mon May 2 2005
|
||||
-- \___\/\___\
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose :
|
||||
--*****************************************************************************
|
||||
-- fifo_wr_addr gray counter with synchronous reset
|
||||
-- Gray counter is used for FIFO address counter
|
||||
|
||||
library ieee;
|
||||
library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use UNISIM.VCOMPONENTS.all;
|
||||
|
||||
entity vhdl_bl4_wr_gray_cntr is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
cnt_en : in std_logic;
|
||||
wgc_gcnt : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end vhdl_bl4_wr_gray_cntr;
|
||||
|
||||
architecture arc of vhdl_bl4_wr_gray_cntr is
|
||||
|
||||
signal d_in : std_logic_vector(3 downto 0);
|
||||
signal gc_int : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
wgc_gcnt <= gc_int(3 downto 0);
|
||||
|
||||
process(gc_int)
|
||||
begin
|
||||
case gc_int is
|
||||
when "0000" => d_in <= "0001"; --0 > 1
|
||||
when "0001" => d_in <= "0011"; --1 > 3
|
||||
when "0010" => d_in <= "0110"; --2 > 6
|
||||
when "0011" => d_in <= "0010"; --3 > 2
|
||||
when "0100" => d_in <= "1100"; --4 > c
|
||||
when "0101" => d_in <= "0100"; --5 > 4
|
||||
when "0110" => d_in <= "0111"; --6 > 7
|
||||
when "0111" => d_in <= "0101"; --7 > 5
|
||||
when "1000" => d_in <= "0000"; --8 > 0
|
||||
when "1001" => d_in <= "1000"; --9 > 8
|
||||
when "1010" => d_in <= "1011"; --a > b
|
||||
when "1011" => d_in <= "1001"; --b > 9
|
||||
when "1100" => d_in <= "1101"; --c > d
|
||||
when "1101" => d_in <= "1111"; --d > f
|
||||
when "1110" => d_in <= "1010"; --e > a
|
||||
when "1111" => d_in <= "1110"; --f > e
|
||||
when others => d_in <= "0001"; --0 > 1
|
||||
end case;
|
||||
end process;
|
||||
|
||||
bit0 : FDCE
|
||||
port map (
|
||||
Q => gc_int(0),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(0)
|
||||
);
|
||||
|
||||
bit1 : FDCE
|
||||
port map (
|
||||
Q => gc_int(1),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(1)
|
||||
);
|
||||
|
||||
bit2 : FDCE
|
||||
port map (
|
||||
Q => gc_int(2),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(2)
|
||||
);
|
||||
|
||||
bit3 : FDCE
|
||||
port map (
|
||||
Q => gc_int(3),
|
||||
C => clk,
|
||||
CE => cnt_en,
|
||||
CLR => reset,
|
||||
D => d_in(3)
|
||||
);
|
||||
|
||||
end arc;
|
||||
1993
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
Executable file
1993
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
Executable file
File diff suppressed because it is too large
Load Diff
1089
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model_parameters.vh
Executable file
1089
ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model_parameters.vh
Executable file
File diff suppressed because it is too large
Load Diff
87
ddr2_sdram/vhdl_bl4/example_design/sim/glbl.v
Executable file
87
ddr2_sdram/vhdl_bl4/example_design/sim/glbl.v
Executable file
@@ -0,0 +1,87 @@
|
||||
//*****************************************************************************
|
||||
// DISCLAIMER OF LIABILITY
|
||||
//
|
||||
// This file contains proprietary and confidential information of
|
||||
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
// from Xilinx, and may be used, copied and/or disclosed only
|
||||
// pursuant to the terms of a valid license agreement with Xilinx.
|
||||
//
|
||||
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
// does not warrant that functions included in the Materials will
|
||||
// meet the requirements of Licensee, or that the operation of the
|
||||
// Materials will be uninterrupted or error-free, or that defects
|
||||
// in the Materials will be corrected. Furthermore, Xilinx does
|
||||
// not warrant or make any representations regarding use, or the
|
||||
// results of the use, of the Materials in terms of correctness,
|
||||
// accuracy, reliability or otherwise.
|
||||
//
|
||||
// Xilinx products are not designed or intended to be fail-safe,
|
||||
// or for use in any application requiring fail-safe performance,
|
||||
// such as life-support or safety devices or systems, Class III
|
||||
// medical devices, nuclear facilities, applications related to
|
||||
// the deployment of airbags, or any other applications that could
|
||||
// lead to death, personal injury or severe property or
|
||||
// environmental damage (individually and collectively, "critical
|
||||
// applications"). Customer assumes the sole risk and liability
|
||||
// of any use of Xilinx products in critical applications,
|
||||
// subject only to applicable laws and regulations governing
|
||||
// limitations on product liability.
|
||||
//
|
||||
// Copyright 2005, 2006 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// This disclaimer and copyright notice must be retained as part
|
||||
// of this file at all times.
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 3.3
|
||||
// \ \ Application : MIG
|
||||
// / / Filename : glbl.v
|
||||
// /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:57 $
|
||||
// \ \ / \ Date Created : Mon May 2 2005
|
||||
// \___\/\___\
|
||||
// Device : Spartan-3/3A/3A-DSP
|
||||
// Design Name : DDR2_SDRAM
|
||||
// Purpose : Used for intializing the simulation environment.
|
||||
//*****************************************************************************
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire PRLD;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
assign (weak1, weak0) GSR = GSR_int;
|
||||
assign (weak1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
118
ddr2_sdram/vhdl_bl4/example_design/sim/sim.do
Executable file
118
ddr2_sdram/vhdl_bl4/example_design/sim/sim.do
Executable file
@@ -0,0 +1,118 @@
|
||||
###############################################################################
|
||||
## DISCLAIMER OF LIABILITY
|
||||
##
|
||||
## This file contains proprietary and confidential information of
|
||||
## Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
## from Xilinx, and may be used, copied and/or disclosed only
|
||||
## pursuant to the terms of a valid license agreement with Xilinx.
|
||||
##
|
||||
## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
## does not warrant that functions included in the Materials will
|
||||
## meet the requirements of Licensee, or that the operation of the
|
||||
## Materials will be uninterrupted or error-free, or that defects
|
||||
## in the Materials will be corrected. Furthermore, Xilinx does
|
||||
## not warrant or make any representations regarding use, or the
|
||||
## results of the use, of the Materials in terms of correctness,
|
||||
## accuracy, reliability or otherwise.
|
||||
##
|
||||
## Xilinx products are not designed or intended to be fail-safe,
|
||||
## or for use in any application requiring fail-safe performance,
|
||||
## such as life-support or safety devices or systems, Class III
|
||||
## medical devices, nuclear facilities, applications related to
|
||||
## the deployment of airbags, or any other applications that could
|
||||
## lead to death, personal injury or severe property or
|
||||
## environmental damage (individually and collectively, "critical
|
||||
## applications"). Customer assumes the sole risk and liability
|
||||
## of any use of Xilinx products in critical applications,
|
||||
## subject only to applicable laws and regulations governing
|
||||
## limitations on product liability.
|
||||
##
|
||||
## Copyright 2007, 2008 Xilinx, Inc.
|
||||
## All rights reserved.
|
||||
##
|
||||
## This disclaimer and copyright notice must be retained as part
|
||||
## of this file at all times.
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 3.3
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : sim.do
|
||||
## /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:57 $
|
||||
## \ \ / \ Date Created : Mon May 14 2007
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device: Spartan-3/3A/3A-DSP
|
||||
## Design Name : DDR2 SDRAM
|
||||
## Purpose:
|
||||
## Sample sim .do file to compile and simulate memory interface
|
||||
## design and run the simulation for specified period of time. Display the
|
||||
## waveforms that are listed with "add wave" command.
|
||||
## Assumptions:
|
||||
## - Simulation takes place in \sim folder of MIG output directory
|
||||
## Reference:
|
||||
## Revision History:
|
||||
###############################################################################
|
||||
|
||||
vlib work
|
||||
#Map the required libraries here.#
|
||||
#Complie design parameter file first. This is required for VHDL designs which #
|
||||
#include a parameter file.#
|
||||
vcom ../rtl/*parameters*
|
||||
#Compile all modules#
|
||||
vcom ../rtl/*
|
||||
#Compile files in sim folder (excluding model parameter file)#
|
||||
vlog ../sim/*.v
|
||||
vcom ../sim/*.vhd
|
||||
#Pass the parameters for memory model parameter file#
|
||||
vlog +incdir+. +define+x512Mb +define+sg5E +define+x16 ddr2_model.v
|
||||
#Load the design. Use required libraries.#
|
||||
vsim -t ps -novopt +notimingchecks -L unisim work.sim_tb_top glbl
|
||||
onerror {resume}
|
||||
|
||||
#Log all the objects in design. These will appear in .wlf file#
|
||||
log -r /*
|
||||
#View sim_tb_top signals in waveform#
|
||||
add wave sim:/sim_tb_top/*
|
||||
#Change radix to Hexadecimal#
|
||||
radix hex
|
||||
#Supress Numeric Std package and Arith package warnings.#
|
||||
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
|
||||
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
|
||||
#We may also get some Arithmetic package warnings because of unknown values on#
|
||||
#some of the signals that are used in an Arithmetic operation.#
|
||||
#In order to suppress these warnings, we use following two commands#
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
#Choose simulation run time by inserting a breakpoint and then run for specified #
|
||||
#period. For more details, refer to Simulation Guide section of MIG user guide (UG086).#
|
||||
when {/sim_tb_top/init_done = 1} {
|
||||
if {[when -label a_100] == ""} {
|
||||
when -label a_100 { $now = 50 us } {
|
||||
nowhen a_100
|
||||
report simulator control
|
||||
report simulator state
|
||||
if {[examine /sim_tb_top/error] == 0} {
|
||||
echo "TEST PASSED"
|
||||
stop
|
||||
}
|
||||
if {[examine /sim_tb_top/error] != 0} {
|
||||
echo "TEST FAILED: DATA ERROR"
|
||||
stop
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#In case calibration fails to complete, choose the run time and then quit#
|
||||
when {$now = @500 us and /sim_tb_top/init_done != 1} {
|
||||
echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
|
||||
stop
|
||||
}
|
||||
run -all
|
||||
stop
|
||||
664
ddr2_sdram/vhdl_bl4/example_design/sim/sim_tb_top.vhd
Executable file
664
ddr2_sdram/vhdl_bl4/example_design/sim/sim_tb_top.vhd
Executable file
@@ -0,0 +1,664 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.3
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : sim_tb_top.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:57 $
|
||||
-- \ \ / \ Date Created : Mon May 14 2007
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : Spartan-3/3A/3A-DSP
|
||||
-- Design Name : DDR2 SDRAM
|
||||
-- Purpose : This is the simulation testbench which is used to verify the
|
||||
-- design. The basic clocks and resets to the interface are
|
||||
-- generated here. This also connects the memory interface to the
|
||||
-- memory model.
|
||||
--*****************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.vhdl_bl4_parameters_0.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity sim_tb_top is
|
||||
|
||||
end entity sim_tb_top;
|
||||
|
||||
architecture arch of sim_tb_top is
|
||||
|
||||
constant DEVICE_WIDTH : integer := 16; -- Memory device data width
|
||||
constant REG_ENABLE : integer := REGISTERED; -- registered addr/ctrl
|
||||
|
||||
constant TEMP1 : real := 7518.0 / 1000.0;
|
||||
constant TCYC_SYS : real := TEMP1/2.0;
|
||||
constant TCYC_SYS_0 : time := TEMP1 * 1 ns;
|
||||
constant TCYC_SYS_DIV2 : time := TCYC_SYS * 1 ns;
|
||||
constant TEMP2 : real := 5.0/2.0;
|
||||
constant TPROP_DQS : time := 0.00 ns; -- Delay for DQS signal during Write Operation
|
||||
constant TPROP_DQS_RD : time := 0.00 ns; -- Delay for DQS signal during Read Operation
|
||||
constant TPROP_PCB_CTRL : time := 0.00 ns; -- Delay for Address and Ctrl signals
|
||||
constant TPROP_PCB_DATA : time := 0.00 ns; -- Delay for data signal during Write operation
|
||||
constant TPROP_PCB_DATA_RD : time := 0.00 ns; -- Delay for data signal during Read operation
|
||||
|
||||
component vhdl_bl4
|
||||
port (
|
||||
reset_in_n : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
cntrl0_ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
|
||||
cntrl0_ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
|
||||
cntrl0_ddr2_ras_n : out std_logic;
|
||||
cntrl0_ddr2_cas_n : out std_logic;
|
||||
cntrl0_ddr2_we_n : out std_logic;
|
||||
cntrl0_ddr2_cs_n : out std_logic;
|
||||
cntrl0_ddr2_odt : out std_logic;
|
||||
cntrl0_ddr2_cke : out std_logic;
|
||||
cntrl0_ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
cntrl0_ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
|
||||
cntrl0_ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
|
||||
cntrl0_ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
cntrl0_ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
cntrl0_ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
|
||||
|
||||
cntrl0_led_error_output1 : out std_logic;
|
||||
cntrl0_data_valid_out : out std_logic;
|
||||
cntrl0_init_done : out std_logic;
|
||||
|
||||
cntrl0_rst_dqs_div_in : in std_logic;
|
||||
cntrl0_rst_dqs_div_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component ddr2_model
|
||||
port (
|
||||
ck : in std_logic;
|
||||
ck_n : in std_logic;
|
||||
cke : in std_logic;
|
||||
cs_n : in std_logic;
|
||||
ras_n : in std_logic;
|
||||
cas_n : in std_logic;
|
||||
we_n : in std_logic;
|
||||
dm_rdqs : inout std_logic_vector((DEVICE_WIDTH/16) downto 0);
|
||||
ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);
|
||||
addr : in std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
dq : inout std_logic_vector((DEVICE_WIDTH - 1) downto 0);
|
||||
dqs : inout std_logic_vector((DEVICE_WIDTH/16) downto 0);
|
||||
dqs_n : inout std_logic_vector((DEVICE_WIDTH/16) downto 0);
|
||||
rdqs_n : out std_logic_vector((DEVICE_WIDTH/16) downto 0);
|
||||
odt : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component WireDelay
|
||||
generic (
|
||||
Delay_g : time;
|
||||
Delay_rd : time);
|
||||
port (
|
||||
A : inout Std_Logic;
|
||||
B : inout Std_Logic;
|
||||
reset : in Std_Logic);
|
||||
end component;
|
||||
|
||||
|
||||
signal sys_clk : std_logic := '0';
|
||||
signal sys_clk_n : std_logic;
|
||||
signal sys_clk_p : std_logic;
|
||||
signal sys_clk200 : std_logic := '0';
|
||||
signal sys_rst_n : std_logic := '0';
|
||||
signal sys_rst_out : std_logic;
|
||||
signal ddr2_dq_sdram : std_logic_vector((DATA_WIDTH - 1) downto 0);
|
||||
signal ddr2_dqs_sdram : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal ddr2_dqs_n_sdram : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);-- this
|
||||
signal ddr2_dm_sdram : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
|
||||
signal ddr2_clk_sdram : std_logic_vector((CLK_WIDTH - 1) downto 0);
|
||||
signal ddr2_clk_n_sdram : std_logic_vector((CLK_WIDTH - 1) downto 0);
|
||||
signal ddr2_address_sdram : std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
signal ddr2_ba_sdram : std_logic_vector((BANK_ADDRESS - 1) downto 0);
|
||||
signal ddr2_ras_n_sdram : std_logic;
|
||||
signal ddr2_cas_n_sdram : std_logic;
|
||||
signal ddr2_we_n_sdram : std_logic;
|
||||
signal ddr2_cs_n_sdram : std_logic;
|
||||
signal ddr2_cke_sdram : std_logic;
|
||||
signal ddr2_odt_sdram : std_logic;
|
||||
signal error : std_logic;
|
||||
signal init_done : std_logic;
|
||||
|
||||
-- Only RDIMM memory parts support the reset signal,
|
||||
-- hence the ddr2_reset_n_sdram and ddr2_reset_n_fpga signals can be
|
||||
-- ignored for other memory parts
|
||||
signal ddr2_reset_n_sdram : std_logic;
|
||||
signal ddr2_reset_n_fpga : std_logic;
|
||||
|
||||
signal ddr2_address_reg : std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
signal ddr2_ba_reg : std_logic_vector((BANK_ADDRESS - 1) downto 0);
|
||||
signal ddr2_cke_reg : std_logic;
|
||||
signal ddr2_ras_n_reg : std_logic;
|
||||
signal ddr2_cas_n_reg : std_logic;
|
||||
signal ddr2_we_n_reg : std_logic;
|
||||
signal ddr2_cs_n_reg : std_logic;
|
||||
signal ddr2_odt_reg : std_logic;
|
||||
|
||||
--below signals will be driven only in case of component or unbuffered
|
||||
--and data_width not multiple of 16 and selected component width is x16
|
||||
signal dq_vector : std_logic_vector(15 downto 0);
|
||||
signal dqs_vector : std_logic_vector(1 downto 0);
|
||||
signal dqs_n_vector : std_logic_vector(1 downto 0);
|
||||
signal dm_vector : std_logic_vector(1 downto 0);
|
||||
signal command : std_logic_vector(2 downto 0);
|
||||
signal enable : std_logic;
|
||||
signal enable_o : std_logic;
|
||||
|
||||
signal command1 : std_logic_vector(2 downto 0);
|
||||
signal enable1 : std_logic;
|
||||
signal enable2 : std_logic;
|
||||
signal ddr2_dq_fpga : std_logic_vector((DATA_WIDTH - 1) downto 0);
|
||||
signal ddr2_dqs_fpga : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal ddr2_dqs_n_fpga : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
|
||||
signal ddr2_dm_fpga : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
|
||||
signal ddr2_clk_fpga : std_logic_vector((CLK_WIDTH - 1) downto 0);
|
||||
signal ddr2_clk_n_fpga : std_logic_vector((CLK_WIDTH - 1) downto 0);
|
||||
signal ddr2_address_fpga : std_logic_vector((ROW_ADDRESS - 1) downto 0);
|
||||
signal ddr2_ba_fpga : std_logic_vector((BANK_ADDRESS - 1) downto 0);
|
||||
signal ddr2_ras_n_fpga : std_logic;
|
||||
signal ddr2_cas_n_fpga : std_logic;
|
||||
signal ddr2_we_n_fpga : std_logic;
|
||||
signal ddr2_cs_n_fpga : std_logic;
|
||||
signal ddr2_cke_fpga : std_logic;
|
||||
signal ddr2_odt_fpga : std_logic;
|
||||
signal data_valid_out : std_logic;
|
||||
signal ddr2_dm_8_16 : std_logic_vector(1 downto 0);-- this signal will be driven only for x16 components
|
||||
signal rst_dqs_div_loop : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Clock generation and reset
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
process
|
||||
begin
|
||||
sys_clk <= not sys_clk;
|
||||
wait for (TCYC_SYS_DIV2);
|
||||
end process;
|
||||
|
||||
sys_clk_p <= sys_clk;
|
||||
sys_clk_n <= not sys_clk;
|
||||
|
||||
process
|
||||
begin
|
||||
sys_rst_n <= '0';
|
||||
wait for 200 ns;
|
||||
sys_rst_n <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
sys_rst_out <= (sys_rst_n) when (RESET_ACTIVE_LOW = '1') else (not sys_rst_n);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- FPGA memory controller
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
u_mem_controller : vhdl_bl4
|
||||
port map (
|
||||
sys_clk_in => sys_clk_p,
|
||||
reset_in_n => sys_rst_out,
|
||||
cntrl0_ddr2_ras_n => ddr2_ras_n_fpga,
|
||||
cntrl0_ddr2_cas_n => ddr2_cas_n_fpga,
|
||||
cntrl0_ddr2_we_n => ddr2_we_n_fpga,
|
||||
cntrl0_ddr2_cs_n => ddr2_cs_n_fpga,
|
||||
cntrl0_ddr2_cke => ddr2_cke_fpga,
|
||||
cntrl0_ddr2_odt => ddr2_odt_fpga,
|
||||
cntrl0_ddr2_dm => ddr2_dm_fpga,
|
||||
cntrl0_ddr2_dq => ddr2_dq_fpga,
|
||||
cntrl0_ddr2_dqs => ddr2_dqs_fpga,
|
||||
cntrl0_ddr2_dqs_n => ddr2_dqs_n_fpga,
|
||||
cntrl0_ddr2_ck => ddr2_clk_fpga,
|
||||
cntrl0_ddr2_ck_n => ddr2_clk_n_fpga,
|
||||
cntrl0_ddr2_ba => ddr2_ba_fpga,
|
||||
cntrl0_ddr2_a => ddr2_address_fpga,
|
||||
cntrl0_led_error_output1 => error,
|
||||
cntrl0_data_valid_out => data_valid_out,
|
||||
cntrl0_init_done => init_done,
|
||||
cntrl0_rst_dqs_div_in => rst_dqs_div_loop,
|
||||
cntrl0_rst_dqs_div_out => rst_dqs_div_loop
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Delay insertion modules for each signal
|
||||
-- Use standard non-inertial (transport) delay mechanism for unidirectional
|
||||
-- signals from FPGA to SDRAM
|
||||
-----------------------------------------------------------------------------
|
||||
ddr2_address_sdram <= TRANSPORT ddr2_address_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_ba_sdram <= TRANSPORT ddr2_ba_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_ras_n_sdram <= TRANSPORT ddr2_ras_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_cas_n_sdram <= TRANSPORT ddr2_cas_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_we_n_sdram <= TRANSPORT ddr2_we_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_cs_n_sdram <= TRANSPORT ddr2_cs_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_cke_sdram <= TRANSPORT ddr2_cke_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_odt_sdram <= TRANSPORT ddr2_odt_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_clk_sdram <= TRANSPORT ddr2_clk_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_clk_n_sdram <= TRANSPORT ddr2_clk_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_reset_n_sdram <= TRANSPORT ddr2_reset_n_fpga after TPROP_PCB_CTRL;
|
||||
ddr2_dm_sdram <= TRANSPORT ddr2_dm_fpga after TPROP_PCB_DATA;
|
||||
|
||||
dq_delay: for i in 0 to DATA_WIDTH - 1 generate
|
||||
u_delay_dq: WireDelay
|
||||
generic map (
|
||||
Delay_g => TPROP_PCB_DATA,
|
||||
Delay_rd => TPROP_PCB_DATA_RD)
|
||||
port map(
|
||||
A => ddr2_dq_fpga(i),
|
||||
B => ddr2_dq_sdram(i),
|
||||
reset => sys_rst_n);
|
||||
end generate;
|
||||
|
||||
dqs_delay: for i in 0 to DATA_STROBE_WIDTH - 1 generate
|
||||
u_delay_dqs: WireDelay
|
||||
generic map (
|
||||
Delay_g => TPROP_DQS,
|
||||
Delay_rd => TPROP_DQS_RD)
|
||||
port map(
|
||||
A => ddr2_dqs_fpga(i),
|
||||
B => ddr2_dqs_sdram(i),
|
||||
reset => sys_rst_n);
|
||||
end generate;
|
||||
|
||||
dqs_n_delay: for i in 0 to DATA_STROBE_WIDTH - 1 generate
|
||||
u_delay_dqs: WireDelay
|
||||
generic map (
|
||||
Delay_g => TPROP_DQS,
|
||||
Delay_rd => TPROP_DQS_RD)
|
||||
port map(
|
||||
A => ddr2_dqs_n_fpga(i),
|
||||
B => ddr2_dqs_n_sdram(i),
|
||||
reset => sys_rst_n);
|
||||
end generate;
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Extra one clock pipelining for RDIMM address and
|
||||
-- control signals is implemented here (Implemented external to memory model)
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
process (ddr2_clk_sdram)
|
||||
begin
|
||||
if (rising_edge(ddr2_clk_sdram(0))) then
|
||||
if ( ddr2_reset_n_sdram = '0' ) then
|
||||
ddr2_ras_n_reg <= '1';
|
||||
ddr2_cas_n_reg <= '1';
|
||||
ddr2_we_n_reg <= '1';
|
||||
ddr2_cs_n_reg <= '1';
|
||||
ddr2_odt_reg <= '0';
|
||||
else
|
||||
ddr2_address_reg <= TRANSPORT ddr2_address_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_ba_reg <= TRANSPORT ddr2_ba_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_ras_n_reg <= TRANSPORT ddr2_ras_n_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_cas_n_reg <= TRANSPORT ddr2_cas_n_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_we_n_reg <= TRANSPORT ddr2_we_n_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_cs_n_reg <= TRANSPORT ddr2_cs_n_sdram after TCYC_SYS_DIV2;
|
||||
ddr2_odt_reg <= TRANSPORT ddr2_odt_sdram after TCYC_SYS_DIV2;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- To avoid tIS violations on CKE when reset is deasserted
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
process (ddr2_clk_n_sdram)
|
||||
begin
|
||||
if (rising_edge(ddr2_clk_n_sdram(0))) then
|
||||
if ( ddr2_reset_n_sdram = '0' ) then
|
||||
ddr2_cke_reg <= '0';
|
||||
else
|
||||
ddr2_cke_reg <= TRANSPORT ddr2_cke_sdram after TCYC_SYS_0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Memory model instances
|
||||
-----------------------------------------------------------------------------
|
||||
comp_16 : if (DEVICE_WIDTH = 16) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if memory part is x16
|
||||
-----------------------------------------------------------------------------
|
||||
registered_dimm : if (REG_ENABLE = 1) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is Registered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes : for i in 0 to (DATA_STROBE_WIDTH/2 - 1) generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
ck_n => ddr2_clk_n_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
cke => ddr2_cke_reg,
|
||||
cs_n => ddr2_cs_n_reg,
|
||||
ras_n => ddr2_ras_n_reg,
|
||||
cas_n => ddr2_cas_n_reg,
|
||||
we_n => ddr2_we_n_reg,
|
||||
dm_rdqs => ddr2_dm_sdram((2*(i+1))-1 downto i*2),
|
||||
ba => ddr2_ba_reg,
|
||||
addr => ddr2_address_reg,
|
||||
dq => ddr2_dq_sdram((16*(i+1))-1 downto i*16),
|
||||
dqs => ddr2_dqs_sdram((2*(i+1))-1 downto i*2),
|
||||
dqs_n => ddr2_dqs_n_sdram((2*(i+1))-1 downto i*2),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_reg
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate registered_dimm;
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is component or unbuffered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
comp16_mul8 : if (((DATA_WIDTH mod 16) /= 0) and (REG_ENABLE = 0)) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- for the memory part x16, if the data width is not multiple
|
||||
-- of 16, memory models are instantiated for all data with x16
|
||||
-- memory model and except for MSB data. For the MSB data
|
||||
-- of 8 bits, all memory data, strobe and mask data signals are
|
||||
-- replicated to make it as x16 part. For example if the design
|
||||
-- is generated for data width of 72, memory model x16 parts
|
||||
-- instantiated for 4 times with data ranging from 0 to 63.
|
||||
-- For MSB data ranging from 64 to 71, one x16 memory model
|
||||
-- by replicating the 8-bit data twice and similarly
|
||||
-- the case with data mask and strobe.
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes : for i in 0 to (DATA_WIDTH/16 - 1) generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(i),
|
||||
ck_n => ddr2_clk_n_sdram(i),
|
||||
cke => ddr2_cke_sdram,
|
||||
cs_n => ddr2_cs_n_sdram,
|
||||
ras_n => ddr2_ras_n_sdram,
|
||||
cas_n => ddr2_cas_n_sdram,
|
||||
we_n => ddr2_we_n_sdram,
|
||||
dm_rdqs => ddr2_dm_sdram((2*(i+1))-1 downto i*2),
|
||||
ba => ddr2_ba_sdram,
|
||||
addr => ddr2_address_sdram,
|
||||
dq => ddr2_dq_sdram((16*(i+1))-1 downto i*16),
|
||||
dqs => ddr2_dqs_sdram((2*(i+1))-1 downto i*2),
|
||||
dqs_n => ddr2_dqs_n_sdram((2*(i+1))-1 downto i*2),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_sdram
|
||||
);
|
||||
end generate gen_bytes;
|
||||
-----------------------------------------------------------------------------
|
||||
--Logic to assign the remaining bits of DQ and DQS
|
||||
-----------------------------------------------------------------------------
|
||||
command <= (ddr2_ras_n_fpga & ddr2_cas_n_fpga & ddr2_we_n_fpga);
|
||||
|
||||
process(ddr2_clk_fpga)
|
||||
begin
|
||||
if (rising_edge(ddr2_clk_fpga(0))) then
|
||||
if (sys_rst_n = '0') then
|
||||
enable <= '0';
|
||||
enable_o <= '0';
|
||||
elsif (command = "100") then
|
||||
enable_o <= '0';
|
||||
elsif (command = "101") then
|
||||
enable_o <= '1';
|
||||
else
|
||||
enable_o <= enable_o;
|
||||
end if;
|
||||
enable <= enable_o;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
--read
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
ddr2_dq_sdram(DATA_WIDTH - 1 downto DATA_WIDTH - 8) <= dq_vector(7 downto 0)
|
||||
when enable = '1'
|
||||
else "ZZZZZZZZ";
|
||||
ddr2_dqs_sdram(DATA_STROBE_WIDTH - 1) <= dqs_vector(0)
|
||||
when enable = '1'
|
||||
else 'Z';
|
||||
ddr2_dqs_n_sdram(DATA_STROBE_WIDTH - 1) <= dqs_n_vector(0)
|
||||
when enable = '1'
|
||||
else 'Z';
|
||||
ddr2_dm_sdram(DATA_MASK_WIDTH - 1) <= dm_vector(0)
|
||||
when enable = '1'
|
||||
else 'Z';
|
||||
-----------------------------------------------------------------------------
|
||||
--write
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
dq_vector(7 downto 0) <= ddr2_dq_sdram(DATA_WIDTH - 1 downto DATA_WIDTH - 8)
|
||||
when (enable_o = '0' and enable = '0')
|
||||
else "ZZZZZZZZ";
|
||||
dqs_vector(0) <= ddr2_dqs_sdram(DATA_STROBE_WIDTH - 1)
|
||||
when (enable_o = '0' and enable = '0') else 'Z';
|
||||
dqs_n_vector(0) <= ddr2_dqs_n_sdram(DATA_STROBE_WIDTH - 1)
|
||||
when (enable_o = '0' and enable = '0') else 'Z';
|
||||
dm_vector(0) <= ddr2_dm_sdram(DATA_MASK_WIDTH - 1)
|
||||
when enable_o = '0' else 'Z';
|
||||
|
||||
dq_vector(15 downto 8) <= dq_vector(7 downto 0);
|
||||
dqs_vector(1) <= dqs_vector(0);
|
||||
dqs_n_vector(1) <= dqs_n_vector(0);
|
||||
ddr2_dm_8_16 <= ddr2_dm_sdram(DATA_MASK_WIDTH - 1) & ddr2_dm_sdram(DATA_MASK_WIDTH - 1);
|
||||
|
||||
|
||||
u_mem1 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(CLK_WIDTH-1),
|
||||
ck_n => ddr2_clk_n_sdram(CLK_WIDTH-1),
|
||||
cke => ddr2_cke_sdram,
|
||||
cs_n => ddr2_cs_n_sdram,
|
||||
ras_n => ddr2_ras_n_sdram,
|
||||
cas_n => ddr2_cas_n_sdram,
|
||||
we_n => ddr2_we_n_sdram,
|
||||
dm_rdqs => ddr2_dm_8_16,
|
||||
ba => ddr2_ba_sdram,
|
||||
addr => ddr2_address_sdram,
|
||||
dq => dq_vector,
|
||||
dqs => dqs_vector,
|
||||
dqs_n => dqs_n_vector,
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_sdram
|
||||
);
|
||||
end generate comp16_mul8;
|
||||
|
||||
comp16_mul16 : if (((DATA_WIDTH mod 16) = 0) and (REG_ENABLE = 0)) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the data width is multiple of 16
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes : for i in 0 to ((DATA_STROBE_WIDTH/2) - 1) generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(i),
|
||||
ck_n => ddr2_clk_n_sdram(i),
|
||||
cke => ddr2_cke_sdram,
|
||||
cs_n => ddr2_cs_n_sdram,
|
||||
ras_n => ddr2_ras_n_sdram,
|
||||
cas_n => ddr2_cas_n_sdram,
|
||||
we_n => ddr2_we_n_sdram,
|
||||
dm_rdqs => ddr2_dm_sdram((2*(i+1))-1 downto i*2),
|
||||
ba => ddr2_ba_sdram,
|
||||
addr => ddr2_address_sdram,
|
||||
dq => ddr2_dq_sdram((16*(i+1))-1 downto i*16),
|
||||
dqs => ddr2_dqs_sdram((2*(i+1))-1 downto i*2),
|
||||
dqs_n => ddr2_dqs_n_sdram((2*(i+1))-1 downto i*2),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_sdram
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate comp16_mul16;
|
||||
end generate comp_16;
|
||||
|
||||
comp_8 : if (DEVICE_WIDTH = 8) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is x8
|
||||
-----------------------------------------------------------------------------
|
||||
registered_dimm : if (REG_ENABLE = 1) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is Registered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes : for i in 0 to (DATA_STROBE_WIDTH - 1) generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
ck_n => ddr2_clk_n_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
cke => ddr2_cke_reg,
|
||||
cs_n => ddr2_cs_n_reg,
|
||||
ras_n => ddr2_ras_n_reg,
|
||||
cas_n => ddr2_cas_n_reg,
|
||||
we_n => ddr2_we_n_reg,
|
||||
dm_rdqs => ddr2_dm_sdram(i downto i),
|
||||
ba => ddr2_ba_reg,
|
||||
addr => ddr2_address_reg,
|
||||
dq => ddr2_dq_sdram((8*(i+1))-1 downto i*8),
|
||||
dqs => ddr2_dqs_sdram(i downto i),
|
||||
dqs_n => ddr2_dqs_n_sdram(i downto i),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_reg
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate registered_dimm;
|
||||
comp8_mul8 : if (REG_ENABLE = 0) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is component or unbuffered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes: for i in 0 to DATA_STROBE_WIDTH - 1 generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(i),
|
||||
ck_n => ddr2_clk_n_sdram(i),
|
||||
cke => ddr2_cke_sdram,
|
||||
cs_n => ddr2_cs_n_sdram,
|
||||
ras_n => ddr2_ras_n_sdram,
|
||||
cas_n => ddr2_cas_n_sdram,
|
||||
we_n => ddr2_we_n_sdram,
|
||||
dm_rdqs => ddr2_dm_sdram(i downto i),
|
||||
ba => ddr2_ba_sdram,
|
||||
addr => ddr2_address_sdram,
|
||||
dq => ddr2_dq_sdram((8*(i+1))-1 downto i*8),
|
||||
dqs => ddr2_dqs_sdram(i downto i),
|
||||
dqs_n => ddr2_dqs_n_sdram(i downto i),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_sdram
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate comp8_mul8;
|
||||
end generate comp_8;
|
||||
|
||||
comp_4 : if (DEVICE_WIDTH = 4) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is x4
|
||||
-----------------------------------------------------------------------------
|
||||
registered_dimm : if (REG_ENABLE = 1) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is Registered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes : for i in 0 to (DATA_STROBE_WIDTH - 1) generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
ck_n => ddr2_clk_n_sdram(CLK_WIDTH*i/DATA_STROBE_WIDTH),
|
||||
cke => ddr2_cke_reg,
|
||||
cs_n => ddr2_cs_n_reg,
|
||||
ras_n => ddr2_ras_n_reg,
|
||||
cas_n => ddr2_cas_n_reg,
|
||||
we_n => ddr2_we_n_reg,
|
||||
dm_rdqs => ddr2_dm_sdram(i/2 downto i/2),
|
||||
ba => ddr2_ba_reg,
|
||||
addr => ddr2_address_reg,
|
||||
dq => ddr2_dq_sdram((4*(i+1))-1 downto i*4),
|
||||
dqs => ddr2_dqs_sdram(i downto i),
|
||||
dqs_n => ddr2_dqs_n_sdram(i downto i),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_reg
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate registered_dimm;
|
||||
comp4_mul4 : if (REG_ENABLE = 0) generate
|
||||
-----------------------------------------------------------------------------
|
||||
-- if the memory part is component or unbuffered DIMM
|
||||
-----------------------------------------------------------------------------
|
||||
gen_bytes: for i in 0 to DATA_STROBE_WIDTH - 1 generate
|
||||
|
||||
u_mem0 : ddr2_model
|
||||
port map (
|
||||
ck => ddr2_clk_sdram(i),
|
||||
ck_n => ddr2_clk_n_sdram(i),
|
||||
cke => ddr2_cke_sdram,
|
||||
cs_n => ddr2_cs_n_sdram,
|
||||
ras_n => ddr2_ras_n_sdram,
|
||||
cas_n => ddr2_cas_n_sdram,
|
||||
we_n => ddr2_we_n_sdram,
|
||||
dm_rdqs => ddr2_dm_sdram(i/2 downto i/2),
|
||||
ba => ddr2_ba_sdram,
|
||||
addr => ddr2_address_sdram,
|
||||
dq => ddr2_dq_sdram((4*(i+1))-1 downto i*4),
|
||||
dqs => ddr2_dqs_sdram(i downto i),
|
||||
dqs_n => ddr2_dqs_n_sdram(i downto i),
|
||||
rdqs_n => open,
|
||||
odt => ddr2_odt_sdram
|
||||
);
|
||||
end generate gen_bytes;
|
||||
end generate comp4_mul4;
|
||||
end generate comp_4;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- synthesizable test bench provided for wotb designs
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
end architecture;
|
||||
133
ddr2_sdram/vhdl_bl4/example_design/sim/wiredly.vhd
Executable file
133
ddr2_sdram/vhdl_bl4/example_design/sim/wiredly.vhd
Executable file
@@ -0,0 +1,133 @@
|
||||
--*****************************************************************************
|
||||
-- DISCLAIMER OF LIABILITY
|
||||
--
|
||||
-- This file contains proprietary and confidential information of
|
||||
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
||||
-- from Xilinx, and may be used, copied and/or disclosed only
|
||||
-- pursuant to the terms of a valid license agreement with Xilinx.
|
||||
--
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
||||
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
||||
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
||||
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
||||
-- does not warrant that functions included in the Materials will
|
||||
-- meet the requirements of Licensee, or that the operation of the
|
||||
-- Materials will be uninterrupted or error-free, or that defects
|
||||
-- in the Materials will be corrected. Furthermore, Xilinx does
|
||||
-- not warrant or make any representations regarding use, or the
|
||||
-- results of the use, of the Materials in terms of correctness,
|
||||
-- accuracy, reliability or otherwise.
|
||||
--
|
||||
-- Xilinx products are not designed or intended to be fail-safe,
|
||||
-- or for use in any application requiring fail-safe performance,
|
||||
-- such as life-support or safety devices or systems, Class III
|
||||
-- medical devices, nuclear facilities, applications related to
|
||||
-- the deployment of airbags, or any other applications that could
|
||||
-- lead to death, personal injury or severe property or
|
||||
-- environmental damage (individually and collectively, "critical
|
||||
-- applications"). Customer assumes the sole risk and liability
|
||||
-- of any use of Xilinx products in critical applications,
|
||||
-- subject only to applicable laws and regulations governing
|
||||
-- limitations on product liability.
|
||||
--
|
||||
-- Copyright 2007, 2008 Xilinx, Inc.
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- This disclaimer and copyright notice must be retained as part
|
||||
-- of this file at all times.
|
||||
--*****************************************************************************
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 3.3
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : wiredly.vhd
|
||||
-- /___/ /\ Date Last Modified : $Date: 2008/12/20 12:05:58 $
|
||||
-- \ \ / \ Date Created : Mon Jun 18 2007
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : SPARTAN
|
||||
-- Design Name : DDR2
|
||||
-- Description: This module provide
|
||||
-- the definition of a zero ohm component (A, B).
|
||||
--
|
||||
-- The applications of this component include:
|
||||
-- . Normal operation of a jumper wire (data flowing in both directions)
|
||||
--
|
||||
-- The component consists of 2 ports:
|
||||
-- . Port A: One side of the pass-through switch
|
||||
-- . Port B: The other side of the pass-through switch
|
||||
|
||||
-- The model is sensitive to transactions on all ports. Once a
|
||||
-- transaction is detected, all other transactions are ignored
|
||||
-- for that simulation time (i.e. further transactions in that
|
||||
-- delta time are ignored).
|
||||
--
|
||||
-- Model Limitations and Restrictions:
|
||||
-- Signals asserted on the ports of the error injector should not have
|
||||
-- transactions occuring in multiple delta times because the model
|
||||
-- is sensitive to transactions on port A, B ONLY ONCE during
|
||||
-- a simulation time. Thus, once fired, a process will
|
||||
-- not refire if there are multiple transactions occuring in delta times.
|
||||
-- This condition may occur in gate level simulations with
|
||||
-- ZERO delays because transactions may occur in multiple delta times.
|
||||
--*****************************************************************************
|
||||
|
||||
library IEEE;
|
||||
use IEEE.Std_Logic_1164.all;
|
||||
|
||||
entity WireDelay is
|
||||
generic (
|
||||
Delay_g : time;
|
||||
Delay_rd : time);
|
||||
port
|
||||
(A : inout Std_Logic;
|
||||
B : inout Std_Logic;
|
||||
reset : in Std_Logic
|
||||
);
|
||||
end WireDelay;
|
||||
|
||||
|
||||
architecture WireDelay_a of WireDelay is
|
||||
|
||||
signal A_r : Std_Logic;
|
||||
signal B_r : Std_Logic;
|
||||
signal line_en : Std_Logic;
|
||||
|
||||
begin
|
||||
|
||||
A <= A_r;
|
||||
B <= B_r;
|
||||
|
||||
ABC0_Lbl: process (reset, A, B)
|
||||
begin
|
||||
if (reset = '0') then
|
||||
line_en <= '0';
|
||||
else
|
||||
if (A /= A_r) then
|
||||
line_en <= '0';
|
||||
elsif (B_r /= B) then
|
||||
line_en <= '1';
|
||||
else
|
||||
line_en <= line_en;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process ABC0_Lbl;
|
||||
|
||||
lnenab: process (reset, line_en, A, B)
|
||||
begin
|
||||
if (reset = '0') then
|
||||
A_r <= 'Z';
|
||||
B_r <= 'Z';
|
||||
elsif (line_en = '1') then
|
||||
A_r <= TRANSPORT B AFTER Delay_rd;
|
||||
B_r <= 'Z';
|
||||
else
|
||||
B_r <= TRANSPORT A AFTER Delay_g;
|
||||
A_r <= 'Z';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end WireDelay_a;
|
||||
46
ddr2_sdram/vhdl_bl4/example_design/synth/mem_interface_top_synp.sdc
Executable file
46
ddr2_sdram/vhdl_bl4/example_design/synth/mem_interface_top_synp.sdc
Executable file
@@ -0,0 +1,46 @@
|
||||
# Synplicity, Inc. constraint file
|
||||
# Written on Mon Jun 27 15:50:39 2005
|
||||
|
||||
define_global_attribute syn_global_buffers {2}
|
||||
define_attribute {v:work.vhdl_bl4_parameters_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_addr_gen_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_cal_ctl} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_cal_top} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_clk_dcm} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_cmd_fsm_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_cmp_data_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_controller_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_controller_iobs_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_gen_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_path_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_path_iobs_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_read_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_read_controller_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_data_write_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_dqs_delay_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_fifo_0_wr_en_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_fifo_1_wr_en_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_infrastructure} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_infrastructure_iobs_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_infrastructure_top} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_iobs_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_main_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_ram8d_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_rd_gray_cntr} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_s3_dm_iob} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_s3_dq_iob} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_s3_dqs_iob} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_tap_dly} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_test_bench_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_top_0} syn_hier {hard}
|
||||
define_attribute {v:work.vhdl_bl4_wr_gray_cntr} syn_hier {hard}
|
||||
|
||||
|
||||
# clock Constraints
|
||||
|
||||
define_clock -disable -name {clk_dcm0} -period 7.52 -clockgroup default_clkgroup_2
|
||||
define_clock -name {infrastructure_top0.lvds_clk_input} -period 7.52 -clockgroup default_clkgroup_3
|
||||
define_clock -disable -name {DCM_INST1} -period 7.52 -clockgroup default_clkgroup_4
|
||||
|
||||
|
||||
65
ddr2_sdram/vhdl_bl4/example_design/synth/script_synp.tcl
Executable file
65
ddr2_sdram/vhdl_bl4/example_design/synth/script_synp.tcl
Executable file
@@ -0,0 +1,65 @@
|
||||
project -new
|
||||
add_file -vhdl "../rtl/vhdl_bl4_parameters_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_addr_gen_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_cal_ctl.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_cal_top.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_clk_dcm.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_cmd_fsm_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_cmp_data_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_controller_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_controller_iobs_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_gen_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_path_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_path_iobs_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_read_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_read_controller_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_data_write_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_dqs_delay_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_fifo_0_wr_en_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_fifo_1_wr_en_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_infrastructure.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_infrastructure_iobs_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_infrastructure_top.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_iobs_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_main_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_ram8d_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_rd_gray_cntr.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_s3_dm_iob.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_s3_dq_iob.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_s3_dqs_iob.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_tap_dly.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_test_bench_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_top_0.vhd"
|
||||
add_file -vhdl "../rtl/vhdl_bl4_wr_gray_cntr.vhd"
|
||||
add_file -constraint "../synth/mem_interface_top_synp.sdc"
|
||||
impl -add rev_1
|
||||
set_option -technology spartan3a
|
||||
set_option -part xc3s700a
|
||||
set_option -package fg484
|
||||
set_option -speed_grade -4
|
||||
set_option -default_enum_encoding default
|
||||
set_option -symbolic_fsm_compiler 1
|
||||
set_option -resource_sharing 0
|
||||
set_option -use_fsm_explorer 0
|
||||
set_option -top_module "vhdl_bl4"
|
||||
set_option -frequency 133
|
||||
set_option -fanout_limit 1000
|
||||
set_option -disable_io_insertion 0
|
||||
set_option -pipe 1
|
||||
set_option -fixgatedclocks 0
|
||||
set_option -retiming 0
|
||||
set_option -modular 0
|
||||
set_option -update_models_cp 0
|
||||
set_option -verification_mode 0
|
||||
set_option -write_verilog 0
|
||||
set_option -write_vhdl 0
|
||||
set_option -write_apr_constraint 0
|
||||
project -result_file "../synth/rev_1/vhdl_bl4.edf"
|
||||
set_option -vlog_std v2001
|
||||
set_option -auto_constrain_io 0
|
||||
impl -active "../synth/rev_1"
|
||||
project -run hdl_info_gen -fileorder
|
||||
project -run
|
||||
project -save
|
||||
|
||||
1
ddr2_sdram/vhdl_bl4/example_design/synth/vhdl_bl4.lso
Executable file
1
ddr2_sdram/vhdl_bl4/example_design/synth/vhdl_bl4.lso
Executable file
@@ -0,0 +1 @@
|
||||
work
|
||||
34
ddr2_sdram/vhdl_bl4/example_design/synth/vhdl_bl4.prj
Executable file
34
ddr2_sdram/vhdl_bl4/example_design/synth/vhdl_bl4.prj
Executable file
@@ -0,0 +1,34 @@
|
||||
vhdl work ../rtl/vhdl_bl4.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_addr_gen_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_cal_ctl.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_cal_top.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_clk_dcm.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_cmd_fsm_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_cmp_data_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_controller_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_controller_iobs_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_gen_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_path_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_path_iobs_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_read_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_read_controller_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_data_write_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_dqs_delay_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_fifo_0_wr_en_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_fifo_1_wr_en_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_infrastructure.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_infrastructure_iobs_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_infrastructure_top.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_iobs_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_main_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_parameters_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_ram8d_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_ram8d_1.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_rd_gray_cntr.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_s3_dm_iob.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_s3_dq_iob.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_s3_dqs_iob.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_tap_dly.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_test_bench_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_top_0.vhd
|
||||
vhdl work ../rtl/vhdl_bl4_wr_gray_cntr.vhd
|
||||
788
ddr2_sdram/vhdl_bl4/example_design/vhdl_bl4cl2.cpj
Executable file
788
ddr2_sdram/vhdl_bl4/example_design/vhdl_bl4cl2.cpj
Executable file
@@ -0,0 +1,788 @@
|
||||
#ChipScope Pro Analyzer Project File, Version 3.0
|
||||
#Fri Jul 09 10:54:24 IST 2010
|
||||
device.0.configFileDir=\\\\Xhd-filer2\\ipmig\\on_boardtesting\\SP3A\\ddr2_sdram\\vhdl\\vhdl_bl4\\example_design\\par
|
||||
device.0.configFilename=vhdl_bl4.bit
|
||||
device.0.inserterCDCFileDir=\\\\Xhd-filer2\\ipmig\\on_boardtesting\\SP3A\\ddr2_sdram\\vhdl\\vhdl_bl4\\example_design\\par
|
||||
device.0.inserterCDCFilename=
|
||||
deviceChain.deviceName0=XC3S700A
|
||||
deviceChain.deviceName1=XCF04S
|
||||
deviceChain.iRLength0=6
|
||||
deviceChain.iRLength1=8
|
||||
deviceChain.name0=MyDevice0
|
||||
deviceChain.name1=MyDevice1
|
||||
deviceIds=02228093f5046093
|
||||
mdiAreaHeight=0.375
|
||||
mdiAreaHeightLast=0.7321428571428571
|
||||
mdiCount=2
|
||||
mdiDevice0=0
|
||||
mdiDevice1=0
|
||||
mdiType0=1
|
||||
mdiType1=0
|
||||
mdiUnit0=0
|
||||
mdiUnit1=0
|
||||
navigatorHeight=0.29464285714285715
|
||||
navigatorHeightLast=0.17633928571428573
|
||||
navigatorWidth=0.16468725257323832
|
||||
navigatorWidthLast=0.1250989707046714
|
||||
unit.-1.-1.username=
|
||||
unit.0.-1.username=
|
||||
unit.0.0.0.HEIGHT0=1.963964
|
||||
unit.0.0.0.TriggerRow0=1
|
||||
unit.0.0.0.TriggerRow1=1
|
||||
unit.0.0.0.TriggerRow2=1
|
||||
unit.0.0.0.WIDTH0=1.0
|
||||
unit.0.0.0.X0=0.0
|
||||
unit.0.0.0.Y0=0.0
|
||||
unit.0.0.1.HEIGHT1=1.963964
|
||||
unit.0.0.1.WIDTH1=1.0
|
||||
unit.0.0.1.X1=0.0
|
||||
unit.0.0.1.Y1=0.0
|
||||
unit.0.0.MFBitsA0=XXXXXRX
|
||||
unit.0.0.MFBitsB0=0000000
|
||||
unit.0.0.MFCompareA0=0
|
||||
unit.0.0.MFCompareB0=999
|
||||
unit.0.0.MFCount=1
|
||||
unit.0.0.MFDisplay0=0
|
||||
unit.0.0.MFEventType0=3
|
||||
unit.0.0.RunMode=SINGLE RUN
|
||||
unit.0.0.SQCondition=All Data
|
||||
unit.0.0.SQContiguous0=0
|
||||
unit.0.0.SequencerOn=0
|
||||
unit.0.0.TCActive=0
|
||||
unit.0.0.TCAdvanced0=0
|
||||
unit.0.0.TCCondition0_0=M0
|
||||
unit.0.0.TCCondition0_1=
|
||||
unit.0.0.TCConditionType0=0
|
||||
unit.0.0.TCCount=1
|
||||
unit.0.0.TCEventCount0=1
|
||||
unit.0.0.TCEventType0=3
|
||||
unit.0.0.TCName0=TriggerCondition0
|
||||
unit.0.0.TCOutputEnable0=0
|
||||
unit.0.0.TCOutputHigh0=1
|
||||
unit.0.0.TCOutputMode0=0
|
||||
unit.0.0.browser_tree_state<Data\ Port>=1
|
||||
unit.0.0.browser_tree_state<Trigger\ Ports>=1
|
||||
unit.0.0.browser_tree_state<TriggerPort0>=1
|
||||
unit.0.0.browser_tree_state<dbg_cnt>=1
|
||||
unit.0.0.browser_tree_state<dbg_phase_cnt>=1
|
||||
unit.0.0.coretype=ILA
|
||||
unit.0.0.eventCount0=1
|
||||
unit.0.0.port.-1.b.0.alias=cmp_data_fall
|
||||
unit.0.0.port.-1.b.0.channellist=39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
|
||||
unit.0.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.b.0.name=DataPort
|
||||
unit.0.0.port.-1.b.0.orderindex=-1
|
||||
unit.0.0.port.-1.b.0.radix=Hex
|
||||
unit.0.0.port.-1.b.0.signedOffset=0.0
|
||||
unit.0.0.port.-1.b.0.signedPrecision=0
|
||||
unit.0.0.port.-1.b.0.signedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.0.tokencount=0
|
||||
unit.0.0.port.-1.b.0.unsignedOffset=0.0
|
||||
unit.0.0.port.-1.b.0.unsignedPrecision=0
|
||||
unit.0.0.port.-1.b.0.unsignedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.0.visible=1
|
||||
unit.0.0.port.-1.b.1.alias=cmp_data_rise
|
||||
unit.0.0.port.-1.b.1.channellist=23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
|
||||
unit.0.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.b.1.name=DataPort
|
||||
unit.0.0.port.-1.b.1.orderindex=-1
|
||||
unit.0.0.port.-1.b.1.radix=Hex
|
||||
unit.0.0.port.-1.b.1.signedOffset=0.0
|
||||
unit.0.0.port.-1.b.1.signedPrecision=0
|
||||
unit.0.0.port.-1.b.1.signedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.1.tokencount=0
|
||||
unit.0.0.port.-1.b.1.unsignedOffset=0.0
|
||||
unit.0.0.port.-1.b.1.unsignedPrecision=0
|
||||
unit.0.0.port.-1.b.1.unsignedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.1.visible=1
|
||||
unit.0.0.port.-1.b.2.alias=dbg_cnt
|
||||
unit.0.0.port.-1.b.2.channellist=3 4 5 6 7 8
|
||||
unit.0.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.b.2.name=DataPort
|
||||
unit.0.0.port.-1.b.2.orderindex=-1
|
||||
unit.0.0.port.-1.b.2.radix=Hex
|
||||
unit.0.0.port.-1.b.2.signedOffset=0.0
|
||||
unit.0.0.port.-1.b.2.signedPrecision=0
|
||||
unit.0.0.port.-1.b.2.signedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.2.tokencount=0
|
||||
unit.0.0.port.-1.b.2.unsignedOffset=0.0
|
||||
unit.0.0.port.-1.b.2.unsignedPrecision=0
|
||||
unit.0.0.port.-1.b.2.unsignedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.2.visible=1
|
||||
unit.0.0.port.-1.b.3.alias=dbg_delay_sel
|
||||
unit.0.0.port.-1.b.3.channellist=15 16 17 18 19
|
||||
unit.0.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.b.3.name=DataPort
|
||||
unit.0.0.port.-1.b.3.orderindex=-1
|
||||
unit.0.0.port.-1.b.3.radix=Hex
|
||||
unit.0.0.port.-1.b.3.signedOffset=0.0
|
||||
unit.0.0.port.-1.b.3.signedPrecision=0
|
||||
unit.0.0.port.-1.b.3.signedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.3.tokencount=0
|
||||
unit.0.0.port.-1.b.3.unsignedOffset=0.0
|
||||
unit.0.0.port.-1.b.3.unsignedPrecision=0
|
||||
unit.0.0.port.-1.b.3.unsignedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.3.visible=1
|
||||
unit.0.0.port.-1.b.4.alias=dbg_phase_cnt
|
||||
unit.0.0.port.-1.b.4.channellist=9 10 11 12 13
|
||||
unit.0.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.b.4.name=DataPort
|
||||
unit.0.0.port.-1.b.4.orderindex=-1
|
||||
unit.0.0.port.-1.b.4.radix=Hex
|
||||
unit.0.0.port.-1.b.4.signedOffset=0.0
|
||||
unit.0.0.port.-1.b.4.signedPrecision=0
|
||||
unit.0.0.port.-1.b.4.signedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.4.tokencount=0
|
||||
unit.0.0.port.-1.b.4.unsignedOffset=0.0
|
||||
unit.0.0.port.-1.b.4.unsignedPrecision=0
|
||||
unit.0.0.port.-1.b.4.unsignedScaleFactor=1.0
|
||||
unit.0.0.port.-1.b.4.visible=1
|
||||
unit.0.0.port.-1.buscount=5
|
||||
unit.0.0.port.-1.channelcount=58
|
||||
unit.0.0.port.-1.s.0.alias=dbg_enb_trans_two_dtct
|
||||
unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.s.0.name=DataPort[0]
|
||||
unit.0.0.port.-1.s.0.orderindex=-1
|
||||
unit.0.0.port.-1.s.0.visible=1
|
||||
unit.0.0.port.-1.s.1.alias=dbg_trans_twodtct
|
||||
unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.s.1.name=DataPort[1]
|
||||
unit.0.0.port.-1.s.1.orderindex=-1
|
||||
unit.0.0.port.-1.s.1.visible=1
|
||||
unit.0.0.port.-1.s.10.alias=
|
||||
unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.0.port.-1.s.10.name=DataPort[10]
|
||||
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|
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|
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|
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|
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unit.0.0.waveform.posn.57.name=DataPort[57]
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unit.0.0.waveform.posn.57.type=signal
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unit.0.0.waveform.posn.7.channel=2147483646
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unit.0.0.waveform.posn.7.name=dbg_delay_sel
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unit.0.0.waveform.posn.7.type=bus
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unit.0.0.waveform.posn.8.channel=2147483646
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unit.0.0.waveform.posn.8.name=dbg_phase_cnt
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unit.0.0.waveform.posn.8.type=bus
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unit.0.0.waveform.posn.9.channel=2147483646
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unit.0.0.waveform.posn.9.type=bus
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unit.0.1.port.-1.channelcount=0
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unit.0.1.port.1.s.1.visible=1
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unit.0.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.10.display=0
|
||||
unit.0.1.port.1.s.10.name=AsyncOut[10]
|
||||
unit.0.1.port.1.s.10.orderindex=-1
|
||||
unit.0.1.port.1.s.10.persistence=0
|
||||
unit.0.1.port.1.s.10.value=0
|
||||
unit.0.1.port.1.s.10.visible=1
|
||||
unit.0.1.port.1.s.11.alias=
|
||||
unit.0.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.11.display=0
|
||||
unit.0.1.port.1.s.11.name=AsyncOut[11]
|
||||
unit.0.1.port.1.s.11.orderindex=-1
|
||||
unit.0.1.port.1.s.11.persistence=0
|
||||
unit.0.1.port.1.s.11.value=0
|
||||
unit.0.1.port.1.s.11.visible=1
|
||||
unit.0.1.port.1.s.2.alias=
|
||||
unit.0.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.2.display=0
|
||||
unit.0.1.port.1.s.2.name=AsyncOut[2]
|
||||
unit.0.1.port.1.s.2.orderindex=-1
|
||||
unit.0.1.port.1.s.2.persistence=0
|
||||
unit.0.1.port.1.s.2.value=0
|
||||
unit.0.1.port.1.s.2.visible=1
|
||||
unit.0.1.port.1.s.3.alias=
|
||||
unit.0.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.3.display=0
|
||||
unit.0.1.port.1.s.3.name=AsyncOut[3]
|
||||
unit.0.1.port.1.s.3.orderindex=-1
|
||||
unit.0.1.port.1.s.3.persistence=0
|
||||
unit.0.1.port.1.s.3.value=0
|
||||
unit.0.1.port.1.s.3.visible=1
|
||||
unit.0.1.port.1.s.4.alias=
|
||||
unit.0.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.4.display=0
|
||||
unit.0.1.port.1.s.4.name=AsyncOut[4]
|
||||
unit.0.1.port.1.s.4.orderindex=-1
|
||||
unit.0.1.port.1.s.4.persistence=0
|
||||
unit.0.1.port.1.s.4.value=0
|
||||
unit.0.1.port.1.s.4.visible=1
|
||||
unit.0.1.port.1.s.5.alias=
|
||||
unit.0.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.5.display=0
|
||||
unit.0.1.port.1.s.5.name=AsyncOut[5]
|
||||
unit.0.1.port.1.s.5.orderindex=-1
|
||||
unit.0.1.port.1.s.5.persistence=0
|
||||
unit.0.1.port.1.s.5.value=0
|
||||
unit.0.1.port.1.s.5.visible=1
|
||||
unit.0.1.port.1.s.6.alias=
|
||||
unit.0.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.6.display=0
|
||||
unit.0.1.port.1.s.6.name=AsyncOut[6]
|
||||
unit.0.1.port.1.s.6.orderindex=-1
|
||||
unit.0.1.port.1.s.6.persistence=0
|
||||
unit.0.1.port.1.s.6.value=0
|
||||
unit.0.1.port.1.s.6.visible=1
|
||||
unit.0.1.port.1.s.7.alias=
|
||||
unit.0.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.7.display=0
|
||||
unit.0.1.port.1.s.7.name=AsyncOut[7]
|
||||
unit.0.1.port.1.s.7.orderindex=-1
|
||||
unit.0.1.port.1.s.7.persistence=0
|
||||
unit.0.1.port.1.s.7.value=0
|
||||
unit.0.1.port.1.s.7.visible=1
|
||||
unit.0.1.port.1.s.8.alias=
|
||||
unit.0.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.8.display=0
|
||||
unit.0.1.port.1.s.8.name=AsyncOut[8]
|
||||
unit.0.1.port.1.s.8.orderindex=-1
|
||||
unit.0.1.port.1.s.8.persistence=0
|
||||
unit.0.1.port.1.s.8.value=0
|
||||
unit.0.1.port.1.s.8.visible=1
|
||||
unit.0.1.port.1.s.9.alias=
|
||||
unit.0.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
|
||||
unit.0.1.port.1.s.9.display=0
|
||||
unit.0.1.port.1.s.9.name=AsyncOut[9]
|
||||
unit.0.1.port.1.s.9.orderindex=-1
|
||||
unit.0.1.port.1.s.9.persistence=0
|
||||
unit.0.1.port.1.s.9.value=0
|
||||
unit.0.1.port.1.s.9.visible=1
|
||||
unit.0.1.port.2.buscount=0
|
||||
unit.0.1.port.2.channelcount=0
|
||||
unit.0.1.portcount=3
|
||||
unit.0.1.username=MyVIO1
|
||||
Reference in New Issue
Block a user