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2d_display_engine/doc/wb_ddr_ctrl_wb.txt

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From wb to ddr (62 bits)
data (31..0)
adr (25..2)
we
_burst/single
be (3..0)
for read cycles, data is don't care
From ddr to wb (32 bits)
data (31..0)
for write cycles, data is don't care