99 lines
3.1 KiB
VHDL
Executable File
99 lines
3.1 KiB
VHDL
Executable File
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-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 9.2.04i
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-- \ \ Application : xaw2vhdl
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-- / / Filename : dcm_in50.vhd
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-- /___/ /\ Timestamp : 01/03/2009 16:40:00
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-- \ \ / \
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-- \___\/\___\
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--
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--Command: xaw2vhdl-st C:\vhdl\nascom2_t80\coregen\\dcm_in50.xaw C:\vhdl\nascom2_t80\coregen\\dcm_in50
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--Design Name: dcm_in50
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--Device: xc3s700an-4fgg484
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--
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-- Module dcm_in50
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-- Generated by Xilinx Architecture Wizard
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-- Written for synthesis tool: XST
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-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
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-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.88 ns
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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entity dcm_in50 is
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port ( CLKIN_IN : in std_logic;
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RST_IN : in std_logic;
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CLKFX_OUT : out std_logic;
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CLKIN_IBUFG_OUT : out std_logic;
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CLK0_OUT : out std_logic;
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LOCKED_OUT : out std_logic);
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end dcm_in50;
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architecture BEHAVIORAL of dcm_in50 is
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signal CLKFB_IN : std_logic;
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signal CLKFX_BUF : std_logic;
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signal CLKIN_IBUFG : std_logic;
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signal CLK0_BUF : std_logic;
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signal GND_BIT : std_logic;
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begin
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GND_BIT <= '0';
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CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
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CLK0_OUT <= CLKFB_IN;
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CLKFX_BUFG_INST : BUFG
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port map (I=>CLKFX_BUF,
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O=>CLKFX_OUT);
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CLKIN_IBUFG_INST : IBUFG
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port map (I=>CLKIN_IN,
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O=>CLKIN_IBUFG);
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CLK0_BUFG_INST : BUFG
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port map (I=>CLK0_BUF,
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O=>CLKFB_IN);
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DCM_SP_INST : DCM_SP
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generic map( CLK_FEEDBACK => "1X",
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 25,
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CLKFX_MULTIPLY => 16,
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CLKIN_DIVIDE_BY_2 => TRUE,
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CLKIN_PERIOD => 40.000,
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CLKOUT_PHASE_SHIFT => "NONE",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => x"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => TRUE)
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port map (CLKFB=>CLKFB_IN,
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CLKIN=>CLKIN_IBUFG,
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DSSEN=>GND_BIT,
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PSCLK=>GND_BIT,
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PSEN=>GND_BIT,
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PSINCDEC=>GND_BIT,
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RST=>RST_IN,
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CLKDV=>open,
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CLKFX=>CLKFX_BUF,
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CLKFX180=>open,
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CLK0=>CLK0_BUF,
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CLK2X=>open,
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CLK2X180=>open,
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CLK90=>open,
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CLK180=>open,
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CLK270=>open,
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LOCKED=>LOCKED_OUT,
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PSDONE=>open,
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STATUS=>open);
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end BEHAVIORAL;
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