Initial commit
This commit is contained in:
matthias
BIN
KCPSM3.EXE
Executable file
BIN
KCPSM3.EXE
Executable file
Binary file not shown.
45
Makefile
Executable file
45
Makefile
Executable file
@@ -0,0 +1,45 @@
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XILINX=C:/Xilinx92i
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XILPATH=$(XILINX)/bin/nt
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INFILES=toplevel.vhd memory.vhd coregen/charrom.vhd coregen/monitorrom.vhd coregen/basic_rom.vhd coregen/ram2kx8.vhd coregen/dcm_in50.vhd T80_Pack.vhd T80_ALU.vhd T80_MCode.vhd T80_RegX.vhd T80.vhd T80a.vhd T80se.vhd video.vhd videogen.vhd syncgen.vhd keyboard.vhd uart.vhd kcpsm3.vhd uartprog.vhd fifo16x8.vhd spi.vhd
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NGCFILE=nascom2.ngc
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XSTFILE=nascom2.xst
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UCF=nascom2.ucf
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PCFFILE=nascom2.pcf
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NGDFILE=nascom2.ngd
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NCDFILE=nascom2.ncd
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NCDFILE_R=nascom2_routed.ncd
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BITFILE=nascom2.bit
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TWRFILE=nascom2.twr
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PART=xc3s700an-fgg484-4
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NGDOPTS=-p $(PART) -aul -uc $(UCF) -sd coregen/
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MAPOPTS=-p $(PART) -cm area
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PAROPTS=-rl high -pl high
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BITGENOPTS=
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TRACEOPTS=-v -u 100
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all: $(BITFILE)
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%.vhd: %.psm
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KCPSM3.exe $<
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$(NGCFILE): $(INFILES)
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$(XILPATH)/xst -ifn $(XSTFILE)
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$(NGDFILE): $(NGCFILE) $(UCF)
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$(XILPATH)/ngdbuild $(NGDOPTS) $(NGCFILE) $(NGDFILE)
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$(PCFFILE) $(NCDFILE) : $(NGDFILE)
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$(XILPATH)/map $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
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$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
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$(XILPATH)/par -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
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$(BITFILE): $(NCDFILE_R) $(PCFFILE)
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$(XILPATH)/bitgen -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
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$(TWRFILE): $(NCDFILE_R) $(PCFFILE)
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$(XILPATH)/trce $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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clean:
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rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE)
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258
NASSYSI.coe
Executable file
258
NASSYSI.coe
Executable file
@@ -0,0 +1,258 @@
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memory_initialization_radix=16;
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memory_initialization_vector=
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31, 00, 10, D7, 08, C3, B2, 03,
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||||
DF, 62, D8, 18, FB, C3, 9A, 03,
|
||||
E5, F5, 37, 21, 08, 00, 18, 05,
|
||||
E5, F5, A7, 18, F6, C3, 70, 05,
|
||||
E3, 2B, E3, C3, 1A, 04, 00, 00,
|
||||
E3, 7E, 23, B7, 20, 06, E3, C9,
|
||||
E5, C3, 5A, 07, F7, 18, F2, 00,
|
||||
3D, C8, F5, F1, 18, FA, AF, 47,
|
||||
FF, FF, 10, FC, C9, E5, 21, 00,
|
||||
0C, AE, D3, 00, 7E, D3, 00, E1,
|
||||
C9, 3E, 10, E5, 21, 00, 0C, AE,
|
||||
77, 18, F2, F5, D3, 01, DB, 02,
|
||||
CB, 77, 28, FA, F1, C9, C3, 7D,
|
||||
0C, 1E, C0, DF, 62, D8, 1D, 20,
|
||||
FA, C9, 2A, 29, 0C, 56, 36, 5F,
|
||||
D7, EF, 72, D8, D7, EB, 30, F2,
|
||||
C9, DB, 02, 17, D0, DB, 01, C9,
|
||||
3E, 02, CD, 45, 00, 21, 01, 0C,
|
||||
DB, 00, 2F, 77, 06, 08, 3E, 01,
|
||||
CD, 45, 00, 23, DB, 00, 2F, 57,
|
||||
AE, 20, 04, 10, F1, B7, C9, AF,
|
||||
FF, DB, 00, 2F, 5F, 7A, AE, 0E,
|
||||
FF, 16, 00, 37, CB, 12, 0C, 1F,
|
||||
30, FA, 7A, A3, 5F, 7E, A2, BB,
|
||||
28, E1, 7E, AA, 77, 7B, B7, 28,
|
||||
DA, 3A, 01, 0C, E6, 10, B0, 87,
|
||||
87, 87, B1, D7, 5B, 28, 06, E6,
|
||||
7F, D7, 55, 20, C8, 37, ED, 52,
|
||||
7D, FE, 41, 38, 1E, FE, 5B, 30,
|
||||
1A, 21, 01, 0C, CB, 66, 21, 27,
|
||||
0C, 20, 08, CB, 46, 28, 0C, C6,
|
||||
20, 18, 08, C6, 20, CB, 46, 28,
|
||||
02, D6, 20, 21, 01, 0C, FE, 40,
|
||||
20, 06, CB, 66, 28, 97, 18, 06,
|
||||
CB, 6E, 28, 02, EE, 40, CB, 5E,
|
||||
28, 02, EE, 40, 21, 06, 0C, CB,
|
||||
76, 28, 02, EE, 80, 21, 27, 0C,
|
||||
CB, 56, 28, 02, EE, 80, 37, C9,
|
||||
2A, 6F, 0C, 54, 5D, ED, 4B, 6D,
|
||||
0C, ED, B1, C9, 00, 10, 60, 00,
|
||||
9E, 05, 06, 07, 7F, 07, 82, 07,
|
||||
C3, 2F, 00, C3, 2F, 00, C3, B7,
|
||||
C8, F5, FE, 0A, 28, 24, FE, 0C,
|
||||
20, 22, 21, 0A, 08, E5, 06, 30,
|
||||
36, 20, 23, 10, FB, 06, 10, 36,
|
||||
00, 23, 10, FB, EB, E1, E5, 01,
|
||||
B0, 03, ED, B0, E1, DF, 7C, 22,
|
||||
29, 0C, F1, C9, 2A, 29, 0C, FE,
|
||||
08, 20, 11, F5, 2B, 7E, B7, 28,
|
||||
FB, F1, FE, 11, 28, 02, 36, 20,
|
||||
D7, 63, 18, E6, FE, 11, 28, EB,
|
||||
FE, 17, 28, D9, FE, 1B, 20, 0B,
|
||||
DF, 7C, 06, 30, 36, 20, 23, 10,
|
||||
FB, 18, CA, FE, 0D, 28, 66, FE,
|
||||
18, 20, 0C, E5, DF, 7C, D1, B7,
|
||||
ED, 52, 19, 28, BA, 18, 56, FE,
|
||||
13, 20, 08, 11, C0, FF, 19, D7,
|
||||
2C, 18, AF, FE, 14, 20, 05, 11,
|
||||
40, 00, 18, F2, FE, 15, 20, 0E,
|
||||
23, 7E, 2B, B7, 20, 04, 36, 20,
|
||||
18, 98, 77, 23, 18, F2, FE, 16,
|
||||
20, 1F, 06, 20, 7E, B7, 28, 8A,
|
||||
70, 47, 23, 18, F7, 11, 0A, 08,
|
||||
B7, ED, 52, 19, D8, 11, BA, 0B,
|
||||
B7, ED, 52, 19, D0, F1, C3, 77,
|
||||
01, FE, 12, 28, 01, 77, 23, 7E,
|
||||
B7, 28, FB, D7, E0, DF, 7C, 11,
|
||||
40, 00, 19, D7, D8, 11, 0A, 08,
|
||||
21, 4A, 08, 01, 70, 03, ED, B0,
|
||||
06, 30, 2B, 36, 20, 10, FB, 21,
|
||||
8A, 0B, 18, D2, 7D, D6, 40, 30,
|
||||
FC, C6, 36, 5F, 7D, 93, 6F, C9,
|
||||
DF, 60, 22, 0C, 0C, DF, 66, 7E,
|
||||
DF, 68, EF, 20, 11, 11, 11, 00,
|
||||
D7, 54, DF, 64, 38, 4C, 7E, B7,
|
||||
28, 48, 23, D5, 5E, 23, 56, EB,
|
||||
D1, 06, 00, E5, DF, 64, 7E, B7,
|
||||
28, 07, 23, 7E, E1, 77, 04, 23,
|
||||
E5, E1, 1A, FE, 2E, C8, FE, 2C,
|
||||
20, 05, 13, 1A, 13, 18, EE, 78,
|
||||
B7, 20, 01, 23, 1A, FE, 3A, 20,
|
||||
04, 2B, 2B, 18, B5, FE, 2F, 20,
|
||||
0A, 13, DF, 64, 38, 0C, 2A, 21,
|
||||
0C, 18, A7, B7, 28, A4, FE, 20,
|
||||
28, C1, DF, 6B, 18, 9A, E5, CD,
|
||||
8A, 03, AF, 32, 26, 0C, 21, 1A,
|
||||
04, 22, 7E, 0C, E1, E5, DF, 7B,
|
||||
F7, FE, 0D, 20, F9, 2A, 29, 0C,
|
||||
11, C0, FF, 19, EB, E1, C9, C5,
|
||||
18, 17, B7, ED, 52, 19, 38, 06,
|
||||
C1, EF, 2E, 0D, 00, C9, 78, B1,
|
||||
20, 07, CF, FE, 1B, 28, F1, C1,
|
||||
C5, 0B, C5, 0E, 00, EF, 20, 20,
|
||||
00, DF, 66, 06, 08, 7E, DF, 67,
|
||||
23, DF, 69, 10, F8, 79, DF, 68,
|
||||
EF, 08, 08, 0D, 00, C1, 18, CA,
|
||||
7C, DF, 67, 7D, DF, 67, 3E, 20,
|
||||
F7, C9, EF, 45, 72, 72, 6F, 72,
|
||||
00, 3E, 0D, F7, C9, F5, 81, 4F,
|
||||
F1, F5, 1F, 1F, 1F, 1F, D7, 01,
|
||||
F1, E6, 0F, C6, 30, FE, 3A, 38,
|
||||
02, C6, 07, F7, C9, D7, 00, DF,
|
||||
66, EB, C9, 1A, FE, 20, 13, 28,
|
||||
FA, 1B, 21, 00, 00, 22, 21, 0C,
|
||||
AF, 21, 20, 0C, 77, 1A, B7, C8,
|
||||
FE, 20, C8, D6, 30, D8, FE, 0A,
|
||||
38, 0B, D6, 07, FE, 0A, D8, FE,
|
||||
10, 38, 02, 37, C9, 13, 34, 23,
|
||||
ED, 6F, 23, ED, 6F, 2B, 2B, 28,
|
||||
DC, 1B, 37, C9, 01, 0B, 0C, AF,
|
||||
02, DF, 64, D8, 7E, B7, C8, 23,
|
||||
03, 7E, 02, 23, 03, 7E, 02, 21,
|
||||
0B, 0C, 34, 7E, FE, 0B, 38, E9,
|
||||
37, C9, 2A, 23, 0C, 7E, 32, 25,
|
||||
0C, C9, 2A, 23, 0C, 3A, 25, 0C,
|
||||
77, C9, D7, F6, 11, 00, 0C, 06,
|
||||
6B, AF, 12, 13, 10, FC, 21, 3C,
|
||||
01, 01, 15, 00, ED, B0, EF, 0C,
|
||||
00, C9, 31, 61, 0C, 2A, 3C, 01,
|
||||
22, 6B, 0C, EF, 4E, 41, 53, 2D,
|
||||
53, 59, 53, 20, 69, 0D, 00, D7,
|
||||
C9, CD, A6, 02, 01, 2B, 0C, 1A,
|
||||
FE, 20, 20, 05, 0A, FE, 53, 20,
|
||||
F0, FE, 41, 38, 0D, FE, 5B, 30,
|
||||
09, 02, 32, 0A, 0C, 13, DF, 79,
|
||||
30, 04, DF, 6B, 18, DB, DF, 60,
|
||||
DF, 5C, 18, D5, 3E, FF, 32, 26,
|
||||
0C, F1, 3A, 0B, 0C, B7, 28, 03,
|
||||
22, 69, 0C, C1, D1, F1, F1, 2A,
|
||||
6B, 0C, F9, 2A, 69, 0C, E5, 2A,
|
||||
65, 0C, F5, 3E, 08, D3, 00, F1,
|
||||
ED, 45, F5, E5, 3A, 00, 0C, D3,
|
||||
00, 3A, 26, 0C, B7, 28, 0D, CD,
|
||||
8A, 03, 36, E7, AF, 32, 26, 0C,
|
||||
E1, F1, ED, 45, D5, C5, 21, 00,
|
||||
00, 39, 31, 61, 0C, 11, 61, 0C,
|
||||
01, 08, 00, ED, B0, 5E, 23, 56,
|
||||
23, ED, 53, 69, 0C, 22, 6B, 0C,
|
||||
EF, 18, 00, 21, 6D, 0C, 06, 06,
|
||||
2B, 7E, DF, 68, 2B, 7E, DF, 68,
|
||||
DF, 69, 10, F4, ED, 57, DF, 68,
|
||||
DF, 69, DD, E5, E1, DF, 66, FD,
|
||||
E5, E1, DF, 66, 3A, 67, 0C, 11,
|
||||
8B, 04, 06, 08, 13, 17, F5, 1A,
|
||||
30, 01, F7, F1, 10, F6, EF, 18,
|
||||
00, C3, C7, 03, 53, 5A, 00, 48,
|
||||
00, 50, 4E, 43, DF, 5F, DF, 77,
|
||||
E5, DF, 78, E5, CF, E6, 7F, FE,
|
||||
2E, 28, 3A, FE, 0D, 28, 07, FE,
|
||||
20, 38, F1, F7, 18, EE, 2A, 29,
|
||||
0C, DF, 7C, EB, DF, 79, 38, 21,
|
||||
21, 0C, 0C, AF, 06, 12, 86, 23,
|
||||
10, FC, BE, 20, 14, 2A, 0C, 0C,
|
||||
11, 0E, 0C, 06, 08, 1A, 77, 23,
|
||||
13, 13, 10, F9, EF, 1B, 00, 18,
|
||||
C3, DF, 6A, 18, BF, CF, E6, 7F,
|
||||
FE, 0D, 20, B9, F7, C3, 86, 06,
|
||||
DF, 5F, DF, 5D, DF, 77, E5, AF,
|
||||
47, DF, 6F, 10, FC, DF, 60, ED,
|
||||
5B, 0E, 0C, EB, 37, ED, 52, DA,
|
||||
8A, 06, EB, AF, FF, 06, 05, DF,
|
||||
6F, 3E, FF, 10, FA, AF, BA, 20,
|
||||
02, 43, 04, 58, 7D, DF, 6F, 7C,
|
||||
DF, 6F, 7B, DF, 6F, 7A, DF, 6F,
|
||||
0E, 00, DF, 6C, 79, DF, 6F, DF,
|
||||
6D, 06, 0B, 79, DF, 6F, AF, 10,
|
||||
FB, DF, 6A, 18, C2, B7, ED, 52,
|
||||
19, 30, 09, 0B, EB, 09, EB, 09,
|
||||
03, ED, B8, C9, ED, B0, C9, EB,
|
||||
E5, 19, DF, 66, E1, B7, ED, 52,
|
||||
DF, 66, 2B, 2B, 7C, FE, FF, 20,
|
||||
0A, CB, 7D, 20, 0D, EF, 3F, 3F,
|
||||
0D, 00, C9, B7, 20, F7, CB, 7D,
|
||||
20, F3, 7D, DF, 68, C3, 11, 03,
|
||||
D5, F5, 39, 5E, 23, 56, 13, 72,
|
||||
2B, 73, 1B, EB, F1, 30, 11, 5E,
|
||||
7B, 17, 9F, 57, 23, 19, D1, F1,
|
||||
E3, C9, E5, F5, D5, 21, 0A, 0C,
|
||||
5E, 16, 00, 2A, 71, 0C, 19, 19,
|
||||
5E, 23, 56, EB, 18, E8, FF, FF,
|
||||
FF, FF, FF, FF, FF, FF, 08, FF,
|
||||
8E, FF, 88, 09, FF, FF, FF, 3E,
|
||||
2E, 46, 36, BE, AE, 0E, FF, FF,
|
||||
FF, 89, FF, FF, FF, FF, 14, 9C,
|
||||
9B, A3, 92, C2, BA, B2, AA, A2,
|
||||
98, A0, 29, 0A, 21, 19, 1A, 1C,
|
||||
1B, 23, 12, 42, 3A, 32, 2A, 22,
|
||||
18, 20, A9, 8A, A1, 99, 0D, 2C,
|
||||
41, 13, 3B, 33, 43, 10, 40, 2D,
|
||||
38, 30, 28, 31, 39, 25, 1D, 24,
|
||||
15, 34, 45, 35, 11, 2B, 44, 3D,
|
||||
3C, 1E, 9E, 16, 9A, 96, 7D, 32,
|
||||
27, 0C, C9, 22, 23, 0C, C9, 44,
|
||||
4D, ED, 59, C9, 44, 4D, ED, 78,
|
||||
DF, 68, C3, 11, 03, ED, 4B, 10,
|
||||
0C, ED, 5B, 0E, 0C, 2A, 0C, 0C,
|
||||
C9, 21, 7A, 07, DF, 71, E5, 21,
|
||||
4C, 06, 06, 06, 7E, F7, 0E, 14,
|
||||
AF, FF, 0D, 20, FC, 23, 10, F4,
|
||||
DF, 57, AF, FF, 3E, 45, F7, 2A,
|
||||
10, 0C, DF, 66, 3E, 0D, F7, E1,
|
||||
22, 73, 0C, C9, 0D, 45, 30, 0D,
|
||||
52, 0D, 0E, 00, 7E, 81, 4F, 7E,
|
||||
DF, 6F, 23, 10, F7, C9, DF, 5F,
|
||||
DF, 77, E5, DF, 78, E5, CF, FE,
|
||||
FF, 20, 0B, 06, 03, CF, FE, FF,
|
||||
20, 04, 10, F9, 18, 1B, FE, 1B,
|
||||
20, EC, 06, 03, CF, FE, 1B, 20,
|
||||
E6, 10, F9, EF, 18, 00, E1, 22,
|
||||
75, 0C, E1, 22, 73, 0C, C3, 51,
|
||||
00, CF, 6F, CF, 67, CF, 5F, CF,
|
||||
57, 0E, 00, DF, 6C, CF, B9, 20,
|
||||
1E, 43, 0E, 00, 3A, 2B, 0C, FE,
|
||||
52, 28, 03, CF, 18, 02, CF, 77,
|
||||
E5, 2A, 29, 0C, 77, E1, 81, 4F,
|
||||
23, 10, E9, CF, B9, 28, 06, EF,
|
||||
3F, 20, 00, 18, A1, EF, 2E, 20,
|
||||
00, AF, BA, 20, 99, 18, B4, 21,
|
||||
81, 07, DF, 72, 21, 7E, 07, DF,
|
||||
71, C9, 7D, 32, 28, 0C, 21, 85,
|
||||
07, DF, 72, 21, 7D, 07, DF, 71,
|
||||
C9, DF, 70, D0, E6, 7F, F5, 21,
|
||||
28, 0C, CB, 6E, CC, 21, 07, D7,
|
||||
20, F1, FE, 7F, 20, 01, AF, FE,
|
||||
1B, 28, 05, B7, 28, 02, CB, FE,
|
||||
37, C9, F5, 21, 28, 0C, CB, 7E,
|
||||
CC, 17, 07, CB, BE, F1, C9, D7,
|
||||
08, FE, 0D, C0, CB, 66, C0, 3E,
|
||||
0A, B7, C8, F5, EA, 29, 07, EE,
|
||||
80, CB, 46, 28, 02, EE, 80, DF,
|
||||
6F, F1, C9, DF, 7B, F7, 18, FB,
|
||||
DF, 78, 21, 7F, 07, E5, 2A, 73,
|
||||
0C, E3, 22, 73, 0C, E1, C9, 21,
|
||||
82, 07, E5, 2A, 75, 0C, E3, 22,
|
||||
75, 0C, E1, C9, E5, 21, 75, 0C,
|
||||
18, 03, 21, 73, 0C, D5, C5, 5E,
|
||||
23, 56, F5, 1A, 13, B7, 28, 0D,
|
||||
32, 0A, 0C, F1, D5, B7, CD, 8A,
|
||||
05, D1, 30, EE, F5, F1, C1, D1,
|
||||
E1, C9, 65, 6F, 00, 6E, 75, 65,
|
||||
00, 76, 61, 70, 00, 74, 61, 00,
|
||||
47, 05, 03, 06, 44, 05, 0A, 03,
|
||||
F4, 03, 0A, 03, 21, 06, 33, 07,
|
||||
35, 05, FA, FF, FE, 05, 94, 04,
|
||||
40, 02, 38, 07, 07, 06, 0A, 03,
|
||||
0C, 06, 5E, 06, F9, 03, C7, 02,
|
||||
CF, 06, 5E, 06, E8, 04, DA, 06,
|
||||
0A, 03, FD, FF, B2, 03, 8A, 05,
|
||||
3E, 00, 45, 00, 51, 00, 15, 06,
|
||||
88, 00, 54, 07, B5, 02, 33, 03,
|
||||
4F, 01, 00, 03, 15, 03, 19, 03,
|
||||
06, 03, 11, 03, 0A, 03, 2D, 03,
|
||||
52, 06, 0A, 07, 5B, 00, 81, 00,
|
||||
3D, 07, 4A, 07, 5D, 07, E9, 06,
|
||||
77, 0C, 7A, 0C, 3A, 07, 47, 07,
|
||||
6C, 03, 21, 03, 72, 00, 34, 02;
|
||||
130
Nasbugt2.coe
Executable file
130
Nasbugt2.coe
Executable file
@@ -0,0 +1,130 @@
|
||||
memory_initialization_radix = 16;
|
||||
memory_initialization_vector =
|
||||
31, 33, 0C, 21, 00, 0C, 06, 15,
|
||||
36, 00, 23, 10, FB, 21, 28, 01,
|
||||
11, 3D, 0C, 01, 13, 00, ED, B0,
|
||||
3E, 1E, CD, 3B, 01, C3, 59, 03,
|
||||
F5, E5, D5, C3, 26, 03, 00, 00,
|
||||
E3, 7E, 23, B7, 28, 05, CD, 4A,
|
||||
0C, 18, F6, E3, C9, AF, F5, F1,
|
||||
F5, F1, 3D, 20, F9, C9, CD, 4D,
|
||||
0C, D8, DB, 02, 17, 30, F7, DB,
|
||||
01, C9, F5, CD, 53, 00, F1, 18,
|
||||
02, 3E, 10, E5, 21, 00, 0C, AE,
|
||||
D3, 00, 77, E1, C9, D3, 01, DB,
|
||||
02, 87, F8, 18, FA, 00, C3, 47,
|
||||
0C, C5, D5, E5, 3E, 02, CD, 4A,
|
||||
00, 21, 01, 0C, DB, 00, 2F, 77,
|
||||
06, 08, 3E, 01, CD, 4A, 00, 23,
|
||||
DB, 00, 2F, 57, AE, 20, 07, 10,
|
||||
F1, B7, E1, D1, C1, C9, CD, 35,
|
||||
00, DB, 00, 2F, 5F, 7A, AE, 0E,
|
||||
FF, 16, 00, 37, CB, 12, 0C, 1F,
|
||||
30, FA, 7A, A3, 5F, 7E, A2, BB,
|
||||
28, DD, 7E, AA, 77, 7B, B7, 28,
|
||||
D6, 3A, 01, 0C, E6, 10, B0, 87,
|
||||
87, 87, B1, ED, 4B, 3F, 0C, 2A,
|
||||
43, 0C, ED, B1, 28, 0B, 2A, 43,
|
||||
0C, ED, 4B, 3F, 0C, E6, 7F, ED,
|
||||
B1, 20, B6, ED, 4B, 43, 0C, 37,
|
||||
ED, 42, ED, 4B, 41, 0C, 09, 7D,
|
||||
37, 18, A7, 2A, 0C, 0C, 22, 15,
|
||||
0C, C9, 08, 88, 09, 14, 9C, 9B,
|
||||
A3, 92, C2, BA, B2, AA, A2, 98,
|
||||
A0, 29, 0A, 21, 19, 1A, 1C, 1B,
|
||||
23, 12, 42, 3A, 32, 2A, 22, 18,
|
||||
20, B1, 8A, B9, 99, 0D, 2C, 41,
|
||||
13, 3B, 33, 43, 10, 40, 2D, 38,
|
||||
30, 28, 31, 39, 25, 1D, 24, 15,
|
||||
34, 45, 35, 11, 2B, 44, 3D, 3C,
|
||||
00, 10, 3E, 00, 1D, 00, EA, 00,
|
||||
63, 03, C3, 05, 03, C3, 3B, 01,
|
||||
C3, 69, 00, B7, C8, F5, C5, D5,
|
||||
E5, FE, 1E, 20, 2F, 21, 09, 08,
|
||||
36, FF, 23, 06, 30, 36, 20, 23,
|
||||
10, FB, 06, 10, 36, 00, 23, 10,
|
||||
FB, EB, 21, 0A, 08, 01, B0, 03,
|
||||
ED, B0, 3E, FF, 32, BA, 0B, 21,
|
||||
8A, 0B, 36, 5F, 22, 18, 0C, E1,
|
||||
D1, C1, F1, C9, 2A, 18, 0C, 36,
|
||||
20, FE, 1D, 20, 0B, 2B, 7E, B7,
|
||||
28, FB, 3C, 20, E5, 23, 18, E2,
|
||||
FE, 1F, 28, 09, 77, 23, 7E, B7,
|
||||
28, FB, 3C, 20, D5, 11, 0A, 08,
|
||||
21, 4A, 08, 01, 70, 03, ED, B0,
|
||||
21, 10, 00, 19, 06, 30, 36, 20,
|
||||
23, 10, FB, 18, BA, 2A, 0C, 0C,
|
||||
CD, 32, 02, 7E, CD, 44, 02, CD,
|
||||
DB, 01, 11, 52, 0B, 06, 00, E5,
|
||||
CD, 5A, 02, 7E, B7, 28, 08, 23,
|
||||
7E, E1, 77, 04, 23, 18, F0, E1,
|
||||
1A, FE, 2E, C8, 78, B7, 20, 01,
|
||||
23, 18, D5, EF, 3E, 00, CD, 3E,
|
||||
00, FE, 1D, 28, 09, FE, 1F, 28,
|
||||
57, CD, 4A, 0C, 18, F0, ED, 5B,
|
||||
18, 0C, 1B, 1A, FE, 3E, 28, E6,
|
||||
3E, 1D, 18, ED, 2A, 0C, 0C, ED,
|
||||
5B, 0E, 0C, E5, B7, ED, 52, E1,
|
||||
38, 05, EF, 2E, 1F, 00, C9, 0E,
|
||||
00, CD, 32, 02, 06, 08, 7E, CD,
|
||||
2B, 02, 23, CD, 3C, 02, 10, F6,
|
||||
79, CD, 44, 02, EF, 1D, 1D, 1F,
|
||||
00, 18, D4, 57, 81, 4F, 7A, C3,
|
||||
44, 02, 7C, CD, 2B, 02, 7D, CD,
|
||||
2B, 02, 18, 00, 3E, 20, 18, 17,
|
||||
3E, 1F, 18, 13, F5, 1F, 1F, 1F,
|
||||
1F, CD, 4D, 02, F1, E6, 0F, C6,
|
||||
30, FE, 3A, 38, 02, C6, 07, C3,
|
||||
4A, 0C, 1A, FE, 20, 13, 28, FA,
|
||||
1B, AF, 21, 12, 0C, 77, 23, 77,
|
||||
23, 77, 1A, 2B, 2B, D6, 30, F8,
|
||||
FE, 0A, 38, 08, D6, 07, FE, 0A,
|
||||
F8, FE, 10, F0, 13, 34, 23, ED,
|
||||
6F, 23, ED, 6F, 18, E4, CD, DB,
|
||||
01, 11, 4B, 0B, 01, 0A, 0C, 1A,
|
||||
FE, 20, 20, 05, 0A, FE, 53, 20,
|
||||
ED, 02, 03, 13, AF, 02, 03, CD,
|
||||
5A, 02, 7E, B7, 28, 0D, 23, 7E,
|
||||
02, 23, 03, 7E, 02, 21, 0B, 0C,
|
||||
34, 18, EB, ED, 4B, 0A, 0C, 2A,
|
||||
45, 0C, 7E, B7, 28, C8, 23, B9,
|
||||
28, 05, 00, 23, 23, 18, F3, 5E,
|
||||
23, 56, 21, 86, 02, E5, EB, E9,
|
||||
3E, FF, 32, 1A, 0C, 21, 05, 03,
|
||||
22, 48, 0C, E1, 3A, 0B, 0C, B7,
|
||||
28, 06, 2A, 0C, 0C, 22, 3B, 0C,
|
||||
C1, D1, F1, F1, 2A, 3D, 0C, F9,
|
||||
2A, 3B, 0C, E5, 2A, 37, 0C, F5,
|
||||
3E, 08, D3, 00, F1, ED, 45, AF,
|
||||
32, 1A, 0C, 18, D0, E3, 23, E3,
|
||||
F5, E5, 3A, 00, 0C, D3, 00, 3A,
|
||||
1A, 0C, B7, 28, 10, 2A, 15, 0C,
|
||||
7E, 32, 17, 0C, 36, E7, E1, F1,
|
||||
E3, 2B, E3, ED, 45, D5, C5, 21,
|
||||
00, 00, 39, 11, 33, 0C, 31, 33,
|
||||
0C, 01, 08, 00, ED, B0, 5E, 23,
|
||||
56, 23, 1B, ED, 53, 3B, 0C, 22,
|
||||
3D, 0C, 21, 3F, 0C, 06, 06, 2B,
|
||||
7E, CD, 44, 02, 2B, 7E, CD, 44,
|
||||
02, CD, 3C, 02, 10, F1, CD, 40,
|
||||
02, 2A, 15, 0C, 3A, 17, 0C, 77,
|
||||
C3, 86, 02, 4D, AD, 01, 43, EF,
|
||||
03, 45, D0, 02, 53, FF, 02, 54,
|
||||
FC, 01, 42, E3, 00, 4C, 7C, 03,
|
||||
44, D1, 03, 00, CD, 51, 00, 21,
|
||||
8A, 0B, 22, 18, 0C, CD, 3E, 00,
|
||||
FE, 1D, 28, F9, FE, 1F, 28, 05,
|
||||
CD, 4A, 0C, 20, F0, 11, 8A, 0B,
|
||||
06, 08, 1A, FE, 2E, CA, 51, 00,
|
||||
CD, 5A, 02, 2A, 13, 0C, 7D, 84,
|
||||
4F, E5, 21, 00, 08, E5, E5, CD,
|
||||
5A, 02, 23, 7E, E1, 77, 23, 81,
|
||||
4F, 10, F3, CD, 5A, 02, 23, 7E,
|
||||
B9, E1, D1, 20, 07, 01, 08, 00,
|
||||
ED, B0, 18, B3, CD, 40, 02, 18,
|
||||
AE, CD, 51, 00, 06, 00, CD, 35,
|
||||
00, 10, FB, 2A, 4B, 0C, E5, 21,
|
||||
5D, 00, 22, 4B, 0C, CD, FC, 01,
|
||||
E1, 22, 4B, 0C, C3, 51, 00, 2A,
|
||||
0C, 0C, ED, 5B, 0E, 0C, ED, 4B,
|
||||
10, 0C, ED, B0, C9, 00, 00, 00;
|
||||
258
Nasbugt4.coe
Executable file
258
Nasbugt4.coe
Executable file
@@ -0,0 +1,258 @@
|
||||
memory_initialization_radix = 16;
|
||||
memory_initialization_vector =
|
||||
31, 33, 0C, C3, 57, 05, 00, 00,
|
||||
31, 33, 0C, C3, 6D, 03, 00, 00,
|
||||
E5, E1, E1, 23, E5, C3, B5, 05,
|
||||
E5, E1, E1, 23, E5, C3, C2, 05,
|
||||
E3, 2B, E3, C3, 05, 03, 00, 00,
|
||||
E3, 7E, 23, B7, 20, 16, E3, C9,
|
||||
C3, 4A, 0C, 00, 00, AF, F5, F1,
|
||||
F5, F1, 3D, 20, F9, C9, CD, 4D,
|
||||
0C, D8, 18, FA, F7, 18, E2, 00,
|
||||
00, 00, F5, CD, 53, 00, F1, 18,
|
||||
02, 3E, 10, E5, 21, 00, 0C, AE,
|
||||
D3, 00, 77, E1, C9, F7, D3, 01,
|
||||
DB, 02, 87, F8, 18, FA, C3, 47,
|
||||
0C, C5, D5, E5, 3E, 02, CD, 4A,
|
||||
00, 21, 01, 0C, DB, 00, 2F, 77,
|
||||
06, 08, 3E, 01, CD, 4A, 00, 23,
|
||||
DB, 00, 2F, 57, AE, 20, 07, 10,
|
||||
F1, B7, C3, 70, 01, 00, CD, 35,
|
||||
00, DB, 00, 2F, 5F, 7A, AE, 0E,
|
||||
FF, 16, 00, 37, CB, 12, 0C, 1F,
|
||||
30, FA, 7A, A3, 5F, 7E, A2, BB,
|
||||
28, DD, 7E, AA, 77, 7B, B7, 28,
|
||||
D6, 3A, 01, 0C, E6, 10, B0, 87,
|
||||
87, 87, B1, ED, 4B, 3F, 0C, 2A,
|
||||
43, 0C, ED, B1, 28, 0B, 2A, 43,
|
||||
0C, ED, 4B, 3F, 0C, E6, 7F, ED,
|
||||
B1, 20, B6, ED, 4B, 43, 0C, 37,
|
||||
ED, 42, 7D, FE, 41, 38, 1E, FE,
|
||||
5B, 30, 1A, 21, 01, 0C, CB, 66,
|
||||
21, 41, 0C, 20, 08, CB, 46, 28,
|
||||
0C, C6, 20, 18, 08, C6, 20, CB,
|
||||
46, 28, 02, D6, 20, CD, DD, 04,
|
||||
21, 41, 0C, CB, 56, 28, 02, EE,
|
||||
80, 37, CB, 4E, CA, 8A, 00, FE,
|
||||
20, 37, 28, F8, 21, 08, 0C, CB,
|
||||
66, 28, F1, E1, D1, C1, CD, C6,
|
||||
07, CD, 44, 02, B7, C3, 3C, 02,
|
||||
00, 10, 60, 00, 00, 00, D4, 05,
|
||||
55, 07, C3, 05, 03, C3, 3B, 01,
|
||||
C3, F2, 04, B7, C8, C5, D5, E5,
|
||||
F5, FE, 1E, 20, 2F, 21, 09, 08,
|
||||
36, FF, 23, 06, 30, 36, 20, 23,
|
||||
10, FB, 06, 10, 36, 00, 23, 10,
|
||||
FB, EB, 21, 0A, 08, 01, B0, 03,
|
||||
ED, B0, 3E, FF, 32, BA, 0B, 21,
|
||||
8A, 0B, 36, 5F, 22, 18, 0C, F1,
|
||||
E1, D1, C1, C9, 2A, 18, 0C, 36,
|
||||
20, FE, 1D, 20, 0B, 2B, 7E, B7,
|
||||
28, FB, 3C, 20, E5, 23, 18, E2,
|
||||
FE, 1C, 28, DB, FE, 1F, 28, 09,
|
||||
77, 23, 7E, B7, 28, FB, 3C, 20,
|
||||
D1, 11, 0A, 08, 21, 4A, 08, 01,
|
||||
70, 03, ED, B0, 06, 30, 2B, 36,
|
||||
20, 10, FB, 18, BA, 2A, 0C, 0C,
|
||||
CD, 32, 02, 7E, CD, 44, 02, CD,
|
||||
81, 05, 11, 52, 0B, 06, 00, E5,
|
||||
CD, 5A, 02, 7E, B7, 28, 08, 23,
|
||||
7E, E1, 77, 04, 23, 18, F0, E1,
|
||||
1A, FE, 2E, C8, 78, B7, C3, 8D,
|
||||
05, 00, 00, EF, 3E, 00, CD, 3E,
|
||||
00, FE, 1F, 28, 5B, F5, FE, 1D,
|
||||
20, 06, ED, 5B, 18, 0C, 1B, 1A,
|
||||
FE, 3E, 28, 04, F1, F7, 18, E6,
|
||||
F1, AF, 18, F9, CD, 9B, 06, B7,
|
||||
ED, 52, 19, 38, 05, EF, 2E, 1F,
|
||||
00, C9, 0E, 00, EF, 20, 20, 00,
|
||||
CD, 32, 02, 06, 08, 7E, CD, 2B,
|
||||
02, 23, CD, 3C, 02, 10, F6, 79,
|
||||
CD, 44, 02, EF, 1D, 1D, 1F, 00,
|
||||
18, D5, 00, F5, 81, 4F, F1, C3,
|
||||
44, 02, 7C, CD, 2B, 02, 7D, CD,
|
||||
2B, 02, 00, 00, 3E, 20, 18, 17,
|
||||
3E, 1F, 18, 13, F5, 1F, 1F, 1F,
|
||||
1F, CD, 4D, 02, F1, E6, 0F, C6,
|
||||
30, FE, 3A, 38, 02, C6, 07, C3,
|
||||
4A, 0C, 1A, FE, 20, 13, 28, FA,
|
||||
1B, AF, 21, 12, 0C, 77, 23, 77,
|
||||
23, 77, 1A, 2B, 2B, D6, 30, F8,
|
||||
FE, 0A, 38, 08, D6, 07, FE, 0A,
|
||||
F8, FE, 10, F0, 13, 34, 23, ED,
|
||||
6F, 23, ED, 6F, 18, E4, CD, 81,
|
||||
05, 11, 4B, 0B, 01, 0A, 0C, 1A,
|
||||
FE, 20, 20, 05, 0A, FE, 53, 20,
|
||||
ED, 02, 03, 13, AF, 02, 03, CD,
|
||||
5A, 02, 7E, B7, 28, 1C, 23, 7E,
|
||||
02, 23, 03, 7E, 02, 21, 0B, 0C,
|
||||
34, 7E, FE, 04, 38, E8, F5, F1,
|
||||
EF, 45, 72, 72, 6F, 72, 1F, 00,
|
||||
18, C4, 3A, 0A, 0C, 2A, 45, 0C,
|
||||
CD, 66, 04, 11, 86, 02, D5, E9,
|
||||
3E, FF, 32, 1A, 0C, 21, 05, 03,
|
||||
22, 48, 0C, E1, 3A, 0B, 0C, B7,
|
||||
28, 06, 2A, 0C, 0C, 22, 3B, 0C,
|
||||
C1, D1, F1, F1, 2A, 3D, 0C, F9,
|
||||
2A, 3B, 0C, E5, 2A, 37, 0C, F5,
|
||||
3E, 08, D3, 00, F1, ED, 45, AF,
|
||||
32, 1A, 0C, 18, D0, F5, E5, 3A,
|
||||
00, 0C, D3, 00, 3A, 1A, 0C, B7,
|
||||
28, 13, 2A, 15, 0C, 7E, 32, 17,
|
||||
0C, 36, E7, AF, 32, 1A, 0C, 00,
|
||||
00, E1, F1, ED, 45, D5, C5, 21,
|
||||
00, 00, 39, 11, 33, 0C, 31, 33,
|
||||
0C, 01, 08, 00, ED, B0, 5E, 23,
|
||||
56, 23, 00, ED, 53, 3B, 0C, 22,
|
||||
3D, 0C, CD, A5, 05, 06, 06, 2B,
|
||||
7E, CD, 44, 02, 2B, 7E, CD, 44,
|
||||
02, CD, 3C, 02, 10, F1, CD, D9,
|
||||
06, 00, 00, 00, 2A, 15, 0C, 3A,
|
||||
17, 0C, 77, AF, 32, 1A, 0C, CD,
|
||||
A5, 05, C3, 86, 02, 2A, 28, 01,
|
||||
22, 3D, 0C, 18, E7, CD, 3B, 01,
|
||||
C3, 5E, 00, 00, CD, 51, 00, EF,
|
||||
1C, 00, 00, CD, 3E, 00, FE, 2E,
|
||||
28, 09, FE, 1F, 28, 0C, F4, 4A,
|
||||
0C, 18, F0, EF, 1C, 2E, 1F, 00,
|
||||
18, 63, 11, 8A, 0B, CD, 5A, 02,
|
||||
7E, B7, 28, 28, 2A, 13, 0C, 7D,
|
||||
84, 4F, E5, 21, 00, 08, 44, E5,
|
||||
E5, CD, 5A, 02, 23, 7E, E1, 77,
|
||||
23, 81, 4F, 10, F3, CD, 5A, 02,
|
||||
23, 7E, B9, E1, D1, 20, 05, 4C,
|
||||
ED, B0, 18, B3, CD, 40, 02, 18,
|
||||
AE, CD, 51, 00, AF, 47, FF, 10,
|
||||
FD, 2A, 4B, 0C, E5, 21, 75, 03,
|
||||
22, 4B, 0C, CD, 40, 02, CD, FC,
|
||||
01, E1, 22, 4B, 0C, 18, 0E, 2A,
|
||||
0C, 0C, ED, 5B, 0E, 0C, ED, 4B,
|
||||
10, 0C, ED, B0, C9, C3, 51, 00,
|
||||
CD, 51, 00, AF, 47, FF, 10, FD,
|
||||
2A, 0C, 0C, ED, 5B, 0E, 0C, EB,
|
||||
37, ED, 52, DA, 51, 00, EB, AF,
|
||||
FF, 00, 06, 05, AF, CD, 5E, 00,
|
||||
3E, FF, 10, F9, AF, BA, 20, 02,
|
||||
43, 04, 58, 7D, CD, 5E, 00, 7C,
|
||||
CD, 5E, 00, 7B, CD, 5E, 00, 7A,
|
||||
CD, 5E, 00, 0E, 00, CD, 5B, 04,
|
||||
79, CD, 5E, 00, CD, CC, 06, 06,
|
||||
0B, 79, CD, 5E, 00, AF, 10, FA,
|
||||
CD, 40, 02, 18, B6, 1F, 45, 30,
|
||||
1F, 52, 1F, CD, C6, 07, CD, 61,
|
||||
04, CD, 32, 02, EB, C9, D5, 5F,
|
||||
7E, 23, B7, 28, 07, BB, 28, 04,
|
||||
23, 23, 18, F4, 5E, 23, 56, EB,
|
||||
D1, C9, 21, CF, 07, 22, 4E, 0C,
|
||||
21, BA, 04, 22, 4B, 0C, 3A, 0C,
|
||||
0C, 32, 42, 0C, C9, 28, 05, B7,
|
||||
28, 02, CB, FE, E1, 37, C9, 00,
|
||||
2A, 45, 0C, 7E, B7, CA, 40, 02,
|
||||
F7, CD, 3C, 02, 23, 23, 23, 18,
|
||||
F2, 1F, 0D, 1F, 1E, 1B, 1E, 1D,
|
||||
08, 1D, 1C, 0A, 00, 7F, 7F, 00,
|
||||
00, 00, CD, 3B, 01, F5, CD, 02,
|
||||
05, E5, 21, 42, 0C, CB, 7E, CC,
|
||||
CF, 04, CB, BE, E1, F1, C9, CD,
|
||||
ED, 07, FE, 0D, C0, CB, 66, C0,
|
||||
3E, 0A, C3, ED, 07, 21, 01, 0C,
|
||||
FE, 40, 20, 07, CB, 66, C0, F1,
|
||||
C3, 89, 00, CB, 6E, 28, 02, EE,
|
||||
40, C9, CD, 69, 00, D8, DB, 02,
|
||||
17, D0, DB, 01, 37, C9, CD, F2,
|
||||
04, D0, E5, 21, A9, 04, C3, 9A,
|
||||
07, 00, 2A, 0C, 0C, 22, 45, 0C,
|
||||
C9, 00, 3D, 00, CD, 97, 06, B7,
|
||||
ED, 52, 19, D2, FA, 03, 0B, EB,
|
||||
09, EB, 09, 03, ED, B8, C9, CD,
|
||||
9B, 06, EB, E5, 19, CD, 32, 02,
|
||||
E1, B7, ED, 52, CD, 32, 02, 2B,
|
||||
2B, 7C, FE, FF, 20, 0A, CB, 7D,
|
||||
20, 0D, EF, 3F, 3F, 1F, 00, C9,
|
||||
B7, 20, F7, CB, 7D, 20, F3, 7D,
|
||||
CD, 44, 02, C3, 40, 02, 00, 2A,
|
||||
15, 0C, 3A, 17, 0C, 77, 21, 00,
|
||||
0C, 06, 18, 36, 00, 23, 10, FB,
|
||||
21, 28, 01, 11, 3D, 0C, 01, 13,
|
||||
00, ED, B0, EF, 1E, 4E, 41, 53,
|
||||
42, 55, 47, 20, 34, 00, C3, 63,
|
||||
03, E5, 2A, 15, 0C, 7E, 32, 17,
|
||||
0C, E1, C3, DB, 01, 20, 01, 23,
|
||||
1A, FE, 3A, 20, 02, 2B, 2B, FE,
|
||||
2F, 20, 07, 13, CD, 5A, 02, 2A,
|
||||
13, 0C, C3, B0, 01, 2A, 18, 0C,
|
||||
11, 8A, 0B, B7, ED, 52, 21, 3F,
|
||||
0C, C2, 40, 02, C9, 2B, 3B, 3B,
|
||||
F5, D5, 5E, 7B, 17, 9F, 57, 23,
|
||||
18, 0D, 2B, 3B, 3B, F5, D5, 5E,
|
||||
16, 00, 21, 00, 0E, 19, 19, 19,
|
||||
D1, F1, E3, C9, FF, FF, FF, FF,
|
||||
FF, FF, FF, FF, FF, FF, FF, FF,
|
||||
FF, FF, FF, FF, FF, FF, FF, FF,
|
||||
FF, FF, FF, FF, FF, FF, FF, FF,
|
||||
89, 08, 88, 09, 14, 9C, 9B, A3,
|
||||
92, C2, BA, B2, AA, A2, 98, A0,
|
||||
29, 0A, 21, 19, 1A, 1C, 1B, 23,
|
||||
12, 42, 3A, 32, 2A, 22, 18, 20,
|
||||
A9, 8A, A1, 99, 0D, 2C, 41, 13,
|
||||
3B, 33, 43, 10, 40, 2D, 38, 30,
|
||||
28, 31, 39, 25, 1D, 24, 15, 34,
|
||||
45, 35, 11, 2B, 44, 3D, 3C, FF,
|
||||
FF, FF, 9A, FF, 3A, 0C, 0C, 32,
|
||||
41, 0C, C9, 2A, 0C, 0C, 22, 15,
|
||||
0C, C9, CD, 32, 02, CD, C6, 07,
|
||||
3E, 1F, C3, 5D, 00, 00, 00, 00,
|
||||
00, 0E, 00, CD, 3E, 00, 77, 81,
|
||||
4F, 23, 10, F7, CD, 3E, 00, B9,
|
||||
28, 0A, EF, 45, 72, 72, 6F, 72,
|
||||
1F, 00, 18, 08, CD, 40, 02, AF,
|
||||
BA, CA, 51, 00, C3, 0F, 07, ED,
|
||||
4B, 0C, 0C, 3A, 0E, 0C, ED, 79,
|
||||
18, 06, ED, 4B, 0C, 0C, ED, 78,
|
||||
F5, 79, CD, 44, 02, CD, 3C, 02,
|
||||
F1, CD, 44, 02, C3, 40, 02, ED,
|
||||
4B, 10, 0C, ED, 5B, 0E, 0C, 2A,
|
||||
0C, 0C, C9, 21, 55, 04, 06, 06,
|
||||
CD, C6, 07, 7E, CD, 5D, 00, AF,
|
||||
FF, FF, FF, 23, 10, F5, CD, 00,
|
||||
04, AF, FF, 3E, 45, CD, 5D, 00,
|
||||
21, 75, 03, 22, 4B, 0C, 2A, 10,
|
||||
0C, C3, 42, 06, 0E, 00, 7E, 81,
|
||||
4F, 7E, CD, 5E, 00, 23, 10, F6,
|
||||
C9, ED, 57, CD, 44, 02, CD, 3C,
|
||||
02, DD, E5, E1, CD, 32, 02, FD,
|
||||
E5, E1, CD, 32, 02, 3A, 39, 0C,
|
||||
11, FF, 06, 06, 08, 13, 17, F5,
|
||||
1A, DC, 4A, 0C, F1, 10, F6, C9,
|
||||
53, 5A, 00, 48, 00, 50, 4E, 43,
|
||||
00, 00, 00, 00, CD, 51, 00, CD,
|
||||
3E, 00, FE, FF, 20, 0D, 06, 03,
|
||||
CD, 3E, 00, FE, FF, 20, 04, 10,
|
||||
F7, 18, 12, FE, 1E, 20, E8, 06,
|
||||
03, CD, 3E, 00, FE, 1E, 20, E2,
|
||||
10, F7, C3, 51, 00, CD, 3E, 00,
|
||||
6F, CD, 3E, 00, 67, CD, 3E, 00,
|
||||
5F, CD, 3E, 00, 57, 0E, 00, CD,
|
||||
5B, 04, CD, 3E, 00, B9, C2, 62,
|
||||
06, 43, C3, 51, 06, 41, 27, 05,
|
||||
42, 3B, 06, 43, EF, 03, 44, D1,
|
||||
03, 45, D0, 02, 47, A3, 06, 49,
|
||||
14, 05, 4B, 34, 06, 4C, 7C, 03,
|
||||
4D, AD, 01, 4E, C0, 07, 4F, 77,
|
||||
06, 51, 82, 06, 52, 0C, 07, 53,
|
||||
FF, 02, 54, FC, 01, 57, 00, 04,
|
||||
58, 7A, 04, 5A, 0A, 05, 3F, 98,
|
||||
04, 00, B7, 02, CD, 3E, 00, F7,
|
||||
18, FA, F5, CD, 66, 04, B7, 28,
|
||||
04, F1, 7D, E1, C9, F1, E1, C9,
|
||||
CD, AE, 07, C3, 3B, 01, E5, 21,
|
||||
AA, 04, 18, E6, 21, FE, 04, 22,
|
||||
4E, 0C, 21, A8, 07, E5, 18, 0A,
|
||||
2A, 39, 01, 22, 4E, 0C, E5, 2A,
|
||||
36, 01, 22, 4B, 0C, E1, C9, CD,
|
||||
69, 00, D8, CD, F6, 04, D0, E6,
|
||||
7F, E5, F5, 21, 42, 0C, CB, 6E,
|
||||
CC, CF, 04, F1, CD, AE, 07, FE,
|
||||
1E, C3, 8D, 04, 00, B7, C8, F5,
|
||||
EA, F5, 07, EE, 80, CB, 46, 28,
|
||||
02, EE, 80, CD, 5E, 00, F1, C9;
|
||||
258
Naschr-1.coe
Executable file
258
Naschr-1.coe
Executable file
@@ -0,0 +1,258 @@
|
||||
memory_initialization_radix = 16;
|
||||
memory_initialization_vector =
|
||||
7F, 41, 41, 41, 41, 41, 41, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 40, 40, 40, 40, 40, 40, 40,
|
||||
40, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 08, 08, 08, 08, 08, 08, 08,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
01, 01, 01, 01, 01, 01, 01, 01,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
20, 10, 08, 04, 3E, 10, 08, 04,
|
||||
02, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 63, 55, 49, 55, 63, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 01, 02, 04, 48, 50, 60, 40,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 41, 7F, 14, 14,
|
||||
77, 00, 00, 00, 00, 00, 00, 00,
|
||||
10, 20, 7C, 22, 11, 01, 01, 01,
|
||||
01, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 04, 02, 7F, 02, 04, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 00, 00, 00, 7F, 00, 00, 00,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 08, 08, 49, 2A, 1C, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 08, 2A, 1C, 08, 49, 2A, 1C,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 10, 20, 7F, 20, 10, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 63, 55, 49, 55, 63, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 49, 41, 41, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 41, 41, 7F, 41, 41, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 2A, 49, 49, 4F, 41, 41, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 4F, 49, 49, 2A,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 79, 49, 49, 2A,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 2A, 49, 49, 79, 41, 41, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 11, 0A, 04, 4A, 51, 60, 40,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 22, 22, 22, 22, 22, 22, 22,
|
||||
63, 00, 00, 00, 00, 00, 00, 00,
|
||||
01, 01, 01, 01, 7F, 01, 01, 01,
|
||||
01, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 22, 14, 08, 14, 22, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 08, 08, 1C, 1C, 08, 08, 08,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
3C, 42, 42, 40, 30, 08, 08, 00,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 7F, 41, 41, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 49, 49, 49, 79, 41, 41, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 41, 41, 79, 49, 49, 49,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 41, 41, 4F, 49, 49, 49,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 49, 49, 49, 4F, 41, 41, 41,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 08, 08, 08, 08, 00, 00, 08,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
24, 24, 24, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 20, 20, 70, 20, 20, 21,
|
||||
7E, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 3F, 48, 48, 3E, 09, 09, 7E,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
20, 51, 22, 04, 08, 10, 22, 45,
|
||||
02, 00, 00, 00, 00, 00, 00, 00,
|
||||
38, 44, 44, 28, 10, 29, 46, 46,
|
||||
39, 00, 00, 00, 00, 00, 00, 00,
|
||||
0C, 0C, 08, 10, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
04, 08, 10, 10, 10, 10, 10, 08,
|
||||
04, 00, 00, 00, 00, 00, 00, 00,
|
||||
10, 08, 04, 04, 04, 04, 04, 08,
|
||||
10, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 49, 2A, 1C, 2A, 49, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 08, 08, 7F, 08, 08, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 18,
|
||||
18, 10, 20, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 7F, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 18,
|
||||
18, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 01, 02, 04, 08, 10, 20, 40,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 43, 45, 49, 51, 61, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 18, 28, 08, 08, 08, 08, 08,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 01, 02, 1C, 20, 40, 40,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 01, 01, 1E, 01, 01, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
02, 06, 0A, 12, 22, 42, 7F, 02,
|
||||
02, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 40, 40, 7C, 02, 01, 01, 42,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
1E, 20, 40, 40, 7E, 41, 41, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 41, 02, 04, 08, 10, 10, 10,
|
||||
10, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 41, 41, 3E, 41, 41, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 41, 41, 3F, 01, 01, 02,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 18, 18, 00, 00, 18,
|
||||
18, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 18, 18, 00, 00, 18,
|
||||
18, 10, 20, 00, 00, 00, 00, 00,
|
||||
04, 08, 10, 20, 40, 20, 10, 08,
|
||||
04, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3E, 00, 3E, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
10, 08, 04, 02, 01, 02, 04, 08,
|
||||
10, 00, 00, 00, 00, 00, 00, 00,
|
||||
1E, 21, 21, 01, 06, 08, 08, 00,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
1E, 21, 4D, 55, 55, 5E, 40, 20,
|
||||
1E, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 7F, 41, 41, 41,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
7E, 21, 21, 21, 3E, 21, 21, 21,
|
||||
7E, 00, 00, 00, 00, 00, 00, 00,
|
||||
1E, 21, 40, 40, 40, 40, 40, 21,
|
||||
1E, 00, 00, 00, 00, 00, 00, 00,
|
||||
7C, 22, 21, 21, 21, 21, 21, 22,
|
||||
7C, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 40, 40, 40, 78, 40, 40, 40,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 40, 40, 40, 78, 40, 40, 40,
|
||||
40, 00, 00, 00, 00, 00, 00, 00,
|
||||
1E, 21, 40, 40, 40, 4F, 41, 21,
|
||||
1E, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 41, 41, 7F, 41, 41, 41,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 08, 08, 08, 08, 08, 08, 08,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
1F, 04, 04, 04, 04, 04, 04, 44,
|
||||
38, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 42, 44, 48, 50, 68, 44, 42,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
40, 40, 40, 40, 40, 40, 40, 40,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 63, 55, 49, 49, 41, 41, 41,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 61, 51, 49, 45, 43, 41, 41,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 41, 41, 41, 22,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
7E, 41, 41, 41, 7E, 40, 40, 40,
|
||||
40, 00, 00, 00, 00, 00, 00, 00,
|
||||
1C, 22, 41, 41, 41, 49, 45, 22,
|
||||
1D, 00, 00, 00, 00, 00, 00, 00,
|
||||
7E, 41, 41, 41, 7E, 48, 44, 42,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
3E, 41, 40, 40, 3E, 01, 01, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 08, 08, 08, 08, 08, 08, 08,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 41, 41, 41, 41, 41, 41,
|
||||
3E, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 41, 22, 22, 14, 14, 08,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 41, 41, 49, 49, 55, 63,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 22, 14, 08, 14, 22, 41,
|
||||
41, 00, 00, 00, 00, 00, 00, 00,
|
||||
41, 41, 22, 14, 08, 08, 08, 08,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 01, 02, 04, 08, 10, 20, 40,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
3C, 20, 20, 20, 20, 20, 20, 20,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 40, 20, 10, 08, 04, 02, 01,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
3C, 04, 04, 04, 04, 04, 04, 04,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 1C, 2A, 49, 08, 08, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
18, 18, 08, 04, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3C, 02, 3E, 42, 42,
|
||||
3D, 00, 00, 00, 00, 00, 00, 00,
|
||||
40, 40, 40, 5C, 62, 42, 42, 62,
|
||||
5C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3C, 42, 40, 40, 42,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
02, 02, 02, 3A, 46, 42, 42, 46,
|
||||
3A, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3C, 42, 7E, 40, 40,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
0C, 12, 10, 10, 7C, 10, 10, 10,
|
||||
10, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3A, 46, 42, 42, 46,
|
||||
3A, 02, 42, 3C, 00, 00, 00, 00,
|
||||
40, 40, 40, 5C, 62, 42, 42, 42,
|
||||
42, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 08, 00, 18, 08, 08, 08, 08,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 02, 00, 06, 02, 02, 02, 02,
|
||||
02, 02, 22, 1C, 00, 00, 00, 00,
|
||||
40, 40, 40, 44, 48, 50, 68, 44,
|
||||
42, 00, 00, 00, 00, 00, 00, 00,
|
||||
18, 08, 08, 08, 08, 08, 08, 08,
|
||||
1C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 76, 49, 49, 49, 49,
|
||||
49, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 5C, 62, 42, 42, 42,
|
||||
42, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3C, 42, 42, 42, 42,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 5C, 62, 42, 42, 62,
|
||||
5C, 40, 40, 40, 00, 00, 00, 00,
|
||||
00, 00, 00, 3A, 46, 42, 42, 46,
|
||||
3A, 02, 02, 02, 00, 00, 00, 00,
|
||||
00, 00, 00, 5C, 62, 40, 40, 40,
|
||||
40, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 3C, 42, 30, 0C, 42,
|
||||
3C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 10, 10, 7C, 10, 10, 10, 12,
|
||||
0C, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 42, 42, 42, 42, 46,
|
||||
3A, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 41, 41, 41, 22, 14,
|
||||
08, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 41, 49, 49, 49, 49,
|
||||
36, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 42, 24, 18, 18, 24,
|
||||
42, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 42, 42, 42, 42, 46,
|
||||
3A, 02, 42, 3C, 00, 00, 00, 00,
|
||||
00, 00, 00, 7E, 04, 08, 10, 20,
|
||||
7E, 00, 00, 00, 00, 00, 00, 00,
|
||||
0C, 10, 10, 10, 20, 10, 10, 10,
|
||||
0C, 00, 00, 00, 00, 00, 00, 00,
|
||||
08, 08, 08, 00, 00, 08, 08, 08,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
18, 04, 04, 04, 02, 04, 04, 04,
|
||||
18, 00, 00, 00, 00, 00, 00, 00,
|
||||
7F, 00, 00, 00, 00, 00, 00, 00,
|
||||
00, 00, 00, 00, 00, 00, 00, 00,
|
||||
24, 49, 12, 24, 49, 12, 24, 49,
|
||||
12, 00, 00, 00, 00, 00, 00, 00;
|
||||
29
ROM_form.coe
Executable file
29
ROM_form.coe
Executable file
@@ -0,0 +1,29 @@
|
||||
component_name={name};
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
|
||||
350
ROM_form.v
Executable file
350
ROM_form.v
Executable file
@@ -0,0 +1,350 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 1.02
|
||||
// \ \ Filename: ROM_form.v
|
||||
// / / Date Last Modified: September 7 2004
|
||||
// /___/ /\ Date Created: July 2003
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Xilinx
|
||||
//Purpose:
|
||||
// This is the Verilog template file for the KCPSM3 assembler.
|
||||
// It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block
|
||||
// RAM to act as a single port program ROM.
|
||||
//
|
||||
// This Verilog file is not valid as input directly into a synthesis or
|
||||
// simulation tool. The assembler will read this template and insert the
|
||||
// data required to complete the definition of program ROM and write it out
|
||||
// to a new '.v' file associated with the name of the original '.psm' file
|
||||
// being assembled.
|
||||
//
|
||||
// This template can be modified to define alternative memory definitions
|
||||
// such as dual port. However, you are responsible for ensuring the template
|
||||
// is correct as the assembler does not perform any checking of the Verilog.
|
||||
//
|
||||
// The assembler identifies all text enclosed by {} characters, and replaces
|
||||
// these character strings. All templates should include these {} character
|
||||
// strings for the assembler to work correctly.
|
||||
//
|
||||
// This template defines a block RAM configured in 1024 x 18-bit single port
|
||||
// mode and conneceted to act as a single port ROM.
|
||||
//
|
||||
//Reference:
|
||||
// None
|
||||
//Revision History:
|
||||
// Rev 1.00 - jc - Converted to verilog, July 2003.
|
||||
// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004.
|
||||
// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004.
|
||||
// Rev 1.03 - sus - Added text to conform to Xilinx generated
|
||||
// HDL spec, September 7 2004
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Contact: e-mail picoblaze@xilinx.com
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Disclaimer:
|
||||
// LIMITED WARRANTY AND DISCLAIMER. These designs are
|
||||
// provided to you "as is". Xilinx and its licensors make and you
|
||||
// receive no warranties or conditions, express, implied,
|
||||
// statutory or otherwise, and Xilinx specifically disclaims any
|
||||
// implied warranties of merchantability, non-infringement, or
|
||||
// fitness for a particular purpose. Xilinx does not warrant that
|
||||
// the functions contained in these designs will meet your
|
||||
// requirements, or that the operation of these designs will be
|
||||
// uninterrupted or error free, or that defects in the Designs
|
||||
// will be corrected. Furthermore, Xilinx does not warrant or
|
||||
// make any representations regarding use or the results of the
|
||||
// use of the designs in terms of correctness, accuracy,
|
||||
// reliability, or otherwise.
|
||||
//
|
||||
// LIMITATION OF LIABILITY. In no event will Xilinx or its
|
||||
// licensors be liable for any loss of data, lost profits, cost
|
||||
// or procurement of substitute goods or services, or for any
|
||||
// special, incidental, consequential, or indirect damages
|
||||
// arising from the use or operation of the designs or
|
||||
// accompanying documentation, however caused and on any theory
|
||||
// of liability. This limitation will apply even if Xilinx
|
||||
// has been advised of the possibility of such damage. This
|
||||
// limitation shall apply not-withstanding the failure of the
|
||||
// essential purpose of any limited remedies herein.
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: {name}.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 {name}.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: {name}
|
||||
//Generated {timestamp}.
|
||||
//Purpose:
|
||||
// {name} verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1 ps / 1ps
|
||||
|
||||
module {name} (address, instruction, clk);
|
||||
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
|
||||
output [17:0] instruction;
|
||||
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "{INIT_00}"
|
||||
init_01 = "{INIT_01}"
|
||||
init_02 = "{INIT_02}"
|
||||
init_03 = "{INIT_03}"
|
||||
init_04 = "{INIT_04}"
|
||||
init_05 = "{INIT_05}"
|
||||
init_06 = "{INIT_06}"
|
||||
init_07 = "{INIT_07}"
|
||||
init_08 = "{INIT_08}"
|
||||
init_09 = "{INIT_09}"
|
||||
init_0A = "{INIT_0A}"
|
||||
init_0B = "{INIT_0B}"
|
||||
init_0C = "{INIT_0C}"
|
||||
init_0D = "{INIT_0D}"
|
||||
init_0E = "{INIT_0E}"
|
||||
init_0F = "{INIT_0F}"
|
||||
init_10 = "{INIT_10}"
|
||||
init_11 = "{INIT_11}"
|
||||
init_12 = "{INIT_12}"
|
||||
init_13 = "{INIT_13}"
|
||||
init_14 = "{INIT_14}"
|
||||
init_15 = "{INIT_15}"
|
||||
init_16 = "{INIT_16}"
|
||||
init_17 = "{INIT_17}"
|
||||
init_18 = "{INIT_18}"
|
||||
init_19 = "{INIT_19}"
|
||||
init_1A = "{INIT_1A}"
|
||||
init_1B = "{INIT_1B}"
|
||||
init_1C = "{INIT_1C}"
|
||||
init_1D = "{INIT_1D}"
|
||||
init_1E = "{INIT_1E}"
|
||||
init_1F = "{INIT_1F}"
|
||||
init_20 = "{INIT_20}"
|
||||
init_21 = "{INIT_21}"
|
||||
init_22 = "{INIT_22}"
|
||||
init_23 = "{INIT_23}"
|
||||
init_24 = "{INIT_24}"
|
||||
init_25 = "{INIT_25}"
|
||||
init_26 = "{INIT_26}"
|
||||
init_27 = "{INIT_27}"
|
||||
init_28 = "{INIT_28}"
|
||||
init_29 = "{INIT_29}"
|
||||
init_2A = "{INIT_2A}"
|
||||
init_2B = "{INIT_2B}"
|
||||
init_2C = "{INIT_2C}"
|
||||
init_2D = "{INIT_2D}"
|
||||
init_2E = "{INIT_2E}"
|
||||
init_2F = "{INIT_2F}"
|
||||
init_30 = "{INIT_30}"
|
||||
init_31 = "{INIT_31}"
|
||||
init_32 = "{INIT_32}"
|
||||
init_33 = "{INIT_33}"
|
||||
init_34 = "{INIT_34}"
|
||||
init_35 = "{INIT_35}"
|
||||
init_36 = "{INIT_36}"
|
||||
init_37 = "{INIT_37}"
|
||||
init_38 = "{INIT_38}"
|
||||
init_39 = "{INIT_39}"
|
||||
init_3A = "{INIT_3A}"
|
||||
init_3B = "{INIT_3B}"
|
||||
init_3C = "{INIT_3C}"
|
||||
init_3D = "{INIT_3D}"
|
||||
init_3E = "{INIT_3E}"
|
||||
init_3F = "{INIT_3F}"
|
||||
initp_00 = "{INITP_00}"
|
||||
initp_01 = "{INITP_01}"
|
||||
initp_02 = "{INITP_02}"
|
||||
initp_03 = "{INITP_03}"
|
||||
initp_04 = "{INITP_04}"
|
||||
initp_05 = "{INITP_05}"
|
||||
initp_06 = "{INITP_06}"
|
||||
initp_07 = "{INITP_07}" */;
|
||||
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h{INIT_00};
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h{INIT_01};
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h{INIT_02};
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h{INIT_03};
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h{INIT_04};
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h{INIT_05};
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h{INIT_06};
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h{INIT_07};
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h{INIT_08};
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h{INIT_09};
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h{INIT_0A};
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h{INIT_0B};
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h{INIT_0C};
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h{INIT_0D};
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h{INIT_0E};
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h{INIT_0F};
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h{INIT_10};
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h{INIT_11};
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h{INIT_12};
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h{INIT_13};
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h{INIT_14};
|
||||
defparam ram_1024_x_18.INIT_15 = 256'h{INIT_15};
|
||||
defparam ram_1024_x_18.INIT_16 = 256'h{INIT_16};
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h{INIT_17};
|
||||
defparam ram_1024_x_18.INIT_18 = 256'h{INIT_18};
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h{INIT_19};
|
||||
defparam ram_1024_x_18.INIT_1A = 256'h{INIT_1A};
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h{INIT_1B};
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h{INIT_1C};
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h{INIT_1D};
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h{INIT_1E};
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h{INIT_1F};
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h{INIT_20};
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h{INIT_21};
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h{INIT_22};
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h{INIT_23};
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h{INIT_24};
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h{INIT_25};
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h{INIT_26};
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h{INIT_27};
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h{INIT_28};
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h{INIT_29};
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h{INIT_2A};
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h{INIT_2B};
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h{INIT_2C};
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h{INIT_2D};
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h{INIT_2E};
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h{INIT_2F};
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h{INIT_30};
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h{INIT_31};
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h{INIT_32};
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h{INIT_33};
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h{INIT_34};
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h{INIT_35};
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h{INIT_36};
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h{INIT_37};
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h{INIT_38};
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h{INIT_39};
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h{INIT_3A};
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h{INIT_3B};
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h{INIT_3C};
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h{INIT_3D};
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h{INIT_3E};
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h{INIT_3F};
|
||||
defparam ram_1024_x_18.INITP_00 = 256'h{INITP_00};
|
||||
defparam ram_1024_x_18.INITP_01 = 256'h{INITP_01};
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h{INITP_02};
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h{INITP_03};
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h{INITP_04};
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h{INITP_05};
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h{INITP_06};
|
||||
defparam ram_1024_x_18.INITP_07 = 256'h{INITP_07};
|
||||
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "{INIT_00}"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "{INIT_01}"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "{INIT_02}"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "{INIT_03}"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "{INIT_04}"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "{INIT_05}"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "{INIT_06}"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "{INIT_07}"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "{INIT_08}"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "{INIT_09}"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "{INIT_0A}"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "{INIT_0B}"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "{INIT_0C}"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "{INIT_0D}"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "{INIT_0E}"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "{INIT_0F}"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "{INIT_10}"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "{INIT_11}"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "{INIT_12}"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "{INIT_13}"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "{INIT_14}"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "{INIT_15}"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "{INIT_16}"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "{INIT_17}"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "{INIT_18}"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "{INIT_19}"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "{INIT_1A}"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "{INIT_1B}"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "{INIT_1C}"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "{INIT_1D}"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "{INIT_1E}"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "{INIT_1F}"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "{INIT_20}"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "{INIT_21}"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "{INIT_22}"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "{INIT_23}"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "{INIT_24}"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "{INIT_25}"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "{INIT_26}"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "{INIT_27}"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "{INIT_28}"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "{INIT_29}"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "{INIT_2A}"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "{INIT_2B}"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "{INIT_2C}"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "{INIT_2D}"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "{INIT_2E}"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "{INIT_2F}"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "{INIT_30}"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "{INIT_31}"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "{INIT_32}"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "{INIT_33}"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "{INIT_34}"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "{INIT_35}"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "{INIT_36}"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "{INIT_37}"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "{INIT_38}"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "{INIT_39}"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "{INIT_3A}"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "{INIT_3B}"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "{INIT_3C}"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "{INIT_3D}"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "{INIT_3E}"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "{INIT_3F}"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}"
|
||||
|
||||
endmodule
|
||||
|
||||
// END OF FILE {name}.v
|
||||
305
ROM_form.vhd
Executable file
305
ROM_form.vhd
Executable file
@@ -0,0 +1,305 @@
|
||||
ROM_form.vhd
|
||||
|
||||
Ken Chapman (Xilinx Ltd) July 2003
|
||||
|
||||
This is the VHDL template file for the KCPSM3 assembler.
|
||||
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
|
||||
a single port program ROM.
|
||||
|
||||
This VHDL file is not valid as input directly into a synthesis or simulation tool.
|
||||
The assembler will read this template and insert the data required to complete the
|
||||
definition of program ROM and write it out to a new '.vhd' file associated with the
|
||||
name of the original '.psm' file being assembled.
|
||||
|
||||
This template can be modified to define alternative memory definitions such as dual port.
|
||||
However, you are responsible for ensuring the template is correct as the assembler does
|
||||
not perform any checking of the VHDL.
|
||||
|
||||
The assembler identifies all text enclosed by {} characters, and replaces these
|
||||
character strings. All templates should include these {} character strings for
|
||||
the assembler to work correctly.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
This template defines a block RAM configured in 1024 x 18-bit single port mode and
|
||||
conneceted to act as a single port ROM.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler {timestamp}.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity {name} is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end {name};
|
||||
--
|
||||
architecture low_level_definition of {name} is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"{INIT_00}",
|
||||
INIT_01 => X"{INIT_01}",
|
||||
INIT_02 => X"{INIT_02}",
|
||||
INIT_03 => X"{INIT_03}",
|
||||
INIT_04 => X"{INIT_04}",
|
||||
INIT_05 => X"{INIT_05}",
|
||||
INIT_06 => X"{INIT_06}",
|
||||
INIT_07 => X"{INIT_07}",
|
||||
INIT_08 => X"{INIT_08}",
|
||||
INIT_09 => X"{INIT_09}",
|
||||
INIT_0A => X"{INIT_0A}",
|
||||
INIT_0B => X"{INIT_0B}",
|
||||
INIT_0C => X"{INIT_0C}",
|
||||
INIT_0D => X"{INIT_0D}",
|
||||
INIT_0E => X"{INIT_0E}",
|
||||
INIT_0F => X"{INIT_0F}",
|
||||
INIT_10 => X"{INIT_10}",
|
||||
INIT_11 => X"{INIT_11}",
|
||||
INIT_12 => X"{INIT_12}",
|
||||
INIT_13 => X"{INIT_13}",
|
||||
INIT_14 => X"{INIT_14}",
|
||||
INIT_15 => X"{INIT_15}",
|
||||
INIT_16 => X"{INIT_16}",
|
||||
INIT_17 => X"{INIT_17}",
|
||||
INIT_18 => X"{INIT_18}",
|
||||
INIT_19 => X"{INIT_19}",
|
||||
INIT_1A => X"{INIT_1A}",
|
||||
INIT_1B => X"{INIT_1B}",
|
||||
INIT_1C => X"{INIT_1C}",
|
||||
INIT_1D => X"{INIT_1D}",
|
||||
INIT_1E => X"{INIT_1E}",
|
||||
INIT_1F => X"{INIT_1F}",
|
||||
INIT_20 => X"{INIT_20}",
|
||||
INIT_21 => X"{INIT_21}",
|
||||
INIT_22 => X"{INIT_22}",
|
||||
INIT_23 => X"{INIT_23}",
|
||||
INIT_24 => X"{INIT_24}",
|
||||
INIT_25 => X"{INIT_25}",
|
||||
INIT_26 => X"{INIT_26}",
|
||||
INIT_27 => X"{INIT_27}",
|
||||
INIT_28 => X"{INIT_28}",
|
||||
INIT_29 => X"{INIT_29}",
|
||||
INIT_2A => X"{INIT_2A}",
|
||||
INIT_2B => X"{INIT_2B}",
|
||||
INIT_2C => X"{INIT_2C}",
|
||||
INIT_2D => X"{INIT_2D}",
|
||||
INIT_2E => X"{INIT_2E}",
|
||||
INIT_2F => X"{INIT_2F}",
|
||||
INIT_30 => X"{INIT_30}",
|
||||
INIT_31 => X"{INIT_31}",
|
||||
INIT_32 => X"{INIT_32}",
|
||||
INIT_33 => X"{INIT_33}",
|
||||
INIT_34 => X"{INIT_34}",
|
||||
INIT_35 => X"{INIT_35}",
|
||||
INIT_36 => X"{INIT_36}",
|
||||
INIT_37 => X"{INIT_37}",
|
||||
INIT_38 => X"{INIT_38}",
|
||||
INIT_39 => X"{INIT_39}",
|
||||
INIT_3A => X"{INIT_3A}",
|
||||
INIT_3B => X"{INIT_3B}",
|
||||
INIT_3C => X"{INIT_3C}",
|
||||
INIT_3D => X"{INIT_3D}",
|
||||
INIT_3E => X"{INIT_3E}",
|
||||
INIT_3F => X"{INIT_3F}",
|
||||
INITP_00 => X"{INITP_00}",
|
||||
INITP_01 => X"{INITP_01}",
|
||||
INITP_02 => X"{INITP_02}",
|
||||
INITP_03 => X"{INITP_03}",
|
||||
INITP_04 => X"{INITP_04}",
|
||||
INITP_05 => X"{INITP_05}",
|
||||
INITP_06 => X"{INITP_06}",
|
||||
INITP_07 => X"{INITP_07}")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE {name}.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
351
T80_ALU.vhd
Executable file
351
T80_ALU.vhd
Executable file
@@ -0,0 +1,351 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
|
||||
end;
|
||||
1934
T80_MCode.vhd
Executable file
1934
T80_MCode.vhd
Executable file
File diff suppressed because it is too large
Load Diff
208
T80_Pack.vhd
Executable file
208
T80_Pack.vhd
Executable file
@@ -0,0 +1,208 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
105
T80_Reg.vhd
Executable file
105
T80_Reg.vhd
Executable file
@@ -0,0 +1,105 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
170
T80_RegX.vhd
Executable file
170
T80_RegX.vhd
Executable file
@@ -0,0 +1,170 @@
|
||||
--
|
||||
-- T80 Registers for Xilinx Select RAM
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Removed UNISIM library and added componet declaration
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
-- component RAM16X1D
|
||||
-- port(
|
||||
-- DPO : out std_ulogic;
|
||||
-- SPO : out std_ulogic;
|
||||
-- A0 : in std_ulogic;
|
||||
-- A1 : in std_ulogic;
|
||||
-- A2 : in std_ulogic;
|
||||
-- A3 : in std_ulogic;
|
||||
-- D : in std_ulogic;
|
||||
-- DPRA0 : in std_ulogic;
|
||||
-- DPRA1 : in std_ulogic;
|
||||
-- DPRA2 : in std_ulogic;
|
||||
-- DPRA3 : in std_ulogic;
|
||||
-- WCLK : in std_ulogic;
|
||||
-- WE : in std_ulogic);
|
||||
-- end component;
|
||||
|
||||
signal ENH : std_logic;
|
||||
signal ENL : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
ENH <= CEN and WEH;
|
||||
ENL <= CEN and WEL;
|
||||
|
||||
bG1: for I in 0 to 7 generate
|
||||
begin
|
||||
Reg1H : RAM16X1D
|
||||
port map(
|
||||
DPO => DOBH(i),
|
||||
SPO => DOAH(i),
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIH(i),
|
||||
DPRA0 => AddrB(0),
|
||||
DPRA1 => AddrB(1),
|
||||
DPRA2 => AddrB(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENH);
|
||||
Reg1L : RAM16X1D
|
||||
port map(
|
||||
DPO => DOBL(i),
|
||||
SPO => DOAL(i),
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIL(i),
|
||||
DPRA0 => AddrB(0),
|
||||
DPRA1 => AddrB(1),
|
||||
DPRA2 => AddrB(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENL);
|
||||
Reg2H : RAM16X1D
|
||||
port map(
|
||||
DPO => DOCH(i),
|
||||
SPO => open,
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIH(i),
|
||||
DPRA0 => AddrC(0),
|
||||
DPRA1 => AddrC(1),
|
||||
DPRA2 => AddrC(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENH);
|
||||
Reg2L : RAM16X1D
|
||||
port map(
|
||||
DPO => DOCL(i),
|
||||
SPO => open,
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIL(i),
|
||||
DPRA0 => AddrC(0),
|
||||
DPRA1 => AddrC(1),
|
||||
DPRA2 => AddrC(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENL);
|
||||
end generate;
|
||||
|
||||
end;
|
||||
255
T80a.vhd
Executable file
255
T80a.vhd
Executable file
@@ -0,0 +1,255 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core, asynchronous top level
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0208 : First complete release
|
||||
--
|
||||
-- 0211 : Fixed interrupt cycle
|
||||
--
|
||||
-- 0235 : Updated for T80 interface change
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
-- 0247 : Fixed bus req/ack cycle
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80a is
|
||||
generic(
|
||||
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DIN : in std_logic_vector(7 downto 0);
|
||||
DOUT : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80a;
|
||||
|
||||
architecture rtl of T80a is
|
||||
|
||||
signal CEN : std_logic;
|
||||
signal Reset_s : std_logic;
|
||||
signal IntCycle_n : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal MREQ : std_logic;
|
||||
signal MReq_Inhibit : std_logic;
|
||||
signal Req_Inhibit : std_logic;
|
||||
signal RD : std_logic;
|
||||
signal MREQ_n_i : std_logic;
|
||||
signal IORQ_n_i : std_logic;
|
||||
signal RD_n_i : std_logic;
|
||||
signal WR_n_i : std_logic;
|
||||
signal RFSH_n_i : std_logic;
|
||||
signal BUSAK_n_i : std_logic;
|
||||
signal A_i : std_logic_vector(15 downto 0);
|
||||
signal DO : std_logic_vector(7 downto 0);
|
||||
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||
signal Wait_s : std_logic;
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
CEN <= '1';
|
||||
|
||||
BUSAK_n <= BUSAK_n_i;
|
||||
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
|
||||
RD_n_i <= not RD or Req_Inhibit;
|
||||
|
||||
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
|
||||
-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
|
||||
DOUT <= DO;
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
Reset_s <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
Reset_s <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n_i,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_s,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => Reset_s,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n_i,
|
||||
CLK_n => CLK_n,
|
||||
A => A_i,
|
||||
DInst => DIN,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (CLK_n)
|
||||
begin
|
||||
if CLK_n'event and CLK_n = '0' then
|
||||
Wait_s <= WAIT_n;
|
||||
if TState = "011" and BUSAK_n_i = '1' then
|
||||
DI_Reg <= DIN;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
WR_n_i <= '1';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
WR_n_i <= '1';
|
||||
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
|
||||
WR_n_i <= not Write;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
Req_Inhibit <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if MCycle = "001" and TState = "010" then
|
||||
Req_Inhibit <= '1';
|
||||
else
|
||||
Req_Inhibit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
MReq_Inhibit <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if MCycle = "001" and TState = "010" then
|
||||
MReq_Inhibit <= '1';
|
||||
else
|
||||
MReq_Inhibit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
|
||||
if MCycle = "001" then
|
||||
if TState = "001" then
|
||||
RD <= IntCycle_n;
|
||||
MREQ <= IntCycle_n;
|
||||
IORQ_n_i <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '1';
|
||||
end if;
|
||||
if TState = "100" then
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
else
|
||||
if TState = "001" and NoRead = '0' then
|
||||
RD <= not Write;
|
||||
IORQ_n_i <= not IORQ;
|
||||
MREQ <= not IORQ;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
190
T80s.vhd
Executable file
190
T80s.vhd
Executable file
@@ -0,0 +1,190 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0208 : First complete release
|
||||
--
|
||||
-- 0210 : Fixed read with wait
|
||||
--
|
||||
-- 0211 : Fixed interrupt cycle
|
||||
--
|
||||
-- 0235 : Updated for T80 interface change
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80s is
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80s;
|
||||
|
||||
architecture rtl of T80s is
|
||||
|
||||
signal CEN : std_logic;
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
CEN <= '1';
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => IOWait)
|
||||
port map(
|
||||
CEN => CEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if T2Write = 0 then
|
||||
if TState = "010" and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
184
T80se.vhd
Executable file
184
T80se.vhd
Executable file
@@ -0,0 +1,184 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0235 : First release
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80se is
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80se;
|
||||
|
||||
architecture rtl of T80se is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => IOWait)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if CLKEN = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if T2Write = 0 then
|
||||
if TState = "010" and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
8192
coregen/basic_rom.mif
Executable file
8192
coregen/basic_rom.mif
Executable file
File diff suppressed because it is too large
Load Diff
3
coregen/basic_rom.ngc
Executable file
3
coregen/basic_rom.ngc
Executable file
File diff suppressed because one or more lines are too long
121
coregen/basic_rom.vhd
Executable file
121
coregen/basic_rom.vhd
Executable file
@@ -0,0 +1,121 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file basic_rom.vhd when simulating
|
||||
-- the core, basic_rom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY basic_rom IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(12 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END basic_rom;
|
||||
|
||||
ARCHITECTURE basic_rom_a OF basic_rom IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_basic_rom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(12 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_basic_rom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "basic_rom.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 8192,
|
||||
c_write_depth_a => 8192,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 13,
|
||||
c_addrb_width => 13,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 8192,
|
||||
c_read_depth_a => 8192,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 1,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_basic_rom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END basic_rom_a;
|
||||
|
||||
58
coregen/basic_rom.vho
Executable file
58
coregen/basic_rom.vho
Executable file
@@ -0,0 +1,58 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component basic_rom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(12 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : basic_rom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file basic_rom.vhd when simulating
|
||||
-- the core, basic_rom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
78
coregen/basic_rom.xco
Executable file
78
coregen/basic_rom.xco
Executable file
@@ -0,0 +1,78 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Fri Jan 09 14:26:54 2009
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=C:/vhdl/Basic.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=basic_rom
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET enable_a=Use_ENA_Pin
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=8
|
||||
CSET read_width_b=8
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET single_bit_ecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_ramb16bwer_reset_behavior=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_ssra_pin=false
|
||||
CSET use_ssrb_pin=false
|
||||
CSET write_depth_a=8192
|
||||
CSET write_width_a=8
|
||||
CSET write_width_b=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 1cd67ff3
|
||||
|
||||
24
coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
24
coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
@@ -0,0 +1,24 @@
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\basic_rom_blk_mem_gen_v2_6_xst_1.vhd"
|
||||
9
coregen/basic_rom_flist.txt
Executable file
9
coregen/basic_rom_flist.txt
Executable file
@@ -0,0 +1,9 @@
|
||||
# Output products list for <basic_rom>
|
||||
basic_rom.mif
|
||||
basic_rom.ngc
|
||||
basic_rom.vhd
|
||||
basic_rom.vho
|
||||
basic_rom.xco
|
||||
basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
basic_rom_flist.txt
|
||||
basic_rom_xmdf.tcl
|
||||
45
coregen/basic_rom_readme.txt
Executable file
45
coregen/basic_rom_readme.txt
Executable file
@@ -0,0 +1,45 @@
|
||||
The following files were generated for 'basic_rom' in directory
|
||||
C:\vhdl\nascom2_t80\coregen\:
|
||||
|
||||
basic_rom.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
basic_rom.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
basic_rom.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
basic_rom.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
basic_rom.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
|
||||
Please see the core data sheet.
|
||||
|
||||
basic_rom_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
basic_rom_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
basic_rom_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
72
coregen/basic_rom_xmdf.tcl
Executable file
72
coregen/basic_rom_xmdf.tcl
Executable file
@@ -0,0 +1,72 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide basic_rom_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::basic_rom_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::basic_rom_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name basic_rom
|
||||
}
|
||||
# ::basic_rom_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::basic_rom_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module basic_rom
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
BIN
coregen/blk_mem_gen_ds512.pdf
Executable file
BIN
coregen/blk_mem_gen_ds512.pdf
Executable file
Binary file not shown.
2048
coregen/blk_mem_gen_v2_6.mif
Executable file
2048
coregen/blk_mem_gen_v2_6.mif
Executable file
File diff suppressed because it is too large
Load Diff
3
coregen/blk_mem_gen_v2_6.ngc
Executable file
3
coregen/blk_mem_gen_v2_6.ngc
Executable file
File diff suppressed because one or more lines are too long
118
coregen/blk_mem_gen_v2_6.vhd
Executable file
118
coregen/blk_mem_gen_v2_6.vhd
Executable file
@@ -0,0 +1,118 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating
|
||||
-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY blk_mem_gen_v2_6 IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END blk_mem_gen_v2_6;
|
||||
|
||||
ARCHITECTURE blk_mem_gen_v2_6_a OF blk_mem_gen_v2_6 IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_blk_mem_gen_v2_6
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_blk_mem_gen_v2_6 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "blk_mem_gen_v2_6.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_blk_mem_gen_v2_6
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END blk_mem_gen_v2_6_a;
|
||||
|
||||
56
coregen/blk_mem_gen_v2_6.vho
Executable file
56
coregen/blk_mem_gen_v2_6.vho
Executable file
@@ -0,0 +1,56 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component blk_mem_gen_v2_6
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : blk_mem_gen_v2_6
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating
|
||||
-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
78
coregen/blk_mem_gen_v2_6.xco
Executable file
78
coregen/blk_mem_gen_v2_6.xco
Executable file
@@ -0,0 +1,78 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Sat Jan 03 11:55:39 2009
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=blk_mem_gen_v2_6
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=8
|
||||
CSET read_width_b=8
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET single_bit_ecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_ramb16bwer_reset_behavior=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_ssra_pin=false
|
||||
CSET use_ssrb_pin=false
|
||||
CSET write_depth_a=2048
|
||||
CSET write_width_a=8
|
||||
CSET write_width_b=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 686b742a
|
||||
|
||||
24
coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
24
coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
@@ -0,0 +1,24 @@
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1.vhd"
|
||||
9
coregen/blk_mem_gen_v2_6_flist.txt
Executable file
9
coregen/blk_mem_gen_v2_6_flist.txt
Executable file
@@ -0,0 +1,9 @@
|
||||
# Output products list for <blk_mem_gen_v2_6>
|
||||
blk_mem_gen_v2_6.mif
|
||||
blk_mem_gen_v2_6.ngc
|
||||
blk_mem_gen_v2_6.vhd
|
||||
blk_mem_gen_v2_6.vho
|
||||
blk_mem_gen_v2_6.xco
|
||||
blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
blk_mem_gen_v2_6_flist.txt
|
||||
blk_mem_gen_v2_6_xmdf.tcl
|
||||
45
coregen/blk_mem_gen_v2_6_readme.txt
Executable file
45
coregen/blk_mem_gen_v2_6_readme.txt
Executable file
@@ -0,0 +1,45 @@
|
||||
The following files were generated for 'blk_mem_gen_v2_6' in directory
|
||||
C:\vhdl\nascom2_t80\coregen\:
|
||||
|
||||
blk_mem_gen_v2_6.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
blk_mem_gen_v2_6.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
blk_mem_gen_v2_6.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
blk_mem_gen_v2_6.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
blk_mem_gen_v2_6.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj:
|
||||
Please see the core data sheet.
|
||||
|
||||
blk_mem_gen_v2_6_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
blk_mem_gen_v2_6_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
blk_mem_gen_v2_6_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
72
coregen/blk_mem_gen_v2_6_xmdf.tcl
Executable file
72
coregen/blk_mem_gen_v2_6_xmdf.tcl
Executable file
@@ -0,0 +1,72 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide blk_mem_gen_v2_6_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::blk_mem_gen_v2_6_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::blk_mem_gen_v2_6_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v2_6
|
||||
}
|
||||
# ::blk_mem_gen_v2_6_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::blk_mem_gen_v2_6_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v2_6
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
2048
coregen/charrom.mif
Executable file
2048
coregen/charrom.mif
Executable file
File diff suppressed because it is too large
Load Diff
3
coregen/charrom.ngc
Executable file
3
coregen/charrom.ngc
Executable file
File diff suppressed because one or more lines are too long
118
coregen/charrom.vhd
Executable file
118
coregen/charrom.vhd
Executable file
@@ -0,0 +1,118 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file charrom.vhd when simulating
|
||||
-- the core, charrom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY charrom IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END charrom;
|
||||
|
||||
ARCHITECTURE charrom_a OF charrom IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_charrom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_charrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "charrom.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_charrom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END charrom_a;
|
||||
|
||||
56
coregen/charrom.vho
Executable file
56
coregen/charrom.vho
Executable file
@@ -0,0 +1,56 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component charrom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : charrom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file charrom.vhd when simulating
|
||||
-- the core, charrom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
78
coregen/charrom.xco
Executable file
78
coregen/charrom.xco
Executable file
@@ -0,0 +1,78 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Sat Jan 03 11:56:55 2009
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=charrom
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=8
|
||||
CSET read_width_b=8
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET single_bit_ecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_ramb16bwer_reset_behavior=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_ssra_pin=false
|
||||
CSET use_ssrb_pin=false
|
||||
CSET write_depth_a=2048
|
||||
CSET write_width_a=8
|
||||
CSET write_width_b=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 55453eb
|
||||
|
||||
24
coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
24
coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
@@ -0,0 +1,24 @@
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\charrom_blk_mem_gen_v2_6_xst_1.vhd"
|
||||
10
coregen/charrom_flist.txt
Executable file
10
coregen/charrom_flist.txt
Executable file
@@ -0,0 +1,10 @@
|
||||
# Output products list for <charrom>
|
||||
blk_mem_gen_v2_6.mif
|
||||
charrom.mif
|
||||
charrom.ngc
|
||||
charrom.vhd
|
||||
charrom.vho
|
||||
charrom.xco
|
||||
charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
charrom_flist.txt
|
||||
charrom_xmdf.tcl
|
||||
51
coregen/charrom_readme.txt
Executable file
51
coregen/charrom_readme.txt
Executable file
@@ -0,0 +1,51 @@
|
||||
The following files were generated for 'charrom' in directory
|
||||
C:\vhdl\nascom2_t80\coregen\:
|
||||
|
||||
blk_mem_gen_v2_6.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
charrom.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
charrom.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
charrom.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
charrom.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
charrom.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
|
||||
Please see the core data sheet.
|
||||
|
||||
charrom_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
charrom_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
charrom_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
76
coregen/charrom_xmdf.tcl
Executable file
76
coregen/charrom_xmdf.tcl
Executable file
@@ -0,0 +1,76 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide charrom_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::charrom_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::charrom_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name charrom
|
||||
}
|
||||
# ::charrom_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::charrom_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module charrom
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
20
coregen/coregen.cgp
Executable file
20
coregen/coregen.cgp
Executable file
@@ -0,0 +1,20 @@
|
||||
# Date: Wed Dec 31 13:09:41 2008
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
SET workingdirectory = c:\vhdl\nascom2\coregen\tmp
|
||||
|
||||
98
coregen/dcm_in50.vhd
Executable file
98
coregen/dcm_in50.vhd
Executable file
@@ -0,0 +1,98 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
|
||||
--------------------------------------------------------------------------------
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor: Xilinx
|
||||
-- \ \ \/ Version : 9.2.04i
|
||||
-- \ \ Application : xaw2vhdl
|
||||
-- / / Filename : dcm_in50.vhd
|
||||
-- /___/ /\ Timestamp : 01/03/2009 16:40:00
|
||||
-- \ \ / \
|
||||
-- \___\/\___\
|
||||
--
|
||||
--Command: xaw2vhdl-st C:\vhdl\nascom2_t80\coregen\\dcm_in50.xaw C:\vhdl\nascom2_t80\coregen\\dcm_in50
|
||||
--Design Name: dcm_in50
|
||||
--Device: xc3s700an-4fgg484
|
||||
--
|
||||
-- Module dcm_in50
|
||||
-- Generated by Xilinx Architecture Wizard
|
||||
-- Written for synthesis tool: XST
|
||||
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
|
||||
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.88 ns
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.ALL;
|
||||
use ieee.numeric_std.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.ALL;
|
||||
|
||||
entity dcm_in50 is
|
||||
port ( CLKIN_IN : in std_logic;
|
||||
RST_IN : in std_logic;
|
||||
CLKFX_OUT : out std_logic;
|
||||
CLKIN_IBUFG_OUT : out std_logic;
|
||||
CLK0_OUT : out std_logic;
|
||||
LOCKED_OUT : out std_logic);
|
||||
end dcm_in50;
|
||||
|
||||
architecture BEHAVIORAL of dcm_in50 is
|
||||
signal CLKFB_IN : std_logic;
|
||||
signal CLKFX_BUF : std_logic;
|
||||
signal CLKIN_IBUFG : std_logic;
|
||||
signal CLK0_BUF : std_logic;
|
||||
signal GND_BIT : std_logic;
|
||||
begin
|
||||
GND_BIT <= '0';
|
||||
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
|
||||
CLK0_OUT <= CLKFB_IN;
|
||||
CLKFX_BUFG_INST : BUFG
|
||||
port map (I=>CLKFX_BUF,
|
||||
O=>CLKFX_OUT);
|
||||
|
||||
CLKIN_IBUFG_INST : IBUFG
|
||||
port map (I=>CLKIN_IN,
|
||||
O=>CLKIN_IBUFG);
|
||||
|
||||
CLK0_BUFG_INST : BUFG
|
||||
port map (I=>CLK0_BUF,
|
||||
O=>CLKFB_IN);
|
||||
|
||||
DCM_SP_INST : DCM_SP
|
||||
generic map( CLK_FEEDBACK => "1X",
|
||||
CLKDV_DIVIDE => 2.0,
|
||||
CLKFX_DIVIDE => 25,
|
||||
CLKFX_MULTIPLY => 16,
|
||||
CLKIN_DIVIDE_BY_2 => TRUE,
|
||||
CLKIN_PERIOD => 40.000,
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => TRUE,
|
||||
FACTORY_JF => x"C080",
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => TRUE)
|
||||
port map (CLKFB=>CLKFB_IN,
|
||||
CLKIN=>CLKIN_IBUFG,
|
||||
DSSEN=>GND_BIT,
|
||||
PSCLK=>GND_BIT,
|
||||
PSEN=>GND_BIT,
|
||||
PSINCDEC=>GND_BIT,
|
||||
RST=>RST_IN,
|
||||
CLKDV=>open,
|
||||
CLKFX=>CLKFX_BUF,
|
||||
CLKFX180=>open,
|
||||
CLK0=>CLK0_BUF,
|
||||
CLK2X=>open,
|
||||
CLK2X180=>open,
|
||||
CLK90=>open,
|
||||
CLK180=>open,
|
||||
CLK270=>open,
|
||||
LOCKED=>LOCKED_OUT,
|
||||
PSDONE=>open,
|
||||
STATUS=>open);
|
||||
|
||||
end BEHAVIORAL;
|
||||
|
||||
|
||||
3
coregen/dcm_in50.xaw
Executable file
3
coregen/dcm_in50.xaw
Executable file
@@ -0,0 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.4e
|
||||
$9cx5>6339$;9<5>2:35<>71/aI;4=<41Y3861=5&1297?;>;54805(789809=949/0-41o03HXHDZGU169BVR\XGGFRSNO\C@FJJBYDDB;37L\XZ^MMH\YDDBCESHV[ESLBH43<I[]QSB@CY^AOOLHX^HF^I<l4ASUY[JHKQVNHAR]XIUAKMKAXKEA:<6O]W[]LJI_XLMXTO=??;@PT^ZIIDPUOH_QL1038EWQ]WFDGURJKR^AOO40<I[]QSB@CY^FGVZ@KAYLGC]?:;@PT^ZIIDPUMNRKWTDPMEI753HX\VRAALX]JJVRXF\Gn7L\XZ^MMH\YWEJN:96O]W[]LJI_XZLYNXRB@GHA2<>GU_SUDBAWPV@NJ@ZBA[VGDHHo4ARQLGZQN\Al0MZTPCMIAQCR^XL;::6OXZ^AOOGSA\PZN=R@@EEKW56=F_SUH@FQ@UURVPZR^XLi0MZTPFMMTP\VB02K\VR^NRUf8ER\X[PD_DYA@L59AKQN33K_MK?64C;^ulaj[fhyhc`<Pt92_gjtboldWhncPio73*}gp<2IGG=64CMI3[GSAm2IGG=QMUGE\MKUS02IGG=Q@UU48GIM609<0OAE=7178GIM5P11H@F<W1926?FJL19?0OAEKVb9@HNBQWMC]EIK:;BNHBG><KEAMNRGA5:AOOC^?3JF@JU?7089@HN@_WK_Mj6MCKGZ\FP@@W@DXXn5LLJD[[AOQAMOn7NBDFY]NQIRNXES27NBDFY]LQQ3<KEABB<?4CMIJJZBN^@NNSOWP2c9@HNOIW@H^JJ??;BNHMKYNJ\LLSD@\Tg9@HNOIW@H^JJQ@UU:8GIMNFVCEo6MCKHL\T@TNGMo0OAEFN^QQGZR^XL;97NBDOTV\TMGTMVYCEKZl;BNH[CCBLKKHG45LOLOJPQCC?2IYILZJD79GGHYTXk1OO@Q\P^KMWQb<LLY@IZQNDKWPP44<LOYTJ_K^UDL@]ZKHLLk0HABPAOF\B]753MFGSK\JQTGMG\YJGMO>7I]\EO36?ASSQVIROAKPCNPQAFRNGG=0HRXNLTG;?@^SM[DJ@l5IABVLV\YMN<1MMA]J9:DA[VIRZJOh7KKJDCC@OZDRN01MECQZNHVP<>@H]]UXX_o4FNWW[PHN\Zk0JB[[_WCOQ@7<A<1BNXHH8:KMP@TIIE;:7GG[TDP\MKVR\V^R\Hm4JHVWAWYWC;Z@o6DFTUGQ[SGK]L<0@BOKEE48HJELMMk0@BMDEE]LQQ5<DF]87@FU7:O\RDJRM>1EIYY@RJ68JJHB92E37BHKDSASAg=W@HYNS^FFFU;8TLHOIZH^_l5_IOKPCKBBL11[ECYFDUJ;?UTNE]S[I<>4PSMS[UOIAZKHXDXJ5:RPGIM13YYOCCK;;QQFJ==W[@DHHHM<;SQW2>TT\VCEn6]FGDZWAWHFD?1XECICEb9PPDTS]YU\MDZ9;RVBPPU6:2YR_YKB_R[MGMTHFF_X?6Z@P59WVPC?3\YNSO[IG89VW@YE]OMX96XFEV3a?]GPW_OY_DAA1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF3:ZPP3=_lkUBh<>4Xeo\Idlhz_oydaa119[`hYJageyZh||inl6?^6=8T?0W=48]59bvr|43mifn6xjrrklj%7)8=1}dib>1:z`7v178hd&8kih496~DEv4j2JKt?:5F;695~U3<32>6595120;gc1=:=l8<v`71;38j=4=<2.3<79j;|Q77?>221=1=><7cg59607682Y>h76::959564?ko=1>87:6:Q77?>221=1=><7cg5960?1?2n397>51;3xW12=0<03;7?<29ae3?43n::0zY9l:182>4<fsZ>?65;5868277>dn>098k=?;c5;>5<72=0jw)j5879'5c<?02.9<766;%02>2`<,>n1o6l;6;2956<729q/:o4;5:&f>7c<,o0<86*>1;06?!752;?0(<=5289'51<5=2.:9789;%35>22<,8=1>6*>8;47?!7>2<:0(<o5239'07<23-8m6;5+378;?!502:1/?l489:&0b?g<,=:18h5+40850>"3?3=<7):k:39'0=<182.?m78?;%6`>2?<,=l186*:1;7:?!342?;0(8;5609'13<43-?j68:4$709=>"1?3:0(:;5789'3d<0j2.:<7l4$0g90<=#=j0:7);m:69j7<<72-<j65=4$7a93<=<a::1<7*9a;:0?!0d2>307d9>:18'2d<?;2.=o796;:k5b?6=,?k14>5+6884=>=n?90;6)8n:918 3?=?010e;j50;&5e?>43-<26:74;h6a>5<#>h03?6*99;5:?>i5=3:1(;o5829'2f<012.:o7<<;%3g>04<3f8o6=4+6`8;7>=h:00;6)8n:918?j4f290/:l473:9l6`<72-<j65=4$0a966=<g;h1<7*9a;:0?>i5k3:1(;o58298k64=83.=m76<;%4`>2?<,8i1>>54o2194?"1i32876a86;29 3g=0=1/:5489:9l1`<72-<j65=4$7a93<=<g?o1<7*9a;:0?>{e;j0;6?4?:1y'2g<202c>;7>5$7c9<6=#>j0<565`6483>!0f2190(;m57898yg4029096=4?{%4a>75<a<=1<7*9a;:0?!0d2>307b8::18'2d<?;2.=o796;:a70<72;0;6=u+6c817>o2?3:1(;o5829'2f<0121d:84?:%4b>=5<,?i1;454}r1a>5<5s4>=6>74=2a920=#9k08h6s|3083>7}:<?08<63=7;46?!7e2;20q~9=:1828212>;0(:=5569~w70=838p1985249>62<2?2wx?94?:3y>03<4:27897;8;|q6b?6=9r7?:7;j;%50>33<uz9n6=4>{<1`>01<,>919:5rs2:94?7|5:?1:85+72851>{t;m0;6=u+72851>{t:10;6=u+72851>{zf;=1<7?t}o0;>5<6std957>51zm6d<728qvb?l50;3xyk4d290:wp`=d;295~{i:l0;6<urn3d94?7|ug9;6=4>{|~yEFDs:h1>;<k0926yEFEs9wKL]ur@A
|
||||
17
coregen/dcm_in50_arwz.ucf
Executable file
17
coregen/dcm_in50_arwz.ucf
Executable file
@@ -0,0 +1,17 @@
|
||||
# Generated by Xilinx Architecture Wizard
|
||||
# --- UCF Template Only ---
|
||||
# Cut and paste these attributes into the project's UCF file, if desired
|
||||
INST DCM_SP_INST CLK_FEEDBACK = 1X;
|
||||
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
|
||||
INST DCM_SP_INST CLKFX_DIVIDE = 25;
|
||||
INST DCM_SP_INST CLKFX_MULTIPLY = 16;
|
||||
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = TRUE;
|
||||
INST DCM_SP_INST CLKIN_PERIOD = 40.000;
|
||||
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
|
||||
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
|
||||
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
|
||||
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
|
||||
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
|
||||
INST DCM_SP_INST FACTORY_JF = C080;
|
||||
INST DCM_SP_INST PHASE_SHIFT = 0;
|
||||
INST DCM_SP_INST STARTUP_WAIT = TRUE;
|
||||
BIN
coregen/dist_mem_gen_ds322.pdf
Executable file
BIN
coregen/dist_mem_gen_ds322.pdf
Executable file
Binary file not shown.
99
coregen/dist_mem_gen_release_notes.txt
Executable file
99
coregen/dist_mem_gen_release_notes.txt
Executable file
@@ -0,0 +1,99 @@
|
||||
COPYRIGHT (c) 2007 XILINX, INC.
|
||||
ALL RIGHTS RESERVED
|
||||
|
||||
Core name : Distributed Memory Generator
|
||||
Version : v3.3
|
||||
Release Date : April 2, 2007
|
||||
File : distributed_memory_generator_release_notes.txt
|
||||
|
||||
Revision History
|
||||
Date By Version Change Description
|
||||
========================================================================
|
||||
4/2007 Xilinx, Inc. 3.3 Initial creation.
|
||||
========================================================================
|
||||
|
||||
INTRODUCTION
|
||||
RELEASE NOTES
|
||||
1. General Core Design
|
||||
1.1 Enhancements
|
||||
1.2 Resolved Issues
|
||||
1.3 Outstanding Issues
|
||||
2. General Simulation
|
||||
2.1 Enhancements
|
||||
2.2 Resolved Issues
|
||||
2.3 Outstanding Issues
|
||||
3. Documentation
|
||||
3.1 Enhancements
|
||||
3.2 Resolved Issues
|
||||
3.3 Outstanding Issues
|
||||
OTHER GENERAL INFORMATION
|
||||
TECHNICAL SUPPORT
|
||||
|
||||
========================================================================
|
||||
|
||||
INTRODUCTION
|
||||
============
|
||||
Thank you using the Distributed Memory Generator core from Xilinx!
|
||||
In order to obtain the latest core updates and documentation,
|
||||
please visit the Intellectual Property page located at:
|
||||
http://www.xilinx.com/ipcenter/index.htm
|
||||
This document contains the release notes for Distributed Memory Generator v3.3
|
||||
which includes enhancements, resolved issues and outstanding known
|
||||
issues. For release notes and known issues for CORE Generator 9.1i
|
||||
IP Update and Distributed Memory Generator v3.3 please see Answer Record 24307.
|
||||
|
||||
RELEASE NOTES
|
||||
=============
|
||||
This section lists any enhancements, resolved issues and outstanding
|
||||
known issues.
|
||||
|
||||
|
||||
1. General Core Design
|
||||
1.1 Enhancements
|
||||
1.1.1 Support for Spartan(TM) - 3A DSP
|
||||
time.
|
||||
|
||||
1.2 Resolved Issues
|
||||
1.2.1 Solved excessive register duplication in distributed memory synthesis.
|
||||
Change request: 326740
|
||||
|
||||
1.3 Outstanding Issues
|
||||
1.3.1 When a large Distributed Memory Generator IP is generated, CORE ,
|
||||
Generator runs out of memory and fails to generate.
|
||||
Change request: 431917
|
||||
|
||||
2. General Simulation
|
||||
2.1 Enhancements
|
||||
None at this time.
|
||||
|
||||
2.2 Resolved Issues
|
||||
None at this time.
|
||||
|
||||
2.3 Outstanding Issues
|
||||
None at this time.
|
||||
|
||||
3. Documentation
|
||||
3.1 Enhancements
|
||||
None at this time.
|
||||
|
||||
3.2 Resolved Issues
|
||||
None at this time.
|
||||
|
||||
3.3 Outstanding Issues
|
||||
None at this time.
|
||||
|
||||
|
||||
TECHNICAL SUPPORT
|
||||
=================
|
||||
The fastest method for obtaining specific technical support for the
|
||||
Distributed Memory Generator core is through the http://support.xilinx.com/
|
||||
website. Questions are routed to a team of engineers with specific
|
||||
expertise in using the Distributed Memory Generator core. Xilinx will provide
|
||||
technical support for use of this product as described in the Distributed
|
||||
Memory Generator Datasheet. Xilinx cannot guarantee timing,
|
||||
functionality, or support of this product for designs that do not
|
||||
follow these guidelines.
|
||||
|
||||
|
||||
|
||||
|
||||
3
coregen/distram16x8.ngc
Executable file
3
coregen/distram16x8.ngc
Executable file
File diff suppressed because one or more lines are too long
115
coregen/distram16x8.vhd
Executable file
115
coregen/distram16x8.vhd
Executable file
@@ -0,0 +1,115 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file distram16x8.vhd when simulating
|
||||
-- the core, distram16x8. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY distram16x8 IS
|
||||
port (
|
||||
a: IN std_logic_VECTOR(3 downto 0);
|
||||
d: IN std_logic_VECTOR(7 downto 0);
|
||||
dpra: IN std_logic_VECTOR(3 downto 0);
|
||||
clk: IN std_logic;
|
||||
we: IN std_logic;
|
||||
spo: OUT std_logic_VECTOR(7 downto 0);
|
||||
dpo: OUT std_logic_VECTOR(7 downto 0));
|
||||
END distram16x8;
|
||||
|
||||
ARCHITECTURE distram16x8_a OF distram16x8 IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_distram16x8
|
||||
port (
|
||||
a: IN std_logic_VECTOR(3 downto 0);
|
||||
d: IN std_logic_VECTOR(7 downto 0);
|
||||
dpra: IN std_logic_VECTOR(3 downto 0);
|
||||
clk: IN std_logic;
|
||||
we: IN std_logic;
|
||||
spo: OUT std_logic_VECTOR(7 downto 0);
|
||||
dpo: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_distram16x8 use entity XilinxCoreLib.dist_mem_gen_v3_3(behavioral)
|
||||
generic map(
|
||||
c_has_clk => 1,
|
||||
c_has_qdpo_clk => 0,
|
||||
c_has_qdpo_ce => 0,
|
||||
c_has_d => 1,
|
||||
c_has_spo => 1,
|
||||
c_read_mif => 0,
|
||||
c_has_qspo => 0,
|
||||
c_width => 8,
|
||||
c_reg_a_d_inputs => 0,
|
||||
c_has_we => 1,
|
||||
c_pipeline_stages => 0,
|
||||
c_has_qdpo_rst => 0,
|
||||
c_reg_dpra_input => 0,
|
||||
c_qualify_we => 0,
|
||||
c_sync_enable => 1,
|
||||
c_depth => 16,
|
||||
c_has_qspo_srst => 0,
|
||||
c_has_qdpo_srst => 0,
|
||||
c_has_dpra => 1,
|
||||
c_qce_joined => 0,
|
||||
c_mem_type => 2,
|
||||
c_has_i_ce => 0,
|
||||
c_has_dpo => 1,
|
||||
c_mem_init_file => "no_coe_file_loaded",
|
||||
c_default_data => "0",
|
||||
c_has_spra => 0,
|
||||
c_has_qspo_ce => 0,
|
||||
c_addr_width => 4,
|
||||
c_has_qdpo => 0,
|
||||
c_has_qspo_rst => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_distram16x8
|
||||
port map (
|
||||
a => a,
|
||||
d => d,
|
||||
dpra => dpra,
|
||||
clk => clk,
|
||||
we => we,
|
||||
spo => spo,
|
||||
dpo => dpo);
|
||||
-- synthesis translate_on
|
||||
|
||||
END distram16x8_a;
|
||||
|
||||
64
coregen/distram16x8.vho
Executable file
64
coregen/distram16x8.vho
Executable file
@@ -0,0 +1,64 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component distram16x8
|
||||
port (
|
||||
a: IN std_logic_VECTOR(3 downto 0);
|
||||
d: IN std_logic_VECTOR(7 downto 0);
|
||||
dpra: IN std_logic_VECTOR(3 downto 0);
|
||||
clk: IN std_logic;
|
||||
we: IN std_logic;
|
||||
spo: OUT std_logic_VECTOR(7 downto 0);
|
||||
dpo: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : distram16x8
|
||||
port map (
|
||||
a => a,
|
||||
d => d,
|
||||
dpra => dpra,
|
||||
clk => clk,
|
||||
we => we,
|
||||
spo => spo,
|
||||
dpo => dpo);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file distram16x8.vhd when simulating
|
||||
-- the core, distram16x8. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
63
coregen/distram16x8.xco
Executable file
63
coregen/distram16x8.xco
Executable file
@@ -0,0 +1,63 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Wed Dec 31 13:10:21 2008
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET ce_overrides=ce_overrides_sync_controls
|
||||
CSET coefficient_file=no_coe_file_loaded
|
||||
CSET common_output_ce=false
|
||||
CSET common_output_clk=false
|
||||
CSET component_name=distram16x8
|
||||
CSET data_width=8
|
||||
CSET default_data=0
|
||||
CSET default_data_radix=16
|
||||
CSET depth=16
|
||||
CSET dual_port_address=non_registered
|
||||
CSET dual_port_output_clock_enable=false
|
||||
CSET input_clock_enable=false
|
||||
CSET input_options=non_registered
|
||||
CSET memory_type=dual_port_ram
|
||||
CSET output_options=non_registered
|
||||
CSET pipeline_stages=0
|
||||
CSET qualify_we_with_i_ce=false
|
||||
CSET reset_qdpo=false
|
||||
CSET reset_qspo=false
|
||||
CSET single_port_output_clock_enable=false
|
||||
CSET sync_reset_qdpo=false
|
||||
CSET sync_reset_qspo=false
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 79e446fd
|
||||
|
||||
7
coregen/distram16x8_flist.txt
Executable file
7
coregen/distram16x8_flist.txt
Executable file
@@ -0,0 +1,7 @@
|
||||
# Output products list for <distram16x8>
|
||||
distram16x8.ngc
|
||||
distram16x8.vhd
|
||||
distram16x8.vho
|
||||
distram16x8.xco
|
||||
distram16x8_flist.txt
|
||||
distram16x8_xmdf.tcl
|
||||
36
coregen/distram16x8_readme.txt
Executable file
36
coregen/distram16x8_readme.txt
Executable file
@@ -0,0 +1,36 @@
|
||||
The following files were generated for 'distram16x8' in directory
|
||||
c:\vhdl\nascom2\coregen\:
|
||||
|
||||
distram16x8.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
distram16x8.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
distram16x8.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
distram16x8.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
distram16x8_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
distram16x8_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
distram16x8_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
64
coregen/distram16x8_xmdf.tcl
Executable file
64
coregen/distram16x8_xmdf.tcl
Executable file
@@ -0,0 +1,64 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide distram16x8_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::distram16x8_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::distram16x8_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name distram16x8
|
||||
}
|
||||
# ::distram16x8_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::distram16x8_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module distram16x8
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
17
coregen/monitorrom.asy
Executable file
17
coregen/monitorrom.asy
Executable file
@@ -0,0 +1,17 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 monitorrom
|
||||
RECTANGLE Normal 32 32 544 576
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName addra[10:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName clka
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName douta[7:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
2048
coregen/monitorrom.mif
Executable file
2048
coregen/monitorrom.mif
Executable file
File diff suppressed because it is too large
Load Diff
3
coregen/monitorrom.ngc
Executable file
3
coregen/monitorrom.ngc
Executable file
File diff suppressed because one or more lines are too long
27
coregen/monitorrom.sym
Executable file
27
coregen/monitorrom.sym
Executable file
@@ -0,0 +1,27 @@
|
||||
VERSION 5
|
||||
BEGIN SYMBOL monitorrom
|
||||
SYMBOLTYPE BLOCK
|
||||
TIMESTAMP 2008 12 31 13 31 1
|
||||
SYMPIN 0 80 Input addra[10:0]
|
||||
SYMPIN 0 272 Input clka
|
||||
SYMPIN 576 80 Output douta[7:0]
|
||||
BEGIN DISPLAY 32 32 TEXT monitorrom
|
||||
FONT 40 "Arial"
|
||||
END DISPLAY
|
||||
RECTANGLE N 32 32 544 576
|
||||
BEGIN LINE W 0 80 32 80
|
||||
END LINE
|
||||
BEGIN DISPLAY 36 80 PIN addra[10:0] ATTR PinName
|
||||
FONT 24 "Arial"
|
||||
END DISPLAY
|
||||
LINE N 0 272 32 272
|
||||
BEGIN DISPLAY 36 272 PIN clka ATTR PinName
|
||||
FONT 24 "Arial"
|
||||
END DISPLAY
|
||||
BEGIN LINE W 576 80 544 80
|
||||
END LINE
|
||||
BEGIN DISPLAY 540 80 PIN douta[7:0] ATTR PinName
|
||||
ALIGNMENT RIGHT
|
||||
FONT 24 "Arial"
|
||||
END DISPLAY
|
||||
END SYMBOL
|
||||
126
coregen/monitorrom.v
Executable file
126
coregen/monitorrom.v
Executable file
@@ -0,0 +1,126 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2007 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The synthesis directives "translate_off/translate_on" specified below are
|
||||
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
||||
// tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
// You must compile the wrapper file monitorrom.v when simulating
|
||||
// the core, monitorrom. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module monitorrom(
|
||||
clka,
|
||||
addra,
|
||||
douta);
|
||||
|
||||
|
||||
input clka;
|
||||
input [10 : 0] addra;
|
||||
output [7 : 0] douta;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
BLK_MEM_GEN_V2_6 #(
|
||||
.C_ADDRA_WIDTH(11),
|
||||
.C_ADDRB_WIDTH(11),
|
||||
.C_ALGORITHM(1),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_FAMILY("spartan3"),
|
||||
.C_HAS_ENA(0),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_HAS_SSRA(0),
|
||||
.C_HAS_SSRB(0),
|
||||
.C_INIT_FILE_NAME("monitorrom.mif"),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_READ_DEPTH_A(2048),
|
||||
.C_READ_DEPTH_B(2048),
|
||||
.C_READ_WIDTH_A(8),
|
||||
.C_READ_WIDTH_B(8),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_SINITA_VAL("0"),
|
||||
.C_SINITB_VAL("0"),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_USE_DEFAULT_DATA(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_RAMB16BWER_RST_BHV(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_DEPTH_A(2048),
|
||||
.C_WRITE_DEPTH_B(2048),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(8),
|
||||
.C_WRITE_WIDTH_B(8),
|
||||
.C_XDEVICEFAMILY("spartan3a"))
|
||||
inst (
|
||||
.CLKA(clka),
|
||||
.ADDRA(addra),
|
||||
.DOUTA(douta),
|
||||
.DINA(),
|
||||
.ENA(),
|
||||
.REGCEA(),
|
||||
.WEA(),
|
||||
.SSRA(),
|
||||
.CLKB(),
|
||||
.DINB(),
|
||||
.ADDRB(),
|
||||
.ENB(),
|
||||
.REGCEB(),
|
||||
.WEB(),
|
||||
.SSRB(),
|
||||
.DOUTB(),
|
||||
.DBITERR(),
|
||||
.SBITERR());
|
||||
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
// XST black box declaration
|
||||
// box_type "black_box"
|
||||
// synthesis attribute box_type of monitorrom is "black_box"
|
||||
|
||||
endmodule
|
||||
|
||||
45
coregen/monitorrom.veo
Executable file
45
coregen/monitorrom.veo
Executable file
@@ -0,0 +1,45 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2007 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
monitorrom YourInstanceName (
|
||||
.clka(clka),
|
||||
.addra(addra), // Bus [10 : 0]
|
||||
.douta(douta)); // Bus [7 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file monitorrom.v when simulating
|
||||
// the core, monitorrom. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
121
coregen/monitorrom.vhd
Executable file
121
coregen/monitorrom.vhd
Executable file
@@ -0,0 +1,121 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file monitorrom.vhd when simulating
|
||||
-- the core, monitorrom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY monitorrom IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END monitorrom;
|
||||
|
||||
ARCHITECTURE monitorrom_a OF monitorrom IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_monitorrom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "monitorrom.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 1,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 1);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_monitorrom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END monitorrom_a;
|
||||
|
||||
118
coregen/monitorrom.vhd.bak
Executable file
118
coregen/monitorrom.vhd.bak
Executable file
@@ -0,0 +1,118 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file monitorrom.vhd when simulating
|
||||
-- the core, monitorrom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY monitorrom IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END monitorrom;
|
||||
|
||||
ARCHITECTURE monitorrom_a OF monitorrom IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_monitorrom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "monitorrom.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 1);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_monitorrom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END monitorrom_a;
|
||||
|
||||
58
coregen/monitorrom.vho
Executable file
58
coregen/monitorrom.vho
Executable file
@@ -0,0 +1,58 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component monitorrom
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : monitorrom
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file monitorrom.vhd when simulating
|
||||
-- the core, monitorrom. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
78
coregen/monitorrom.xco
Executable file
78
coregen/monitorrom.xco
Executable file
@@ -0,0 +1,78 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Thu Jan 08 11:30:25 2009
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=C:/vhdl/nascom2_t80/NASSYSI.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=monitorrom
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET enable_a=Use_ENA_Pin
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET fill_remaining_memory_locations=true
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=8
|
||||
CSET read_width_b=8
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET single_bit_ecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_ramb16bwer_reset_behavior=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_ssra_pin=false
|
||||
CSET use_ssrb_pin=false
|
||||
CSET write_depth_a=2048
|
||||
CSET write_width_a=8
|
||||
CSET write_width_b=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: b5ba28bc
|
||||
|
||||
24
coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
24
coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
@@ -0,0 +1,24 @@
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\monitorrom_blk_mem_gen_v2_6_xst_1.vhd"
|
||||
9
coregen/monitorrom_flist.txt
Executable file
9
coregen/monitorrom_flist.txt
Executable file
@@ -0,0 +1,9 @@
|
||||
# Output products list for <monitorrom>
|
||||
monitorrom.mif
|
||||
monitorrom.ngc
|
||||
monitorrom.vhd
|
||||
monitorrom.vho
|
||||
monitorrom.xco
|
||||
monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
monitorrom_flist.txt
|
||||
monitorrom_xmdf.tcl
|
||||
45
coregen/monitorrom_readme.txt
Executable file
45
coregen/monitorrom_readme.txt
Executable file
@@ -0,0 +1,45 @@
|
||||
The following files were generated for 'monitorrom' in directory
|
||||
C:\vhdl\nascom2_t80\coregen\:
|
||||
|
||||
monitorrom.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
monitorrom.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
monitorrom.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
monitorrom.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
monitorrom.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
|
||||
Please see the core data sheet.
|
||||
|
||||
monitorrom_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
monitorrom_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
monitorrom_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
72
coregen/monitorrom_xmdf.tcl
Executable file
72
coregen/monitorrom_xmdf.tcl
Executable file
@@ -0,0 +1,72 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide monitorrom_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::monitorrom_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::monitorrom_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name monitorrom
|
||||
}
|
||||
# ::monitorrom_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::monitorrom_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module monitorrom
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
3
coregen/ram2kx8.ngc
Executable file
3
coregen/ram2kx8.ngc
Executable file
File diff suppressed because one or more lines are too long
142
coregen/ram2kx8.vhd
Executable file
142
coregen/ram2kx8.vhd
Executable file
@@ -0,0 +1,142 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file ram2kx8.vhd when simulating
|
||||
-- the core, ram2kx8. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY ram2kx8 IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
dina: IN std_logic_VECTOR(7 downto 0);
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
wea: IN std_logic_VECTOR(0 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0);
|
||||
clkb: IN std_logic;
|
||||
dinb: IN std_logic_VECTOR(7 downto 0);
|
||||
addrb: IN std_logic_VECTOR(10 downto 0);
|
||||
web: IN std_logic_VECTOR(0 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(7 downto 0));
|
||||
END ram2kx8;
|
||||
|
||||
ARCHITECTURE ram2kx8_a OF ram2kx8 IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_ram2kx8
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
dina: IN std_logic_VECTOR(7 downto 0);
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
wea: IN std_logic_VECTOR(0 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0);
|
||||
clkb: IN std_logic;
|
||||
dinb: IN std_logic_VECTOR(7 downto 0);
|
||||
addrb: IN std_logic_VECTOR(10 downto 0);
|
||||
web: IN std_logic_VECTOR(0 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_ram2kx8 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 2,
|
||||
c_prim_type => 1,
|
||||
c_sinita_val => "0",
|
||||
c_read_width_b => 8,
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 8,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_write_mode_b => "READ_FIRST",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_write_mode_a => "READ_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_load_init_file => 0,
|
||||
c_xdevicefamily => "spartan3a",
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_ssrb => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_ssra => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 8,
|
||||
c_write_width_a => 8,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_ramb16bwer_rst_bhv => 0,
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 1,
|
||||
c_sinitb_val => "0",
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_default_data => 1);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_ram2kx8
|
||||
port map (
|
||||
clka => clka,
|
||||
dina => dina,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
wea => wea,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
dinb => dinb,
|
||||
addrb => addrb,
|
||||
web => web,
|
||||
doutb => doutb);
|
||||
-- synthesis translate_on
|
||||
|
||||
END ram2kx8_a;
|
||||
|
||||
72
coregen/ram2kx8.vho
Executable file
72
coregen/ram2kx8.vho
Executable file
@@ -0,0 +1,72 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2007 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component ram2kx8
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
dina: IN std_logic_VECTOR(7 downto 0);
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
ena: IN std_logic;
|
||||
wea: IN std_logic_VECTOR(0 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0);
|
||||
clkb: IN std_logic;
|
||||
dinb: IN std_logic_VECTOR(7 downto 0);
|
||||
addrb: IN std_logic_VECTOR(10 downto 0);
|
||||
web: IN std_logic_VECTOR(0 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(7 downto 0));
|
||||
end component;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : ram2kx8
|
||||
port map (
|
||||
clka => clka,
|
||||
dina => dina,
|
||||
addra => addra,
|
||||
ena => ena,
|
||||
wea => wea,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
dinb => dinb,
|
||||
addrb => addrb,
|
||||
web => web,
|
||||
doutb => doutb);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file ram2kx8.vhd when simulating
|
||||
-- the core, ram2kx8. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
78
coregen/ram2kx8.xco
Executable file
78
coregen/ram2kx8.xco
Executable file
@@ -0,0 +1,78 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version J.40
|
||||
# Date: Sat Jan 03 15:42:53 2009
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s700an
|
||||
SET devicefamily = spartan3a
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = False
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=no_coe_file_loaded
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=ram2kx8
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET enable_a=Use_ENA_Pin
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET fill_remaining_memory_locations=true
|
||||
CSET load_init_file=false
|
||||
CSET memory_type=True_Dual_Port_RAM
|
||||
CSET operating_mode_a=READ_FIRST
|
||||
CSET operating_mode_b=READ_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=8
|
||||
CSET read_width_b=8
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET single_bit_ecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_ramb16bwer_reset_behavior=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_ssra_pin=false
|
||||
CSET use_ssrb_pin=false
|
||||
CSET write_depth_a=2048
|
||||
CSET write_width_a=8
|
||||
CSET write_width_b=8
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: bde5567c
|
||||
|
||||
24
coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
24
coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
Executable file
@@ -0,0 +1,24 @@
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
|
||||
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\ram2kx8_blk_mem_gen_v2_6_xst_1.vhd"
|
||||
8
coregen/ram2kx8_flist.txt
Executable file
8
coregen/ram2kx8_flist.txt
Executable file
@@ -0,0 +1,8 @@
|
||||
# Output products list for <ram2kx8>
|
||||
ram2kx8.ngc
|
||||
ram2kx8.vhd
|
||||
ram2kx8.vho
|
||||
ram2kx8.xco
|
||||
ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
ram2kx8_flist.txt
|
||||
ram2kx8_xmdf.tcl
|
||||
39
coregen/ram2kx8_readme.txt
Executable file
39
coregen/ram2kx8_readme.txt
Executable file
@@ -0,0 +1,39 @@
|
||||
The following files were generated for 'ram2kx8' in directory
|
||||
C:\vhdl\nascom2_t80\coregen\:
|
||||
|
||||
ram2kx8.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
ram2kx8.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
ram2kx8.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
ram2kx8.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj:
|
||||
Please see the core data sheet.
|
||||
|
||||
ram2kx8_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
ram2kx8_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
ram2kx8_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
68
coregen/ram2kx8_xmdf.tcl
Executable file
68
coregen/ram2kx8_xmdf.tcl
Executable file
@@ -0,0 +1,68 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide ram2kx8_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::ram2kx8_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::ram2kx8_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name ram2kx8
|
||||
}
|
||||
# ::ram2kx8_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::ram2kx8_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram2kx8
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
49
dcm_in50_sim.vhd
Executable file
49
dcm_in50_sim.vhd
Executable file
@@ -0,0 +1,49 @@
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
entity dcm_in50 is
|
||||
|
||||
port (
|
||||
CLKIN_IN : in std_logic;
|
||||
RST_IN : in std_logic;
|
||||
CLKFX_OUT : out std_logic;
|
||||
CLKIN_IBUFG_OUT : out std_logic;
|
||||
CLK0_OUT : out std_logic;
|
||||
LOCKED_OUT : out std_logic);
|
||||
|
||||
end dcm_in50;
|
||||
|
||||
architecture Behavioral of dcm_in50 is
|
||||
|
||||
begin -- Behavioral
|
||||
|
||||
LOCKED_OUT <= '1';
|
||||
CLKIN_IBUFG_OUT <= CLKIN_IN;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until CLKIN_IN = '1';
|
||||
while true loop
|
||||
CLK0_OUT <= '1';
|
||||
wait for 20 ns;
|
||||
CLK0_OUT <= '0';
|
||||
wait for 20 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until CLKIN_IN = '1';
|
||||
while true loop
|
||||
CLKFX_OUT <= '1';
|
||||
wait for 31.25 ns;
|
||||
CLKFX_OUT <= '0';
|
||||
wait for 31.25 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
72
fifo16x8.vhd
Executable file
72
fifo16x8.vhd
Executable file
@@ -0,0 +1,72 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 14:10:50 12/28/2008
|
||||
-- Design Name:
|
||||
-- Module Name: fifo16x8 - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity fifo16x8 is
|
||||
Port ( DATAIN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
WRITESTB : in STD_LOGIC;
|
||||
DATAOUT : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
READSTB : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
FULL : out STD_LOGIC;
|
||||
EMPTY : out STD_LOGIC);
|
||||
end fifo16x8;
|
||||
|
||||
architecture Behavioral of fifo16x8 is
|
||||
signal counter: std_logic_vector(3 downto 0) := "1111";
|
||||
begin
|
||||
|
||||
shift: for i in 0 to 7 generate
|
||||
srl16e_inst: SRL16E port map(
|
||||
Q => DATAOUT(i),
|
||||
A0 => counter(0),
|
||||
A1 => counter(1),
|
||||
A2 => counter(2),
|
||||
A3 => counter(3),
|
||||
CE => WRITESTB,
|
||||
CLK => CLK,
|
||||
D => DATAIN(i));
|
||||
end generate;
|
||||
|
||||
fifo: process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if (WRITESTB = '0') and (READSTB = '1') then
|
||||
counter <= counter - 1;
|
||||
elsif (WRITESTB = '1') and (READSTB = '0') then
|
||||
counter <= counter + 1;
|
||||
else
|
||||
counter <= counter;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
FULL <= '1' when counter = "1110" else '0';
|
||||
EMPTY <= '1' when counter = "1111" else '0';
|
||||
end Behavioral;
|
||||
|
||||
1901
kcpsm3.vhd
Executable file
1901
kcpsm3.vhd
Executable file
File diff suppressed because it is too large
Load Diff
206
keyboard.vhd
Executable file
206
keyboard.vhd
Executable file
@@ -0,0 +1,206 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:52:22 12/30/2008
|
||||
-- Design Name:
|
||||
-- Module Name: toplevel - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity keyboard is
|
||||
|
||||
port (
|
||||
-- PS/2 Interface
|
||||
PS2_CLK : inout std_logic;
|
||||
PS2_DATA : inout std_logic;
|
||||
-- Z80 interface
|
||||
CLK_16M : in std_logic;
|
||||
IORQ_n : in std_logic;
|
||||
RD_n, WR_n : in std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
-- DEBUG
|
||||
DEBUG : out std_logic_vector(7 downto 0)
|
||||
-- DEBUGLED : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
|
||||
end keyboard;
|
||||
|
||||
architecture Behavioral of keyboard is
|
||||
type states is (ST_RESET, ST_IDLE, ST_READ, ST_PARITY, ST_ERROR, ST_STOP);
|
||||
signal state : states := ST_RESET;
|
||||
signal parity_r, up_r, ext_r : std_logic := '0';
|
||||
signal key_in_r : std_logic_vector(7 downto 0);
|
||||
signal count : unsigned(2 downto 0);
|
||||
type line_lut_t is array (0 to 255) of integer range 0 to 9;
|
||||
type bit_lut_t is array (0 to 255) of integer range 0 to 7;
|
||||
signal line_lut : line_lut_t;
|
||||
signal bit_lut : bit_lut_t;
|
||||
|
||||
signal ps2clk_s, ps2data_s : std_logic_vector(2 downto 0) := "111";
|
||||
signal debug_evt_counter : std_logic_vector(7 downto 0) := X"00";
|
||||
|
||||
type key_buffer_t is array (0 to 9) of std_logic_vector(7 downto 0);
|
||||
signal key_buffer : key_buffer_t;
|
||||
signal keyb_row_r : unsigned(3 downto 0) := to_unsigned(0, 4);
|
||||
signal lastin_r : std_logic_vector(1 downto 0) := "00";
|
||||
begin -- Behavioral
|
||||
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
|
||||
line_lut <= (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, -- 0_
|
||||
0, 0, 0, 0, 0, 5, 6, 0, 0, 0, 2, 3, 4, 4, 6, 0, -- 1_
|
||||
0, 7, 1, 2, 3, 7, 5, 0, 0, 7, 7, 1, 1, 7, 1, 0, -- 2_
|
||||
0, 2, 1, 1, 7, 2, 2, 0, 0, 0, 3, 2, 3, 3, 4, 0, -- 3_
|
||||
|
||||
0, 4, 3, 4, 5, 6, 5, 0, 0, 5, 6, 4, 5, 6, 8, 0, -- 4_
|
||||
0, 0, 6, 0, 6, 0, 0, 0, 0, 0, 8, 7, 0, 5, 0, 0, -- 5_
|
||||
0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 6_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 7_
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 0_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 1_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 2_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 3_
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 4_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 5_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, -- e0 6_
|
||||
0, 0, 3, 0, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- e0 7_
|
||||
|
||||
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
|
||||
bit_lut <= (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, -- 0_
|
||||
0, 0, 4, 0, 0, 4, 4, 0, 0, 0, 5, 4, 4, 3, 3, 0, -- 1_
|
||||
0, 3, 4, 3, 3, 2, 3, 0, 0, 4, 1, 3, 5, 5, 2, 0, -- 2_
|
||||
0, 1, 1, 0, 0, 4, 2, 0, 0, 0, 1, 0, 5, 2, 2, 0, -- 3_
|
||||
|
||||
0, 1, 0, 5, 5, 2, 2, 0, 0, 1, 1, 0, 0, 5, 2, 0, -- 4_
|
||||
0, 0, 0, 0, 6, 0, 0, 0, 0, 4, 1, 6, 0, 6, 0, 0, -- 5_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 6_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 7_
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 0_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 1_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 2_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 3_
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 4_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 5_
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, -- e0 6_
|
||||
0, 0, 6, 0, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- e0 7_
|
||||
|
||||
z80bus: process(CLK_16M)
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
if (IORQ_n = '0') and (WR_n = '0') then
|
||||
if (DATA_I(0) = '0') and (lastin_r(0) = '1') then
|
||||
if keyb_row_r < 9 then
|
||||
keyb_row_r <= keyb_row_r + 1;
|
||||
end if;
|
||||
elsif (DATA_I(1) = '0') and (lastin_r(1) = '1') then
|
||||
keyb_row_r <= to_unsigned(0, keyb_row_r'length);
|
||||
end if;
|
||||
lastin_r <= DATA_I(1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DATA_O <= key_buffer(to_integer(keyb_row_r));
|
||||
|
||||
process (CLK_16M)
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
ps2clk_s <= ps2clk_s(1 downto 0) & PS2_CLK;
|
||||
ps2data_s <= ps2data_s(1 downto 0) & PS2_DATA;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fsm: process (CLK_16M)
|
||||
variable next_state : states;
|
||||
variable line_v : integer range 0 to 8;
|
||||
variable bit_v : integer range 0 to 7;
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
next_state := state;
|
||||
case state is
|
||||
when ST_RESET =>
|
||||
key_buffer <= (X"FF", X"FF", X"FF", X"FF",
|
||||
X"FF", X"FF", X"FF", X"FF",
|
||||
X"FF", X"FF");
|
||||
next_state := ST_IDLE;
|
||||
when ST_IDLE =>
|
||||
if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge
|
||||
if ps2data_s(2) = '0' then
|
||||
count <= to_unsigned(0, count'length);
|
||||
parity_r <= '0';
|
||||
next_state := ST_READ;
|
||||
end if;
|
||||
end if;
|
||||
when ST_READ =>
|
||||
if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge
|
||||
key_in_r(to_integer(count)) <= ps2data_s(2);
|
||||
parity_r <= parity_r xor ps2data_s(2);
|
||||
if count = 7 then
|
||||
next_state := ST_PARITY;
|
||||
else
|
||||
count <= count + 1;
|
||||
end if;
|
||||
end if;
|
||||
when ST_PARITY =>
|
||||
if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge
|
||||
if parity_r = ps2data_s(2) then
|
||||
-- ext_r <= '0';
|
||||
-- up_r <= '0';
|
||||
next_state := ST_ERROR;
|
||||
else
|
||||
if key_in_r = X"E0" then
|
||||
ext_r <= '1';
|
||||
elsif key_in_r = X"F0" then
|
||||
up_r <= '1';
|
||||
else
|
||||
-- process key code
|
||||
line_v := line_lut(conv_integer(ext_r & key_in_r(6 downto 0)));
|
||||
bit_v := bit_lut(conv_integer(ext_r & key_in_r(6 downto 0)));
|
||||
if not ((line_v = 0) and (bit_v = 0)) then
|
||||
key_buffer(line_v)(bit_v) <= up_r;
|
||||
end if;
|
||||
ext_r <= '0';
|
||||
up_r <= '0';
|
||||
end if;
|
||||
next_state := ST_STOP;
|
||||
end if;
|
||||
end if;
|
||||
when ST_ERROR =>
|
||||
debug_evt_counter <= debug_evt_counter + 1;
|
||||
next_state := ST_IDLE;
|
||||
when ST_STOP =>
|
||||
next_state := ST_IDLE;
|
||||
when others => null;
|
||||
end case;
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- DEBUGLED <= debug_evt_counter;
|
||||
|
||||
PS2_CLK <= 'Z';
|
||||
PS2_DATA <= 'Z';
|
||||
end Behavioral;
|
||||
128
memory.vhd
Executable file
128
memory.vhd
Executable file
@@ -0,0 +1,128 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:22:46 12/30/2008
|
||||
-- Design Name:
|
||||
-- Module Name: memory - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity memory is
|
||||
Port (
|
||||
-- interface to Z80 bus
|
||||
DATA_I : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
DATA_O : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
ADDR_I : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
RD_N : in STD_LOGIC;
|
||||
WR_N : in STD_LOGIC;
|
||||
MREQ_N : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
CLKEN : in STD_LOGIC;
|
||||
-- interface to video generator
|
||||
VID_DATA_O : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
VID_ADDR_I : in STD_LOGIC_VECTOR(9 downto 0);
|
||||
VID_CLK : in STD_LOGIC);
|
||||
end memory;
|
||||
|
||||
architecture Behavioral of memory is
|
||||
component monitorrom IS
|
||||
port ( clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0);
|
||||
ena: in std_logic);
|
||||
END component;
|
||||
|
||||
component basic_rom
|
||||
port (
|
||||
clka : IN std_logic;
|
||||
addra : IN std_logic_VECTOR(12 downto 0);
|
||||
douta : OUT std_logic_VECTOR(7 downto 0);
|
||||
ena : in std_logic);
|
||||
end component;
|
||||
|
||||
component ram2kx8 IS
|
||||
port ( clka: IN std_logic;
|
||||
dina: IN std_logic_VECTOR(7 downto 0);
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
wea: IN std_logic_VECTOR(0 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0);
|
||||
ena: in std_logic;
|
||||
clkb: IN std_logic;
|
||||
dinb: IN std_logic_VECTOR(7 downto 0);
|
||||
addrb: IN std_logic_VECTOR(10 downto 0);
|
||||
web: IN std_logic_VECTOR(0 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(7 downto 0));
|
||||
END component;
|
||||
|
||||
signal monitorrom_data, basicrom_data, ram2kx8_1_dout, ram2kx8_2_dout, ram2kx8_1_doutb: std_logic_vector(7 downto 0);
|
||||
signal ram2kx8_1_addrb : std_logic_vector(10 downto 0);
|
||||
signal ram2kx8_1_we, ram2kx8_2_we: std_logic_vector(0 downto 0);
|
||||
begin
|
||||
monitorrom_inst: monitorrom port map( clka => CLK,
|
||||
addra => ADDR_I(10 downto 0),
|
||||
douta => monitorrom_data,
|
||||
ena => CLKEN);
|
||||
|
||||
basicrom_inst : basic_rom port map (
|
||||
clka => CLK,
|
||||
addra => ADDR_I(12 downto 0),
|
||||
douta => basicrom_data,
|
||||
ena => CLKEN);
|
||||
|
||||
ram2kx8_1_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00001") and (MREQ_N = '0') else '0';
|
||||
ram2kx8_2_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00010") and (MREQ_N = '0') else '0';
|
||||
ram2kx8_1_addrb <= '0' & VID_ADDR_I;
|
||||
|
||||
ram2kx8_inst_1: ram2kx8 port map( clka => CLK,
|
||||
dina => DATA_I,
|
||||
addra => ADDR_I(10 downto 0),
|
||||
wea => ram2kx8_1_we,
|
||||
douta => ram2kx8_1_dout,
|
||||
ena => CLKEN,
|
||||
clkb => VID_CLK,
|
||||
dinb => "00000000",
|
||||
addrb => ram2kx8_1_addrb,
|
||||
web => "0",
|
||||
doutb => ram2kx8_1_doutb);
|
||||
|
||||
ram2kx8_inst_2: ram2kx8 port map( clka => CLK,
|
||||
dina => DATA_I,
|
||||
addra => ADDR_I(10 downto 0),
|
||||
wea => ram2kx8_2_we,
|
||||
douta => ram2kx8_2_dout,
|
||||
ena => CLKEN,
|
||||
clkb => VID_CLK,
|
||||
dinb => "00000000",
|
||||
addrb => "00000000000",
|
||||
web => "0",
|
||||
doutb => open);
|
||||
|
||||
DATA_O <= monitorrom_data when ADDR_I(15 downto 11) = "00000" else
|
||||
ram2kx8_1_dout when ADDR_I(15 downto 11) = "00001" else
|
||||
ram2kx8_2_dout when ADDR_I(15 downto 11) = "00010" else
|
||||
basicrom_data when ADDR_I(15 downto 13) = "111" else
|
||||
"XXXXXXXX";
|
||||
|
||||
VID_DATA_O <= ram2kx8_1_doutb;
|
||||
end Behavioral;
|
||||
|
||||
23
nascom2.prj
Executable file
23
nascom2.prj
Executable file
@@ -0,0 +1,23 @@
|
||||
vhdl work memory.vhd
|
||||
vhdl work coregen/charrom.vhd
|
||||
vhdl work coregen/monitorrom.vhd
|
||||
vhdl work coregen/basic_rom.vhd
|
||||
vhdl work coregen/ram2kx8.vhd
|
||||
vhdl work coregen/dcm_in50.vhd
|
||||
vhdl work toplevel.vhd
|
||||
vhdl work T80a.vhd
|
||||
vhdl work T80.vhd
|
||||
vhdl work T80_ALU.vhd
|
||||
vhdl work T80_MCode.vhd
|
||||
vhdl work T80_RegX.vhd
|
||||
vhdl work T80_Pack.vhd
|
||||
vhdl work T80se.vhd
|
||||
vhdl work video.vhd
|
||||
vhdl work videogen.vhd
|
||||
vhdl work syncgen.vhd
|
||||
vhdl work keyboard.vhd
|
||||
vhdl work uart.vhd
|
||||
vhdl work kcpsm3.vhd
|
||||
vhdl work uartprog.vhd
|
||||
vhdl work fifo16x8.vhd
|
||||
vhdl work spi.vhd
|
||||
159
nascom2.ucf
Executable file
159
nascom2.ucf
Executable file
@@ -0,0 +1,159 @@
|
||||
###################################################
|
||||
# TIMING CONSTRAINTS
|
||||
###################################################
|
||||
# System Clock
|
||||
NET "CLKIN_50M" LOC = "E12"| IOSTANDARD = LVCMOS33;
|
||||
NET "CLKIN_50M" PERIOD = 20 ns HIGH 40 %;
|
||||
#NET "CLKIN_50M" TNM_NET = "CLKIN_50M";
|
||||
# VGA
|
||||
INST "BLUE<0>" TNM = "VGA";
|
||||
INST "BLUE<1>" TNM = "VGA";
|
||||
INST "BLUE<2>" TNM = "VGA";
|
||||
INST "BLUE<3>" TNM = "VGA";
|
||||
INST "GREEN<0>" TNM = "VGA";
|
||||
INST "GREEN<1>" TNM = "VGA";
|
||||
INST "GREEN<2>" TNM = "VGA";
|
||||
INST "GREEN<3>" TNM = "VGA";
|
||||
INST "HSYNC" TNM = "VGA";
|
||||
INST "RED<0>" TNM = "VGA";
|
||||
INST "RED<1>" TNM = "VGA";
|
||||
INST "RED<2>" TNM = "VGA";
|
||||
INST "RED<3>" TNM = "VGA";
|
||||
INST "VSYNC" TNM = "VGA";
|
||||
TIMEGRP "VGA" OFFSET = OUT 5.2 ns AFTER "CLKIN_50M" ;
|
||||
# Z80 BUS
|
||||
#INST "ADDR<0>" TNM = "Z80BUS";
|
||||
#INST "ADDR<1>" TNM = "Z80BUS";
|
||||
#INST "ADDR<10>" TNM = "Z80BUS";
|
||||
#INST "ADDR<11>" TNM = "Z80BUS";
|
||||
#INST "ADDR<12>" TNM = "Z80BUS";
|
||||
#INST "ADDR<13>" TNM = "Z80BUS";
|
||||
#INST "ADDR<14>" TNM = "Z80BUS";
|
||||
#INST "ADDR<15>" TNM = "Z80BUS";
|
||||
#INST "ADDR<2>" TNM = "Z80BUS";
|
||||
#INST "ADDR<3>" TNM = "Z80BUS";
|
||||
#INST "ADDR<4>" TNM = "Z80BUS";
|
||||
#INST "ADDR<5>" TNM = "Z80BUS";
|
||||
#INST "ADDR<6>" TNM = "Z80BUS";
|
||||
#INST "ADDR<7>" TNM = "Z80BUS";
|
||||
#INST "ADDR<8>" TNM = "Z80BUS";
|
||||
#INST "ADDR<9>" TNM = "Z80BUS";
|
||||
#INST "BUSAK_n" TNM = "Z80BUS";
|
||||
#INST "BUSRQ_n" TNM = "Z80BUS";
|
||||
#INST "DATA<0>" TNM = "Z80BUS";
|
||||
#INST "DATA<1>" TNM = "Z80BUS";
|
||||
#INST "DATA<2>" TNM = "Z80BUS";
|
||||
#INST "DATA<3>" TNM = "Z80BUS";
|
||||
#INST "DATA<4>" TNM = "Z80BUS";
|
||||
#INST "DATA<5>" TNM = "Z80BUS";
|
||||
#INST "DATA<6>" TNM = "Z80BUS";
|
||||
#INST "DATA<7>" TNM = "Z80BUS";
|
||||
#INST "HALT_n" TNM = "Z80BUS";
|
||||
#INST "INT_n" TNM = "Z80BUS";
|
||||
#INST "IORQ_n" TNM = "Z80BUS";
|
||||
#INST "M1_n" TNM = "Z80BUS";
|
||||
#INST "NMI_n" TNM = "Z80BUS";
|
||||
#INST "RD_n" TNM = "Z80BUS";
|
||||
#INST "RFSH_n" TNM = "Z80BUS";
|
||||
#INST "WAIT_n" TNM = "Z80BUS";
|
||||
#INST "WR_n" TNM = "Z80BUS";
|
||||
#TIMEGRP "Z80BUS" OFFSET = IN 10 ns BEFORE "CLKIN_50M" ;
|
||||
#TIMEGRP "Z80BUS" OFFSET = OUT 10 ns AFTER "CLKIN_50M" ;
|
||||
|
||||
###################################################
|
||||
# LOCATION CONSTRAINTS
|
||||
###################################################
|
||||
# For S3AN-Board
|
||||
# VGA
|
||||
NET "RED<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "RED<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "RED<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "RED<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "GREEN<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "GREEN<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "GREEN<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "GREEN<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "BLUE<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "BLUE<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "BLUE<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "BLUE<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
# Z80BUS -> FX2 connector
|
||||
#NET "ADDR<0>" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<1>" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<2>" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<3>" LOC = "B15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<4>" LOC = "A15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<5>" LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<6>" LOC = "A17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<7>" LOC = "B17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<8>" LOC = "A18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<9>" LOC = "C18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<10>" LOC = "A19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<11>" LOC = "B19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<12>" LOC = "A20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<13>" LOC = "B20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<14>" LOC = "C19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "ADDR<15>" LOC = "D19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<0>" LOC = "D18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<1>" LOC = "E17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<2>" LOC = "D20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<3>" LOC = "D21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<4>" LOC = "D22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<5>" LOC = "E22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<6>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "DATA<7>" LOC = "F19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "BUSAK_n" LOC = "F20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "BUSRQ_n" LOC = "E20" | IOSTANDARD = LVTTL;
|
||||
#NET "HALT_n" LOC = "G20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "INT_n" LOC = "G19" | IOSTANDARD = LVTTL;
|
||||
#NET "IORQ_n" LOC = "H19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "M1_n" LOC = "J18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "NMI_n" LOC = "K18" | IOSTANDARD = LVTTL;
|
||||
#NET "RD_n" LOC = "K17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "WR_n" LOC = "K19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "RFSH_n" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
|
||||
#NET "WAIT_n" LOC = "L19" | IOSTANDARD = LVTTL;
|
||||
# PS/2 Keyboard
|
||||
NET "PS2_CLK1" LOC = "W12" | IOSTANDARD = LVCMOS33 | PULLUP | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "PS2_DATA1" LOC = "V11" | IOSTANDARD = LVCMOS33 | PULLUP | DRIVE = 8 | SLEW = SLOW;
|
||||
# LEDs
|
||||
NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
# Buttons
|
||||
NET "BTN_NORTH" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN;
|
||||
NET "BTN_SOUTH" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN;
|
||||
NET "BTN_EAST" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN;
|
||||
NET "BTN_WEST" LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN;
|
||||
NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;
|
||||
# Switches
|
||||
NET "SW<3>" LOC = "T9" | IOSTANDARD = LVCMOS33;
|
||||
NET "SW<2>" LOC = "U8" | IOSTANDARD = LVCMOS33;
|
||||
NET "SW<1>" LOC = "U10" | IOSTANDARD = LVCMOS33;
|
||||
NET "SW<0>" LOC = "V8" | IOSTANDARD = LVCMOS33;
|
||||
# SPI
|
||||
NET "SPI_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
|
||||
NET "SPI_SS_B" LOC = "Y4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "DATAFLASH_WP" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
NET "DATAFLASH_RST" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
|
||||
# LCD interface
|
||||
NET "LCD_E" LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_RS" LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_RW" LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<6>" LOC = "AB16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
|
||||
15
nascom2.xst
Executable file
15
nascom2.xst
Executable file
@@ -0,0 +1,15 @@
|
||||
run
|
||||
-ifn nascom2.prj
|
||||
-ifmt mixed
|
||||
-top toplevel
|
||||
-ofn nascom2.ngc
|
||||
-ofmt NGC
|
||||
-p xc3s700an-fgg484-4
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-fsm_encoding auto
|
||||
-slice_utilization_ratio 1500#
|
||||
-bram_utilization_ratio 3#
|
||||
-sd coregen/
|
||||
-rtlview no
|
||||
-iob auto
|
||||
288
nascom2_t80.mpf
Executable file
288
nascom2_t80.mpf
Executable file
@@ -0,0 +1,288 @@
|
||||
;
|
||||
; Copyright Model Technology, a Mentor Graphics
|
||||
; Corporation company 2006, - All rights reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
|
||||
|
||||
; VHDL Section
|
||||
unisim = $MODEL_TECH/../xilinx/vhdl/unisim
|
||||
simprim = $MODEL_TECH/../xilinx/vhdl/simprim
|
||||
xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
|
||||
aim = $MODEL_TECH/../xilinx/vhdl/aim
|
||||
pls = $MODEL_TECH/../xilinx/vhdl/pls
|
||||
cpld = $MODEL_TECH/../xilinx/vhdl/cpld
|
||||
|
||||
; Verilog Section
|
||||
unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
|
||||
uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
|
||||
simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
|
||||
xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
|
||||
aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
|
||||
cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; Turn on VHDL-1993 as the default. Normally is off.
|
||||
VHDL93 = 1
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = false
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turns on incremental compilation of modules
|
||||
; Incremental = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
resolution = 1ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 20 ns
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after an assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Timf: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
;CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
||||
; for Verilog, PathSeparator = .
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, or deposit
|
||||
; or in other terms, fixed, wired or charged.
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated
|
||||
; else open files on first read or write
|
||||
; DelayFileOpen = 0
|
||||
|
||||
; Control VHDL files opened for write
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control number of VHDL files open concurrently
|
||||
; This number should always be less then the
|
||||
; current ulimit setting for max file descriptors
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; This controls the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the waveform window. The default
|
||||
; value or a value of zero tells VSIM to display the full name.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit
|
||||
; packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of a generate statement label. Don't quote it.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is to be compressed.
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
[lmc]
|
||||
[Project]
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 21
|
||||
Project_File_0 = C:/vhdl/nascom2_t80/toplevel.vhd
|
||||
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231501485 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_1 = C:/vhdl/nascom2_t80/T80se.vhd
|
||||
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230996942 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_2 = C:/vhdl/nascom2_t80/T80.vhd
|
||||
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941814 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_3 = C:/vhdl/nascom2_t80/T80a.vhd
|
||||
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230943266 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_4 = C:/vhdl/nascom2_t80/dcm_in50_sim.vhd
|
||||
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231002309 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_5 = C:/vhdl/nascom2_t80/syncgen.vhd
|
||||
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230988654 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_6 = C:/vhdl/nascom2_t80/T80s.vhd
|
||||
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230943564 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_7 = C:/vhdl/nascom2_t80/videogen.vhd
|
||||
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231006634 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_8 = C:/vhdl/nascom2_t80/T80_Pack.vhd
|
||||
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941826 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_9 = C:/vhdl/nascom2_t80/T80_MCode.vhd
|
||||
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941915 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_10 = C:/vhdl/nascom2_t80/T80_ALU.vhd
|
||||
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941923 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_11 = C:/vhdl/bmp_bench/sim_bmppack.vhd
|
||||
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231008643 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_12 = C:/vhdl/nascom2_t80/coregen/charrom.vhd
|
||||
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230983803 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_13 = C:/vhdl/nascom2_t80/coregen/ram2kx8.vhd
|
||||
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230997369 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_14 = C:/vhdl/nascom2_t80/video.vhd
|
||||
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230995258 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_15 = C:/vhdl/nascom2_t80/toplevel_tb.vhd
|
||||
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231010153 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_16 = C:/vhdl/nascom2_t80/coregen/monitorrom.vhd
|
||||
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231414214 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_17 = C:/vhdl/nascom2_t80/T80_Reg.vhd
|
||||
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_18 = C:/vhdl/nascom2_t80/memory.vhd
|
||||
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231511876 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_File_19 = C:/vhdl/nascom2_t80/T80_RegX.vhd
|
||||
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230977546 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
||||
Project_File_20 = C:/vhdl/nascom2_t80/keyboard.vhd
|
||||
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231514379 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ReOpenSourceFiles = 1
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
EditorState = {tabbed horizontal 1}
|
||||
Project_Major_Version = 6
|
||||
Project_Minor_Version = 2
|
||||
23
nascom2_vhdl.prj
Executable file
23
nascom2_vhdl.prj
Executable file
@@ -0,0 +1,23 @@
|
||||
vhdl work "C:\vhdl\nascom2_t80\memory.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\coregen\charrom.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\coregen\monitorrom.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\coregen\basic_rom.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\coregen\ram2kx8.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\coregen\dcm_in50.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\toplevel.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80a.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80_ALU.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80_MCode.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80_RegX.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80_Pack.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\T80se.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\video.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\videogen.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\syncgen.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\keyboard.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\uart.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\kcpsm3.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\uartprog.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\fifo16x8.vhd"
|
||||
vhdl work "C:\vhdl\nascom2_t80\spi.vhd"
|
||||
99
spi.vhd
Executable file
99
spi.vhd
Executable file
@@ -0,0 +1,99 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:52:22 12/30/2008
|
||||
-- Design Name:
|
||||
-- Module Name: toplevel - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity spi is
|
||||
|
||||
port (
|
||||
-- SPI
|
||||
MISO : in std_logic;
|
||||
MOSI, SCK : out std_logic;
|
||||
-- System bus
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
START : in std_logic;
|
||||
BUSY : out std_logic;
|
||||
CLK : in std_logic);
|
||||
|
||||
end spi;
|
||||
|
||||
architecture Behavioral of spi is
|
||||
type states is (ST_IDLE, ST_TRANSMIT);
|
||||
signal state : states := ST_IDLE;
|
||||
|
||||
signal dout_r, din_r : std_logic_vector(7 downto 0) := X"00";
|
||||
signal count : unsigned(2 downto 0) := to_unsigned(0, 3);
|
||||
signal spicycle : unsigned(1 downto 0) := to_unsigned(0, 2);
|
||||
|
||||
attribute iob : string;
|
||||
attribute iob of MOSI, SCK : signal is "true";
|
||||
begin -- Behavioral
|
||||
|
||||
fsm: process (CLK)
|
||||
variable next_state : states;
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
next_state := state;
|
||||
case state is
|
||||
when ST_IDLE =>
|
||||
BUSY <= '0';
|
||||
SCK <= '0';
|
||||
if START = '1' then
|
||||
dout_r <= DATA_I;
|
||||
spicycle <= to_unsigned(0, spicycle'length);
|
||||
count <= to_unsigned(0, count'length);
|
||||
next_state := ST_TRANSMIT;
|
||||
end if;
|
||||
when ST_TRANSMIT =>
|
||||
BUSY <= '1';
|
||||
if spicycle = 0 then -- data out
|
||||
MOSI <= dout_r(7);
|
||||
dout_r <= dout_r(6 downto 0) & '0';
|
||||
elsif spicycle = 1 then -- clock up
|
||||
SCK <= '1';
|
||||
elsif spicycle = 2 then -- nop
|
||||
elsif spicycle = 3 then -- clock down, sample data
|
||||
SCK <= '0';
|
||||
din_r(0) <= MISO;
|
||||
din_r(7 downto 1) <= din_r(6 downto 0);
|
||||
if count = 7 then
|
||||
next_state := ST_IDLE;
|
||||
else
|
||||
count <= count + 1;
|
||||
end if;
|
||||
end if;
|
||||
spicycle <= spicycle + 1;
|
||||
when others => null;
|
||||
end case;
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DATA_O <= din_r;
|
||||
|
||||
end Behavioral;
|
||||
87
syncgen.vhd
Executable file
87
syncgen.vhd
Executable file
@@ -0,0 +1,87 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10:37:34 12/08/2008
|
||||
-- Design Name:
|
||||
-- Module Name: syncgen - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity syncgen is
|
||||
Port ( CLKPIXEL : in STD_LOGIC;
|
||||
VSYNC : out STD_LOGIC;
|
||||
HSYNC : out STD_LOGIC;
|
||||
COLUMN : out STD_LOGIC_VECTOR (9 downto 0);
|
||||
ROW : out STD_LOGIC_VECTOR (9 downto 0));
|
||||
end syncgen;
|
||||
|
||||
architecture Behavioral of syncgen is
|
||||
signal hsync_i, hsync_i_old: std_logic := '1';
|
||||
signal vsync_i: std_logic := '1';
|
||||
signal row_i: std_logic_vector(9 downto 0) := "0000000000";
|
||||
signal column_i: std_logic_vector(9 downto 0) := "0000000000";
|
||||
begin
|
||||
hsync_p: process(CLKPIXEL)
|
||||
begin
|
||||
if rising_edge(CLKPIXEL) then
|
||||
if column_i = 799 then
|
||||
column_i <= "0000000000";
|
||||
else
|
||||
column_i <= column_i + 1;
|
||||
end if;
|
||||
|
||||
if column_i >= 658 and column_i <= 753 then -- generate hsync pulse (one clock early, it is delayed later)
|
||||
hsync_i <= '0'; -- hsync is low active
|
||||
else
|
||||
hsync_i <= '1';
|
||||
end if;
|
||||
|
||||
HSYNC <= hsync_i; -- delay hsync 1 clock
|
||||
end if;
|
||||
end process;
|
||||
|
||||
vsync_p: process(CLKPIXEL)
|
||||
begin
|
||||
if rising_edge(CLKPIXEL) then
|
||||
if (hsync_i = '0') and (hsync_i_old = '1') then
|
||||
if row_i = 524 then
|
||||
row_i <= "0000000000";
|
||||
else
|
||||
row_i <= row_i + 1;
|
||||
end if;
|
||||
|
||||
if row_i = 493 then -- generate vsync pulse
|
||||
vsync_i <= '0'; -- vsync is low active
|
||||
else
|
||||
vsync_i <= '1';
|
||||
end if;
|
||||
end if;
|
||||
hsync_i_old <= hsync_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
COLUMN <= column_i;
|
||||
ROW <= row_i;
|
||||
VSYNC <= vsync_i;
|
||||
end Behavioral;
|
||||
|
||||
9
test.coe
Executable file
9
test.coe
Executable file
@@ -0,0 +1,9 @@
|
||||
memory_initialization_radix = 16;
|
||||
memory_initialization_vector =
|
||||
31, 00, 10,
|
||||
dd, 21, ad, de,
|
||||
fd, 21, ef, be,
|
||||
dd, e5,
|
||||
fd, e3,
|
||||
dd, e1,
|
||||
76;
|
||||
104
textgen.vhd
Executable file
104
textgen.vhd
Executable file
@@ -0,0 +1,104 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:50:00 12/08/2008
|
||||
-- Design Name:
|
||||
-- Module Name: textgen - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity textgen is
|
||||
Port ( OE : in STD_LOGIC;
|
||||
CHRX : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
CHRY : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
SCRADR : in STD_LOGIC_VECTOR (11 downto 0);
|
||||
RED : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
GREEN : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
BLUE : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
CLK : in STD_LOGIC);
|
||||
end textgen;
|
||||
|
||||
architecture Behavioral of textgen is
|
||||
|
||||
component charrom IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(11 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END component;
|
||||
|
||||
component textram IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
dina: IN std_logic_VECTOR(7 downto 0);
|
||||
addra: IN std_logic_VECTOR(11 downto 0);
|
||||
wea: IN std_logic_VECTOR(0 downto 0);
|
||||
douta: OUT std_logic_VECTOR(7 downto 0));
|
||||
END component;
|
||||
signal out_i, oe_i: std_logic := '0';
|
||||
signal charrom_adr, textram_adr: std_logic_vector(11 downto 0);
|
||||
signal charrom_data, textram_data: std_logic_vector(7 downto 0);
|
||||
signal oe_d1, oe_d2, oe_d3: std_logic := '0';
|
||||
begin
|
||||
textram_adr <= SCRADR;
|
||||
|
||||
textram_inst: textram port map( clka => CLK,
|
||||
dina => "00000000",
|
||||
addra => textram_adr,
|
||||
wea => "0",
|
||||
douta => textram_data);
|
||||
|
||||
charrom_adr(11 downto 4) <= textram_data;
|
||||
charrom_adr(3 downto 0) <= CHRY;
|
||||
|
||||
charrom_inst: charrom port map( clka => CLK,
|
||||
addra => charrom_adr,
|
||||
douta => charrom_data);
|
||||
|
||||
|
||||
process (CLK)
|
||||
variable bitmap: std_logic_vector(7 downto 0) := "00000000";
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if CHRX = 3 then
|
||||
bitmap := charrom_data;
|
||||
end if;
|
||||
out_i <= bitmap((conv_integer(2 - CHRX)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
oe_delay: process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
oe_d1 <= OE;
|
||||
oe_d2 <= oe_d1;
|
||||
oe_d3 <= oe_d2;
|
||||
oe_i <= oe_d3;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
RED <= (others => out_i) when oe_i = '1' else "0000";
|
||||
GREEN <= (others => out_i) when oe_i = '1' else "0000";
|
||||
BLUE <= (others => out_i) when oe_i = '1' else "0000";
|
||||
end Behavioral;
|
||||
|
||||
318
toplevel.vhd
Executable file
318
toplevel.vhd
Executable file
@@ -0,0 +1,318 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:52:22 12/30/2008
|
||||
-- Design Name:
|
||||
-- Module Name: toplevel - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity toplevel is
|
||||
Port (
|
||||
-- Clock (50 MHz)
|
||||
CLKIN_50M : in STD_LOGIC;
|
||||
-- VGA out
|
||||
RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
HSYNC, VSYNC : out STD_LOGIC;
|
||||
-- PS2 Keyboard
|
||||
PS2_CLK1, PS2_DATA1 : inout STD_LOGIC;
|
||||
-- LEDs
|
||||
LED : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
-- Buttons
|
||||
BTN_NORTH : in STD_LOGIC;
|
||||
BTN_SOUTH : in STD_LOGIC;
|
||||
BTN_EAST : in STD_LOGIC;
|
||||
BTN_WEST : in STD_LOGIC;
|
||||
ROT_CENTER : in STD_LOGIC;
|
||||
-- Switches - 3=Enable IORQ breakpoint, 2,1,0=N/A
|
||||
SW : in STD_LOGIC_VECTOR(3 downto 0);
|
||||
-- SPI for Atmel Dataflash
|
||||
SPI_MISO : in std_logic;
|
||||
SPI_MOSI : out std_logic;
|
||||
SPI_SCK : out std_logic;
|
||||
SPI_SS_B : out std_logic := '1';
|
||||
DATAFLASH_WP : out std_logic;
|
||||
DATAFLASH_RST : out std_logic;
|
||||
-- LCD interface
|
||||
LCD_DB : inout std_logic_vector(7 downto 0);
|
||||
LCD_E, LCD_RS, LCD_RW : out std_logic
|
||||
);
|
||||
end toplevel;
|
||||
|
||||
architecture Behavioral of toplevel is
|
||||
component dcm_in50
|
||||
port (
|
||||
CLKIN_IN : in std_logic;
|
||||
RST_IN : in std_logic;
|
||||
CLKFX_OUT : out std_logic;
|
||||
CLKIN_IBUFG_OUT : out std_logic;
|
||||
CLK0_OUT : out std_logic;
|
||||
LOCKED_OUT : out std_logic);
|
||||
end component;
|
||||
|
||||
component memory
|
||||
port (
|
||||
DATA_I : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
DATA_O : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
ADDR_I : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
RD_N : in STD_LOGIC;
|
||||
WR_N : in STD_LOGIC;
|
||||
MREQ_N : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
CLKEN : in STD_LOGIC;
|
||||
VID_DATA_O : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
VID_ADDR_I : in STD_LOGIC_VECTOR(9 downto 0);
|
||||
VID_CLK : in STD_LOGIC);
|
||||
end component;
|
||||
|
||||
component T80se
|
||||
generic (
|
||||
Mode : integer := 0;
|
||||
T2Write : integer := 0;
|
||||
IOWait : integer := 0);
|
||||
port (
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0));
|
||||
end component;
|
||||
|
||||
component video
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
ADDR_O : out std_logic_vector(9 downto 0);
|
||||
RED, GREEN, BLUE : out std_logic_vector(3 downto 0);
|
||||
VSYNC, HSYNC : out std_logic);
|
||||
end component;
|
||||
|
||||
component keyboard
|
||||
port (
|
||||
PS2_CLK : inout std_logic;
|
||||
PS2_DATA : inout std_logic;
|
||||
CLK_16M : in std_logic;
|
||||
IORQ_n : in std_logic;
|
||||
RD_n, WR_n : in std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
DEBUG : out std_logic_vector(7 downto 0));
|
||||
end component;
|
||||
|
||||
component uart
|
||||
port (
|
||||
CLK_16M : in std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
ADDR_I : in std_logic_vector(1 downto 0);
|
||||
IORQ_n, RD_n, WR_n : in std_logic;
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
-- SPI for Atmel Dataflash
|
||||
SPI_MISO : in std_logic;
|
||||
SPI_MOSI : out std_logic;
|
||||
SPI_SCK : out std_logic;
|
||||
SPI_SS_B : out std_logic := '1';
|
||||
DATAFLASH_WP : out std_logic;
|
||||
DATAFLASH_RST : out std_logic;
|
||||
-- LCD interface
|
||||
LCD_DB : inout std_logic_vector(7 downto 0);
|
||||
LCD_E, LCD_RS, LCD_RW : out std_logic;
|
||||
-- Buttons
|
||||
BTN_NORTH : in STD_LOGIC;
|
||||
BTN_SOUTH : in STD_LOGIC;
|
||||
BTN_EAST : in STD_LOGIC;
|
||||
BTN_WEST : in STD_LOGIC;
|
||||
ROT_CENTER : in STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal CLK_16M, CLK_25M : std_logic;
|
||||
|
||||
signal z80cpu_addr: std_logic_vector(15 downto 0);
|
||||
signal z80cpu_datao, z80cpu_datai, memory_datao: std_logic_vector(7 downto 0);
|
||||
signal z80cpu_mreq_n, z80cpu_iorq_n, z80cpu_wr_n, z80cpu_rd_n,
|
||||
z80cpu_clken, z80cpu_halt_n, z80cpu_busak_n, z80cpu_m1_n,
|
||||
z80cpu_rfsh_n, z80cpu_reset_n: std_logic;
|
||||
|
||||
signal video_datai : std_logic_vector(7 downto 0);
|
||||
signal video_addro : std_logic_vector(9 downto 0);
|
||||
|
||||
signal red_out, blue_out, green_out : std_logic_vector(3 downto 0);
|
||||
signal hsync_out, vsync_out : std_logic;
|
||||
|
||||
signal keyb_datao : std_logic_vector(7 downto 0);
|
||||
signal keyb_iorq_n : std_logic;
|
||||
|
||||
signal uart_datao : std_logic_vector(7 downto 0);
|
||||
signal uart_iorq_n : std_logic;
|
||||
|
||||
-- shift register for z80 CLKEN
|
||||
-- signal z80cpu_clken_gen : std_logic_vector(1 downto 0) := "01"; -- = 8 MHz
|
||||
-- signal z80cpu_clken_gen : std_logic_vector(3 downto 0) := "0001"; -- = 4 MHz
|
||||
signal z80cpu_clken_gen : std_logic_vector(7 downto 0) := "00000001"; -- = 2 MHz
|
||||
-- signal z80cpu_clken_gen : std_logic_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000001"; -- = 62.5 KHz
|
||||
signal stop : std_logic := '0';
|
||||
begin
|
||||
dcm_in50_inst: dcm_in50
|
||||
port map (
|
||||
CLKIN_IN => CLKIN_50M,
|
||||
RST_IN => '0',
|
||||
CLKFX_OUT => CLK_16M,
|
||||
CLKIN_IBUFG_OUT => open,
|
||||
CLK0_OUT => CLK_25M,
|
||||
LOCKED_OUT => open);
|
||||
|
||||
clken: process(CLK_16M)
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
z80cpu_clken_gen <= z80cpu_clken_gen((z80cpu_clken_gen'left-1) downto 0)
|
||||
& z80cpu_clken_gen(z80cpu_clken_gen'left);
|
||||
if BTN_NORTH = '1' then
|
||||
stop <= '0';
|
||||
elsif (z80cpu_iorq_n = '0') and (SW(3) = '1') then
|
||||
stop <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
z80cpu_clken <= '1' when (stop = '0') and (z80cpu_clken_gen(z80cpu_clken_gen'left) = '1') else
|
||||
'0';
|
||||
|
||||
z80cpu_reset_n <= '0' when (BTN_SOUTH = '1') else
|
||||
'1';
|
||||
|
||||
z80cpu_datai <= memory_datao when z80cpu_mreq_n = '0' else
|
||||
keyb_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "000") else
|
||||
uart_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "001") else
|
||||
uart_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "010") else
|
||||
"XXXXXXXX";
|
||||
|
||||
z80cpu_inst : T80se port map (
|
||||
RESET_n => z80cpu_reset_n,
|
||||
CLK_n => CLK_16M,
|
||||
CLKEN => z80cpu_clken,
|
||||
WAIT_n => '1',
|
||||
INT_n => '1',
|
||||
NMI_n => '1',
|
||||
BUSRQ_n => '1',
|
||||
M1_n => z80cpu_m1_n,
|
||||
MREQ_n => z80cpu_mreq_n,
|
||||
IORQ_n => z80cpu_iorq_n,
|
||||
RD_n => z80cpu_rd_n,
|
||||
WR_n => z80cpu_wr_n,
|
||||
RFSH_n => z80cpu_rfsh_n,
|
||||
HALT_n => z80cpu_halt_n,
|
||||
BUSAK_n => z80cpu_busak_n,
|
||||
A => z80cpu_addr,
|
||||
DI => z80cpu_datai,
|
||||
DO => z80cpu_datao);
|
||||
|
||||
|
||||
--LED <= z80cpu_iorq_n & z80cpu_rd_n & z80cpu_wr_n & z80cpu_addr(1) & "0000";
|
||||
|
||||
memory_inst: memory port map( DATA_I => z80cpu_datao,
|
||||
DATA_O => memory_datao,
|
||||
ADDR_I => z80cpu_addr,
|
||||
RD_N => z80cpu_rd_n,
|
||||
WR_N => z80cpu_wr_n,
|
||||
MREQ_N => z80cpu_mreq_n,
|
||||
CLK => CLK_16M,
|
||||
CLKEN => z80cpu_clken,
|
||||
VID_DATA_O => video_datai,
|
||||
VID_ADDR_I => video_addro,
|
||||
VID_CLK => CLK_25M);
|
||||
|
||||
|
||||
keyb_iorq_n <= '0' when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "000") else
|
||||
'1';
|
||||
|
||||
keyboard_inst : keyboard port map (
|
||||
PS2_CLK => PS2_CLK1,
|
||||
PS2_DATA => PS2_DATA1,
|
||||
CLK_16M => CLK_16M,
|
||||
IORQ_n => keyb_iorq_n,
|
||||
RD_n => z80cpu_rd_n,
|
||||
WR_n => z80cpu_wr_n,
|
||||
DATA_I => z80cpu_datao,
|
||||
DATA_O => keyb_datao,
|
||||
DEBUG => LED);
|
||||
|
||||
uart_iorq_n <= '0' when (z80cpu_iorq_n = '0') and ((z80cpu_addr(2 downto 0) = "001") or
|
||||
(z80cpu_addr(2 downto 0) = "010")) else
|
||||
'1';
|
||||
|
||||
uart_inst : uart port map (
|
||||
CLK_16M => CLK_16M,
|
||||
DATA_I => z80cpu_datao,
|
||||
ADDR_I => z80cpu_addr(1 downto 0),
|
||||
RD_n => z80cpu_rd_n,
|
||||
WR_n => z80cpu_wr_n,
|
||||
IORQ_n => uart_iorq_n,
|
||||
DATA_O => uart_datao,
|
||||
SPI_MISO => SPI_MISO,
|
||||
SPI_MOSI => SPI_MOSI,
|
||||
SPI_SCK => SPI_SCK,
|
||||
SPI_SS_B => SPI_SS_B,
|
||||
DATAFLASH_WP => DATAFLASH_WP,
|
||||
DATAFLASH_RST => DATAFLASH_RST,
|
||||
LCD_DB => LCD_DB,
|
||||
LCD_E => LCD_E,
|
||||
LCD_RS => LCD_RS,
|
||||
LCD_RW => LCD_RW,
|
||||
BTN_NORTH => BTN_NORTH,
|
||||
BTN_EAST => BTN_EAST,
|
||||
BTN_SOUTH => BTN_SOUTH,
|
||||
BTN_WEST => BTN_WEST,
|
||||
ROT_CENTER => ROT_CENTER
|
||||
);
|
||||
|
||||
video_inst : video port map (
|
||||
CLK => CLK_25M,
|
||||
DATA_I => video_datai,
|
||||
ADDR_O => video_addro,
|
||||
RED => red_out,
|
||||
GREEN => green_out,
|
||||
BLUE => blue_out,
|
||||
VSYNC => vsync_out,
|
||||
HSYNC => hsync_out);
|
||||
|
||||
RED <= red_out;
|
||||
GREEN <= green_out;
|
||||
BLUE <= blue_out;
|
||||
HSYNC <= hsync_out;
|
||||
VSYNC <= vsync_out;
|
||||
end Behavioral;
|
||||
|
||||
155
toplevel_tb.vhd
Executable file
155
toplevel_tb.vhd
Executable file
@@ -0,0 +1,155 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : Testbench for design "toplevel"
|
||||
-- Project :
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : toplevel_tb.vhd
|
||||
-- Author : U-MATTHIAS-THINKP\Matthias <Matthias@matthias-thinkp>
|
||||
-- Company :
|
||||
-- Created : 2009-01-03
|
||||
-- Last update: 2009-01-03
|
||||
-- Platform :
|
||||
-- Standard : VHDL'87
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2009
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2009-01-03 1.0 Matthias Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.sim_bmppack.all;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
entity toplevel_tb is
|
||||
|
||||
end toplevel_tb;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
architecture tb of toplevel_tb is
|
||||
|
||||
component toplevel
|
||||
port (
|
||||
-- Clock (50 MHz)
|
||||
CLKIN_50M : in STD_LOGIC;
|
||||
-- NASBUS
|
||||
ADDR : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
DATA : inout STD_LOGIC_VECTOR (7 downto 0);
|
||||
M1_n : out STD_LOGIC;
|
||||
MREQ_n : out STD_LOGIC;
|
||||
IORQ_n : out STD_LOGIC;
|
||||
WR_n : out STD_LOGIC;
|
||||
RD_n : out STD_LOGIC;
|
||||
RFSH_n : out STD_LOGIC;
|
||||
HALT_n : out STD_LOGIC;
|
||||
BUSAK_n : out STD_LOGIC;
|
||||
RESET_n : in STD_LOGIC;
|
||||
WAIT_n : in STD_LOGIC;
|
||||
INT_n : in STD_LOGIC;
|
||||
NMI_n : in STD_LOGIC;
|
||||
BUSRQ_n : in STD_LOGIC;
|
||||
-- VGA out
|
||||
RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
HSYNC, VSYNC : out STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
-- component ports
|
||||
signal CLKIN_50M : STD_LOGIC := '0';
|
||||
signal ADDR : STD_LOGIC_VECTOR (15 downto 0);
|
||||
signal DATA : STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal M1_n : STD_LOGIC;
|
||||
signal MREQ_n : STD_LOGIC;
|
||||
signal IORQ_n : STD_LOGIC;
|
||||
signal WR_n : STD_LOGIC;
|
||||
signal RD_n : STD_LOGIC;
|
||||
signal RFSH_n : STD_LOGIC;
|
||||
signal HALT_n : STD_LOGIC;
|
||||
signal BUSAK_n : STD_LOGIC;
|
||||
signal RESET_n : STD_LOGIC := '0';
|
||||
signal WAIT_n : STD_LOGIC := '1';
|
||||
signal INT_n : STD_LOGIC := '1';
|
||||
signal NMI_n : STD_LOGIC := '1';
|
||||
signal BUSRQ_n : STD_LOGIC := '1';
|
||||
signal RED, GREEN, BLUE : std_logic_vector(3 downto 0);
|
||||
signal VSYNC, HSYNC : std_logic;
|
||||
|
||||
begin -- tb
|
||||
|
||||
-- component instantiation
|
||||
DUT: toplevel
|
||||
port map (
|
||||
CLKIN_50M => CLKIN_50M,
|
||||
ADDR => ADDR,
|
||||
DATA => DATA,
|
||||
M1_n => M1_n,
|
||||
MREQ_n => MREQ_n,
|
||||
IORQ_n => IORQ_n,
|
||||
WR_n => WR_n,
|
||||
RD_n => RD_n,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
RESET_n => RESET_n,
|
||||
WAIT_n => WAIT_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
RED => RED,
|
||||
GREEN => GREEN,
|
||||
BLUE => BLUE,
|
||||
VSYNC => VSYNC,
|
||||
HSYNC => HSYNC
|
||||
);
|
||||
|
||||
-- clock generation
|
||||
CLKIN_50M <= not CLKIN_50M after 10 ns;
|
||||
|
||||
-- waveform generation
|
||||
WaveGen_Proc: process
|
||||
begin
|
||||
-- insert signal assignments here
|
||||
wait for 100 ns;
|
||||
RESET_n <= '1';
|
||||
wait;
|
||||
end process WaveGen_Proc;
|
||||
|
||||
VGARead: process
|
||||
variable i: integer := 0;
|
||||
variable pixeldata : std_logic_vector(23 downto 0);
|
||||
begin
|
||||
ReadFile("vga.bmp");
|
||||
wait until CLKIN_50M = '1'; -- wait for uut to stat
|
||||
wait for 260 ns; -- wait for vga frame to start (depends
|
||||
-- on latency of UUT)
|
||||
while true loop
|
||||
for y in 479 downto 0 loop
|
||||
for x in 0 to 639 loop
|
||||
pixeldata := RED & "0000" & GREEN & "0000" & BLUE & "0000";
|
||||
SetPixel(x, y, pixeldata);
|
||||
wait for 40 ns;
|
||||
end loop; -- x
|
||||
wait for 6400 ns;
|
||||
end loop; -- x
|
||||
wait for 1440 us;
|
||||
WriteFile("vga" & integer'image(i) & ".bmp");
|
||||
i := i + 1;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
end tb;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
configuration toplevel_tb_tb_cfg of toplevel_tb is
|
||||
for tb
|
||||
end for;
|
||||
end toplevel_tb_tb_cfg;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
259
uart.vhd
Executable file
259
uart.vhd
Executable file
@@ -0,0 +1,259 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:52:22 12/30/2008
|
||||
-- Design Name:
|
||||
-- Module Name: toplevel - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity uart is
|
||||
|
||||
port (
|
||||
CLK_16M : in std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
ADDR_I : in std_logic_vector(1 downto 0);
|
||||
IORQ_n, RD_n, WR_n : in std_logic;
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
-- SPI for Atmel Dataflash
|
||||
SPI_MISO : in std_logic;
|
||||
SPI_MOSI : out std_logic;
|
||||
SPI_SCK : out std_logic;
|
||||
SPI_SS_B : out std_logic := '1';
|
||||
DATAFLASH_WP : out std_logic;
|
||||
DATAFLASH_RST : out std_logic;
|
||||
-- LCD interface
|
||||
LCD_DB : inout std_logic_vector(7 downto 0);
|
||||
LCD_E, LCD_RS, LCD_RW : out std_logic;
|
||||
-- Buttons
|
||||
BTN_NORTH : in STD_LOGIC;
|
||||
BTN_SOUTH : in STD_LOGIC;
|
||||
BTN_EAST : in STD_LOGIC;
|
||||
BTN_WEST : in STD_LOGIC;
|
||||
ROT_CENTER : in STD_LOGIC);
|
||||
|
||||
end uart;
|
||||
|
||||
architecture Behavioral of uart is
|
||||
|
||||
component kcpsm3
|
||||
port (
|
||||
address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
component uartprog
|
||||
port (
|
||||
address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
component fifo16x8
|
||||
port (
|
||||
DATAIN : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
WRITESTB : in STD_LOGIC;
|
||||
DATAOUT : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
READSTB : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
FULL : out STD_LOGIC;
|
||||
EMPTY : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
component spi
|
||||
port (
|
||||
MISO : in std_logic;
|
||||
MOSI, SCK : out std_logic;
|
||||
DATA_I : in std_logic_vector(7 downto 0);
|
||||
DATA_O : out std_logic_vector(7 downto 0);
|
||||
START : in std_logic;
|
||||
BUSY : out std_logic;
|
||||
CLK : in std_logic);
|
||||
end component;
|
||||
|
||||
signal receive_r, transmit_r : std_logic_vector(7 downto 0);
|
||||
signal drt_r, drr_r : std_logic := '0';
|
||||
|
||||
signal kcpsm3_addr : std_logic_vector(9 downto 0);
|
||||
signal kcpsm3_instr : std_logic_vector(17 downto 0);
|
||||
signal kcpsm3_portid, kcpsm3_outport, kcpsm3_inport : std_logic_vector(7 downto 0);
|
||||
signal kcpsm3_wrstb, kcpsm3_rdstb : std_logic;
|
||||
|
||||
attribute iob : string;
|
||||
signal lcdctrl_r : std_logic_vector(2 downto 0) := "000";
|
||||
signal lcdout_r : std_logic_vector(7 downto 0) := X"00";
|
||||
attribute iob of lcdout_r : signal is "true";
|
||||
attribute iob of lcdctrl_r : signal is "true";
|
||||
|
||||
signal spi_datao : std_logic_vector(7 downto 0);
|
||||
signal spi_start, spi_busy : std_logic;
|
||||
|
||||
signal iorq_old : std_logic := '0';
|
||||
|
||||
signal fifo_t_wrstb, fifo_t_rdstb, fifo_t_full, fifo_t_empty, fifo_r_wrstb, fifo_r_rdstb, fifo_r_full, fifo_r_empty : std_logic;
|
||||
signal fifo_r_din, fifo_r_dout, fifo_t_din, fifo_t_dout : std_logic_vector(7 downto 0);
|
||||
begin -- Behavioral
|
||||
|
||||
kcpsm3_inst : kcpsm3 port map (
|
||||
address => kcpsm3_addr,
|
||||
instruction => kcpsm3_instr,
|
||||
port_id => kcpsm3_portid,
|
||||
write_strobe => kcpsm3_wrstb,
|
||||
out_port => kcpsm3_outport,
|
||||
read_strobe => kcpsm3_rdstb,
|
||||
in_port => kcpsm3_inport,
|
||||
interrupt => '0',
|
||||
interrupt_ack => open,
|
||||
reset => '0',
|
||||
clk => CLK_16M);
|
||||
|
||||
prog_inst : uartprog port map (
|
||||
address => kcpsm3_addr,
|
||||
instruction => kcpsm3_instr,
|
||||
clk => CLK_16M);
|
||||
|
||||
spi_inst : spi port map (
|
||||
MISO => SPI_MISO,
|
||||
MOSI => SPI_MOSI,
|
||||
SCK => SPI_SCK,
|
||||
DATA_I => kcpsm3_outport,
|
||||
DATA_O => spi_datao,
|
||||
START => spi_start,
|
||||
BUSY => spi_busy,
|
||||
CLK => CLK_16M);
|
||||
|
||||
spi_start <= '1' when (kcpsm3_wrstb = '1') and (kcpsm3_portid = X"02") else
|
||||
'0';
|
||||
|
||||
spi_iface: process (CLK_16M)
|
||||
begin -- process spi_iface
|
||||
if rising_edge(CLK_16M) then
|
||||
if (kcpsm3_wrstb = '1') then
|
||||
if (kcpsm3_portid = X"03") then
|
||||
SPI_SS_B <= kcpsm3_outport(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
lcd_iface: process (CLK_16M)
|
||||
begin -- process lcd_iface
|
||||
if rising_edge(CLK_16M) then
|
||||
if (kcpsm3_wrstb = '1') then
|
||||
if (kcpsm3_portid = X"04") then
|
||||
lcdctrl_r <= kcpsm3_outport(2 downto 0);
|
||||
elsif kcpsm3_portid = X"05" then
|
||||
lcdout_r <= kcpsm3_outport;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process lcd_iface;
|
||||
|
||||
kcpsm3_inport <= fifo_t_dout when kcpsm3_portid = X"00" else
|
||||
"000000" & fifo_t_empty & fifo_r_full when kcpsm3_portid = X"01" else
|
||||
spi_datao when kcpsm3_portid = X"02" else
|
||||
"0000000" & spi_busy when kcpsm3_portid = X"03" else
|
||||
LCD_DB when kcpsm3_portid = X"05" else
|
||||
"00000" & lcdctrl_r when kcpsm3_portid = X"04" else
|
||||
"000" & ROT_CENTER & BTN_NORTH & BTN_EAST & BTN_SOUTH & BTN_WEST when kcpsm3_portid = X"06" else
|
||||
"XXXXXXXX";
|
||||
|
||||
process (CLK_16M)
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
fifo_r_wrstb <= '0';
|
||||
fifo_t_rdstb <= '0';
|
||||
if (kcpsm3_wrstb = '1') then
|
||||
if (kcpsm3_portid = X"00") then
|
||||
fifo_r_din <= kcpsm3_outport;
|
||||
fifo_r_wrstb <= '1';
|
||||
end if;
|
||||
elsif (kcpsm3_rdstb = '1') then
|
||||
if (kcpsm3_portid = X"00") then
|
||||
fifo_t_rdstb <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fifo16x8_inst_transmit : fifo16x8 port map (
|
||||
DATAIN => fifo_t_din,
|
||||
WRITESTB => fifo_t_wrstb,
|
||||
DATAOUT => fifo_t_dout,
|
||||
READSTB => fifo_t_rdstb,
|
||||
CLK => CLK_16M,
|
||||
FULL => fifo_t_full,
|
||||
EMPTY => fifo_t_empty);
|
||||
|
||||
fifo16x8_inst_receive : fifo16x8 port map (
|
||||
DATAIN => fifo_r_din,
|
||||
WRITESTB => fifo_r_wrstb,
|
||||
DATAOUT => fifo_r_dout,
|
||||
READSTB => fifo_r_rdstb,
|
||||
CLK => CLK_16M,
|
||||
FULL => fifo_r_full,
|
||||
EMPTY => fifo_r_empty);
|
||||
|
||||
z80bus: process (CLK_16M)
|
||||
begin
|
||||
if rising_edge(CLK_16M) then
|
||||
fifo_r_rdstb <= '0';
|
||||
fifo_t_wrstb <= '0';
|
||||
if (iorq_old = '1') and (IORQ_n = '0') then
|
||||
if ADDR_I = "01" then
|
||||
if RD_n = '0' then -- read receiver register
|
||||
DATA_O <= fifo_r_dout;
|
||||
fifo_r_rdstb <= '1';
|
||||
elsif WR_n = '0' then -- transmitter buffer load
|
||||
fifo_t_din <= DATA_I;
|
||||
fifo_t_wrstb <= '1';
|
||||
end if;
|
||||
elsif ADDR_I = "10" then
|
||||
if RD_n = '0' then -- read status flags
|
||||
DATA_O <= not fifo_r_empty & not fifo_t_full & "XX000X"; -- DR, TBRE, x, x, FE, PE, OE, x
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
iorq_old <= IORQ_n;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
LCD_DB <= lcdout_r when lcdctrl_r(2) = '0' else
|
||||
"ZZZZZZZZ";
|
||||
LCD_E <= lcdctrl_r(0);
|
||||
LCD_RS <= lcdctrl_r(1);
|
||||
LCD_RW <= lcdctrl_r(2);
|
||||
|
||||
DATAFLASH_RST <= '1';
|
||||
DATAFLASH_WP <= '1';
|
||||
|
||||
end Behavioral;
|
||||
2
uart_prog.psm
Executable file
2
uart_prog.psm
Executable file
@@ -0,0 +1,2 @@
|
||||
done:
|
||||
JUMP done
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user