73 lines
1.8 KiB
VHDL
Executable File
73 lines
1.8 KiB
VHDL
Executable File
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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:10:50 12/28/2008
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-- Design Name:
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-- Module Name: fifo16x8 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity fifo16x8 is
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Port ( DATAIN : in STD_LOGIC_VECTOR (7 downto 0);
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WRITESTB : in STD_LOGIC;
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DATAOUT : out STD_LOGIC_VECTOR (7 downto 0);
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READSTB : in STD_LOGIC;
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CLK : in STD_LOGIC;
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FULL : out STD_LOGIC;
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EMPTY : out STD_LOGIC);
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end fifo16x8;
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architecture Behavioral of fifo16x8 is
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signal counter: std_logic_vector(3 downto 0) := "1111";
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begin
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shift: for i in 0 to 7 generate
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srl16e_inst: SRL16E port map(
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Q => DATAOUT(i),
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A0 => counter(0),
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A1 => counter(1),
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A2 => counter(2),
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A3 => counter(3),
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CE => WRITESTB,
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CLK => CLK,
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D => DATAIN(i));
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end generate;
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fifo: process(CLK)
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begin
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if rising_edge(CLK) then
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if (WRITESTB = '0') and (READSTB = '1') then
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counter <= counter - 1;
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elsif (WRITESTB = '1') and (READSTB = '0') then
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counter <= counter + 1;
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else
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counter <= counter;
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end if;
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end if;
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end process;
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FULL <= '1' when counter = "1110" else '0';
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EMPTY <= '1' when counter = "1111" else '0';
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end Behavioral;
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