88 lines
2.2 KiB
VHDL
Executable File
88 lines
2.2 KiB
VHDL
Executable File
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:37:34 12/08/2008
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-- Design Name:
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-- Module Name: syncgen - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity syncgen is
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Port ( CLKPIXEL : in STD_LOGIC;
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VSYNC : out STD_LOGIC;
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HSYNC : out STD_LOGIC;
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COLUMN : out STD_LOGIC_VECTOR (9 downto 0);
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ROW : out STD_LOGIC_VECTOR (9 downto 0));
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end syncgen;
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architecture Behavioral of syncgen is
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signal hsync_i, hsync_i_old: std_logic := '1';
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signal vsync_i: std_logic := '1';
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signal row_i: std_logic_vector(9 downto 0) := "0000000000";
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signal column_i: std_logic_vector(9 downto 0) := "0000000000";
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begin
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hsync_p: process(CLKPIXEL)
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begin
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if rising_edge(CLKPIXEL) then
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if column_i = 799 then
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column_i <= "0000000000";
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else
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column_i <= column_i + 1;
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end if;
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if column_i >= 658 and column_i <= 753 then -- generate hsync pulse (one clock early, it is delayed later)
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hsync_i <= '0'; -- hsync is low active
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else
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hsync_i <= '1';
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end if;
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HSYNC <= hsync_i; -- delay hsync 1 clock
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end if;
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end process;
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vsync_p: process(CLKPIXEL)
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begin
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if rising_edge(CLKPIXEL) then
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if (hsync_i = '0') and (hsync_i_old = '1') then
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if row_i = 524 then
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row_i <= "0000000000";
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else
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row_i <= row_i + 1;
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end if;
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if row_i = 493 then -- generate vsync pulse
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vsync_i <= '0'; -- vsync is low active
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else
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vsync_i <= '1';
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end if;
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end if;
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hsync_i_old <= hsync_i;
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end if;
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end process;
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COLUMN <= column_i;
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ROW <= row_i;
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VSYNC <= vsync_i;
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end Behavioral;
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