129 lines
4.5 KiB
VHDL
Executable File
129 lines
4.5 KiB
VHDL
Executable File
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:22:46 12/30/2008
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-- Design Name:
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-- Module Name: memory - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity memory is
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Port (
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-- interface to Z80 bus
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DATA_I : in STD_LOGIC_VECTOR (7 downto 0);
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DATA_O : out STD_LOGIC_VECTOR (7 downto 0);
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ADDR_I : in STD_LOGIC_VECTOR (15 downto 0);
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RD_N : in STD_LOGIC;
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WR_N : in STD_LOGIC;
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MREQ_N : in STD_LOGIC;
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CLK : in STD_LOGIC;
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CLKEN : in STD_LOGIC;
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-- interface to video generator
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VID_DATA_O : out STD_LOGIC_VECTOR(7 downto 0);
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VID_ADDR_I : in STD_LOGIC_VECTOR(9 downto 0);
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VID_CLK : in STD_LOGIC);
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end memory;
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architecture Behavioral of memory is
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component monitorrom IS
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port ( clka: IN std_logic;
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addra: IN std_logic_VECTOR(10 downto 0);
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douta: OUT std_logic_VECTOR(7 downto 0);
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ena: in std_logic);
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END component;
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component basic_rom
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port (
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clka : IN std_logic;
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addra : IN std_logic_VECTOR(12 downto 0);
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douta : OUT std_logic_VECTOR(7 downto 0);
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ena : in std_logic);
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end component;
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component ram2kx8 IS
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port ( clka: IN std_logic;
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dina: IN std_logic_VECTOR(7 downto 0);
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addra: IN std_logic_VECTOR(10 downto 0);
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wea: IN std_logic_VECTOR(0 downto 0);
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douta: OUT std_logic_VECTOR(7 downto 0);
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ena: in std_logic;
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clkb: IN std_logic;
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dinb: IN std_logic_VECTOR(7 downto 0);
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addrb: IN std_logic_VECTOR(10 downto 0);
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web: IN std_logic_VECTOR(0 downto 0);
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doutb: OUT std_logic_VECTOR(7 downto 0));
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END component;
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signal monitorrom_data, basicrom_data, ram2kx8_1_dout, ram2kx8_2_dout, ram2kx8_1_doutb: std_logic_vector(7 downto 0);
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signal ram2kx8_1_addrb : std_logic_vector(10 downto 0);
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signal ram2kx8_1_we, ram2kx8_2_we: std_logic_vector(0 downto 0);
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begin
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monitorrom_inst: monitorrom port map( clka => CLK,
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addra => ADDR_I(10 downto 0),
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douta => monitorrom_data,
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ena => CLKEN);
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basicrom_inst : basic_rom port map (
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clka => CLK,
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addra => ADDR_I(12 downto 0),
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douta => basicrom_data,
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ena => CLKEN);
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ram2kx8_1_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00001") and (MREQ_N = '0') else '0';
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ram2kx8_2_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00010") and (MREQ_N = '0') else '0';
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ram2kx8_1_addrb <= '0' & VID_ADDR_I;
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ram2kx8_inst_1: ram2kx8 port map( clka => CLK,
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dina => DATA_I,
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addra => ADDR_I(10 downto 0),
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wea => ram2kx8_1_we,
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douta => ram2kx8_1_dout,
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ena => CLKEN,
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clkb => VID_CLK,
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dinb => "00000000",
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addrb => ram2kx8_1_addrb,
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web => "0",
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doutb => ram2kx8_1_doutb);
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ram2kx8_inst_2: ram2kx8 port map( clka => CLK,
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dina => DATA_I,
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addra => ADDR_I(10 downto 0),
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wea => ram2kx8_2_we,
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douta => ram2kx8_2_dout,
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ena => CLKEN,
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clkb => VID_CLK,
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dinb => "00000000",
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addrb => "00000000000",
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web => "0",
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doutb => open);
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DATA_O <= monitorrom_data when ADDR_I(15 downto 11) = "00000" else
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ram2kx8_1_dout when ADDR_I(15 downto 11) = "00001" else
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ram2kx8_2_dout when ADDR_I(15 downto 11) = "00010" else
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basicrom_data when ADDR_I(15 downto 13) = "111" else
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"XXXXXXXX";
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VID_DATA_O <= ram2kx8_1_doutb;
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end Behavioral;
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