50 lines
896 B
VHDL
Executable File
50 lines
896 B
VHDL
Executable File
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity dcm_in50 is
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port (
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CLKIN_IN : in std_logic;
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RST_IN : in std_logic;
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CLKFX_OUT : out std_logic;
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CLKIN_IBUFG_OUT : out std_logic;
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CLK0_OUT : out std_logic;
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LOCKED_OUT : out std_logic);
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end dcm_in50;
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architecture Behavioral of dcm_in50 is
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begin -- Behavioral
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LOCKED_OUT <= '1';
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CLKIN_IBUFG_OUT <= CLKIN_IN;
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process
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begin
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wait until CLKIN_IN = '1';
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while true loop
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CLK0_OUT <= '1';
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wait for 20 ns;
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CLK0_OUT <= '0';
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wait for 20 ns;
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end loop;
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end process;
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process
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begin
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wait until CLKIN_IN = '1';
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while true loop
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CLKFX_OUT <= '1';
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wait for 31.25 ns;
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CLKFX_OUT <= '0';
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wait for 31.25 ns;
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end loop;
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end process;
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end Behavioral;
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