116 lines
4.6 KiB
VHDL
Executable File
116 lines
4.6 KiB
VHDL
Executable File
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-- This file is owned and controlled by Xilinx and must be used --
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-- solely for design, simulation, implementation and creation of --
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-- design files limited to Xilinx devices or technologies. Use --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- and immediately terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support --
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-- appliances, devices, or systems. Use in such applications are --
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-- expressly prohibited. --
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-- --
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-- (c) Copyright 1995-2007 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file distram16x8.vhd when simulating
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-- the core, distram16x8. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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Library XilinxCoreLib;
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-- synthesis translate_on
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ENTITY distram16x8 IS
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port (
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a: IN std_logic_VECTOR(3 downto 0);
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d: IN std_logic_VECTOR(7 downto 0);
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dpra: IN std_logic_VECTOR(3 downto 0);
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clk: IN std_logic;
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we: IN std_logic;
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spo: OUT std_logic_VECTOR(7 downto 0);
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dpo: OUT std_logic_VECTOR(7 downto 0));
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END distram16x8;
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ARCHITECTURE distram16x8_a OF distram16x8 IS
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-- synthesis translate_off
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component wrapped_distram16x8
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port (
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a: IN std_logic_VECTOR(3 downto 0);
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d: IN std_logic_VECTOR(7 downto 0);
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dpra: IN std_logic_VECTOR(3 downto 0);
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clk: IN std_logic;
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we: IN std_logic;
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spo: OUT std_logic_VECTOR(7 downto 0);
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dpo: OUT std_logic_VECTOR(7 downto 0));
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end component;
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-- Configuration specification
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for all : wrapped_distram16x8 use entity XilinxCoreLib.dist_mem_gen_v3_3(behavioral)
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generic map(
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c_has_clk => 1,
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c_has_qdpo_clk => 0,
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c_has_qdpo_ce => 0,
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c_has_d => 1,
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c_has_spo => 1,
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c_read_mif => 0,
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c_has_qspo => 0,
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c_width => 8,
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c_reg_a_d_inputs => 0,
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c_has_we => 1,
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c_pipeline_stages => 0,
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c_has_qdpo_rst => 0,
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c_reg_dpra_input => 0,
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c_qualify_we => 0,
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c_sync_enable => 1,
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c_depth => 16,
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c_has_qspo_srst => 0,
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c_has_qdpo_srst => 0,
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c_has_dpra => 1,
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c_qce_joined => 0,
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c_mem_type => 2,
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c_has_i_ce => 0,
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c_has_dpo => 1,
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c_mem_init_file => "no_coe_file_loaded",
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c_default_data => "0",
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c_has_spra => 0,
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c_has_qspo_ce => 0,
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c_addr_width => 4,
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c_has_qdpo => 0,
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c_has_qspo_rst => 0);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_distram16x8
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port map (
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a => a,
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d => d,
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dpra => dpra,
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clk => clk,
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we => we,
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spo => spo,
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dpo => dpo);
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-- synthesis translate_on
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END distram16x8_a;
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