64 lines
1.7 KiB
Plaintext
Executable File
64 lines
1.7 KiB
Plaintext
Executable File
##############################################################
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#
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# Xilinx Core Generator version J.40
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# Date: Wed Dec 31 13:10:21 2008
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc3s700an
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SET devicefamily = spartan3a
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = False
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.3
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# END Select
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# BEGIN Parameters
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CSET ce_overrides=ce_overrides_sync_controls
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CSET coefficient_file=no_coe_file_loaded
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CSET common_output_ce=false
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CSET common_output_clk=false
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CSET component_name=distram16x8
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CSET data_width=8
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CSET default_data=0
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CSET default_data_radix=16
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CSET depth=16
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CSET dual_port_address=non_registered
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CSET dual_port_output_clock_enable=false
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CSET input_clock_enable=false
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CSET input_options=non_registered
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CSET memory_type=dual_port_ram
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CSET output_options=non_registered
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CSET pipeline_stages=0
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CSET qualify_we_with_i_ce=false
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CSET reset_qdpo=false
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CSET reset_qspo=false
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CSET single_port_output_clock_enable=false
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CSET sync_reset_qdpo=false
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CSET sync_reset_qspo=false
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# END Parameters
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GENERATE
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# CRC: 79e446fd
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