122 lines
3.9 KiB
VHDL
Executable File
122 lines
3.9 KiB
VHDL
Executable File
-------------------------------------------------------------------------------
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-- Title : NASCOM 2 video generator for VGA monitors
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-- Project :
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-------------------------------------------------------------------------------
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-- File : video.vhd
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-- Author : U-MATTHIAS-THINKP\Matthias <Matthias@matthias-thinkp>
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-- Company :
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-- Created : 2009-01-03
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-- Last update: 2009-01-03
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-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2009
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009-01-03 1.0 Matthias Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity video is
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port (
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CLK : in std_logic; -- Should be 25.175 MHz
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DATA_I : in std_logic_vector(7 downto 0); -- Data from video ram
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ADDR_O : out std_logic_vector(9 downto 0); -- Addr to video ram
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RED, GREEN, BLUE : out std_logic_vector(3 downto 0); -- VGA output to DAC
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VSYNC, HSYNC : out std_logic); -- VGA sync output
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end video;
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architecture Behavioral of video is
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component syncgen
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port (
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CLKPIXEL : in STD_LOGIC;
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VSYNC : out STD_LOGIC;
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HSYNC : out STD_LOGIC;
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COLUMN : out STD_LOGIC_VECTOR (9 downto 0);
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ROW : out STD_LOGIC_VECTOR (9 downto 0));
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end component;
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component videogen
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port (
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ROW : in STD_LOGIC_VECTOR (9 downto 0);
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COLUMN : in STD_LOGIC_VECTOR (9 downto 0);
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CLK : in STD_LOGIC;
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RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0);
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VRAM_ADDR_O : out STD_LOGIC_VECTOR(9 downto 0);
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VRAM_DATA_I : in STD_LOGIC_VECTOR(7 downto 0));
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end component;
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attribute iob : string; -- pull flip-flop into IOB
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signal vsync_int, hsync_int : std_logic := '1'; -- vga sync from syncgen
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signal column, row : std_logic_vector(9 downto 0); -- screen position from syncgen
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signal red_out, green_out, blue_out : std_logic_vector(3 downto 0);
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signal vram_addr_out : std_logic_vector(9 downto 0);
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signal vsync_d1, vsync_d2, vsync_d3, vsync_d4, hsync_d1, hsync_d2, hsync_d3, hsync_d4 : std_logic := '1'; -- delay sync signals by videogen latency
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attribute iob of VSYNC, HSYNC : signal is "TRUE";
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attribute iob of RED, GREEN, BLUE : signal is "TRUE";
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begin -- Behavioral
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syncgen_inst : syncgen port map (
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CLKPIXEL => CLK,
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VSYNC => vsync_int,
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HSYNC => hsync_int,
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COLUMN => column,
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ROW => row);
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videogen_inst : videogen port map (
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ROW => row,
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COLUMN => column,
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CLK => CLK,
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RED => red_out,
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GREEN => green_out,
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BLUE => blue_out,
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VRAM_ADDR_O => vram_addr_out,
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VRAM_DATA_I => DATA_I);
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ADDR_O <= vram_addr_out;
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-- purpose: output register for video data
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-- type : sequential
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-- inputs : CLK, red_out, blue_out, green_out
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-- outputs: RED, BLUE, GREEN
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viddataff: process (CLK)
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begin -- process viddataff
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if rising_edge(CLK) then -- rising clock edge
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RED <= red_out;
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GREEN <= green_out;
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BLUE <= blue_out;
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end if;
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end process viddataff;
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-- purpose: delay sync signals by 3+1 cycles
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-- type : sequential
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-- inputs : CLK, vsync_int, hsync_int
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-- outputs: VSYNC, HSYNC
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syncdelay: process (CLK)
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begin -- process
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if rising_edge(CLK) then
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vsync_d1 <= vsync_int;
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vsync_d2 <= vsync_d1;
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vsync_d3 <= vsync_d2;
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vsync_d4 <= vsync_d3;
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VSYNC <= vsync_d4;
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hsync_d1 <= hsync_int;
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hsync_d2 <= hsync_d1;
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hsync_d3 <= hsync_d2;
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hsync_d4 <= hsync_d3;
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HSYNC <= hsync_d4;
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end if;
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end process;
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end Behavioral;
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