133 lines
3.7 KiB
VHDL
Executable File
133 lines
3.7 KiB
VHDL
Executable File
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:39:57 12/11/2008
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-- Design Name:
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-- Module Name: adrgen - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity videogen is
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Port ( ROW : in STD_LOGIC_VECTOR (9 downto 0);
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COLUMN : in STD_LOGIC_VECTOR (9 downto 0);
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CLK : in STD_LOGIC;
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RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0);
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VRAM_ADDR_O : out STD_LOGIC_VECTOR(9 downto 0);
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VRAM_DATA_I : in STD_LOGIC_VECTOR(7 downto 0)
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);
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end videogen;
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architecture Behavioral of videogen is
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component charrom IS
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port (
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clka: IN std_logic;
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addra: IN std_logic_VECTOR(10 downto 0);
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douta: OUT std_logic_VECTOR(7 downto 0));
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END component;
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signal chrx_i: std_logic_vector(2 downto 0) := "000"; -- h pos in char
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signal chry_i: std_logic_vector(3 downto 0) := "0000"; -- v pos in char
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signal scradrx_i: std_logic_vector(6 downto 0) := "0001010"; -- adr in ram line
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signal scradry_i: std_logic_vector(11 downto 0) := X"3C0"; -- line ofs
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-- in ram
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signal oe_i, oe_d1, oe_d2, oe_d3, oe_o: std_logic := '0'; -- output enable
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-- delay ff chain
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signal charrom_addr : std_logic_vector(10 downto 0);
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signal charrom_data : std_logic_vector(7 downto 0);
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signal out_i : std_logic;
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begin
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adrgen: process (CLK)
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begin
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if rising_edge(CLK) then
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chrx_i <= COLUMN(2 downto 0);
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chry_i <= ROW(3 downto 0);
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if (COLUMN < 384) and (ROW < 256) then -- nascom 48x16 characters mode
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oe_i <= '1';
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if (chrx_i = "111") and (COLUMN(2 downto 0) = "000") then
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if scradrx_i = 57 then
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scradrx_i <= "0001010";
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else
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scradrx_i <= scradrx_i + 1;
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end if;
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end if;
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else
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oe_i <= '0';
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end if;
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if ROW < 256 then
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if (not (chry_i = "0000")) and (ROW(3 downto 0) = "0000") then
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if scradry_i = 960 then
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scradry_i <= X"000";
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else
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scradry_i <= scradry_i + 64;
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end if;
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end if;
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end if;
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end if;
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end process;
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VRAM_ADDR_O <= scradry_i(9 downto 0) + scradrx_i;
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charrom_addr(10 downto 4) <= VRAM_DATA_I(6 downto 0);
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charrom_addr(3 downto 0) <= chry_i;
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charrom_inst: charrom port map( clka => CLK,
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addra => charrom_addr,
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douta => charrom_data);
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vgen: process (CLK)
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variable bitmap: std_logic_vector(7 downto 0) := "00000000";
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begin
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if rising_edge(CLK) then
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if chrx_i = 3 then
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bitmap := charrom_data;
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end if;
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out_i <= bitmap(conv_integer(2 - chrx_i));
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end if;
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end process;
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oe_delay: process (CLK)
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begin
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if rising_edge(CLK) then
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oe_d1 <= oe_i;
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oe_d2 <= oe_d1;
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oe_d3 <= oe_d2;
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oe_o <= oe_d3;
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end if;
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end process;
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RED <= (others => out_i) when oe_o = '1' else "0000";
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GREEN <= (others => out_i) when oe_o = '1' else "0000";
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BLUE <= (others => out_i) when oe_o = '1' else "0000";
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--CHRX <= chrx_i;
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--CHRY <= chry_i;
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--SCRADR <= scradrx_i + scradry_i;
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--OE <= oe_i;
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end Behavioral;
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