Improve some capacitors; Add 3V3 indicator LED
Chose some more sensible caps for the higher-value decoupling ones to actually reach the capacitance requested in the data sheet. Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
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@@ -71,7 +71,7 @@
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# This rule handles diameter minimum and maximum for ALL holes.
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# This rule handles diameter minimum and maximum for ALL holes.
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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(rule "Hole diameter"
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(rule "Hole diameter"
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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(constraint hole_size (min 0.3mm) (max 6.3mm))
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)
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)
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(rule "Hole (NPTH) diameter"
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(rule "Hole (NPTH) diameter"
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@@ -101,10 +101,10 @@
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(constraint hole_to_hole (min 0.5mm))
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(constraint hole_to_hole (min 0.5mm))
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)
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)
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(rule "Clearance: via to via (perimeter), different nets"
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(rule "Clearance: via to via (perimeter), different nets"
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(layer outer)
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(layer outer)
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(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
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(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
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(constraint hole_to_hole (min 0.2mm))
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(constraint hole_to_hole (min 0.2mm))
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)
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)
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(rule "Clearance: hole to hole (perimeter), same net"
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(rule "Clearance: hole to hole (perimeter), same net"
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@@ -1,6 +1,6 @@
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{
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{
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"board": {
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"board": {
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"active_layer": 5,
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"active_layer": 0,
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"active_layer_preset": "",
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"active_layer_preset": "",
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"auto_track_width": true,
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_netclasses": [],
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@@ -450,7 +450,7 @@
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"no_connect_dangling": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"pin_to_pin": "error",
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"power_pin_not_driven": "error",
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"power_pin_not_driven": "error",
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"same_local_global_label": "warning",
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"same_local_global_label": "warning",
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"similar_label_and_power": "warning",
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"similar_label_and_power": "warning",
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