- Created project
- 7seg controller and Lauflicht
This commit is contained in:
19
.gitignore
vendored
Executable file
19
.gitignore
vendored
Executable file
@@ -0,0 +1,19 @@
|
||||
*.bld
|
||||
*.ngc
|
||||
*.xrpt
|
||||
*.xmsgs
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||||
*.log
|
||||
*.exe
|
||||
*.prj
|
||||
*.srp
|
||||
*~
|
||||
netlist.lst
|
||||
toplevel.lso
|
||||
planAhead*.jou
|
||||
planAhead*.log
|
||||
xst/
|
||||
_xmsgs/
|
||||
planahead/
|
||||
isim/
|
||||
xlnx_auto_0_xdb/
|
||||
vga?*.bmp
|
||||
150
Makefile
Executable file
150
Makefile
Executable file
@@ -0,0 +1,150 @@
|
||||
COMMON_INFILES=src/toplevel.vhd src/sseg_ctrl.vhd
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||||
SYN_INFILES=
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||||
PSMFILES=
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||||
CORES=
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||||
PRJNAME=willi_board
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||||
NGCFILE=$(PRJNAME).ngc
|
||||
XSTFILE=$(PRJNAME).xst
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||||
XCF=constr/$(PRJNAME).xcf
|
||||
UCF=constr/$(PRJNAME).ucf
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||||
PCFFILE=$(PRJNAME).pcf
|
||||
NGDFILE=$(PRJNAME).ngd
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||||
NCDFILE=$(PRJNAME).ncd
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||||
NCDFILE_R=$(PRJNAME)_routed.ncd
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||||
BITFILE=$(PRJNAME).bit
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||||
TWRFILE=$(PRJNAME).twr
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||||
TWXFILE=$(PRJNAME).twx
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||||
PRJFILE=$(PRJNAME).prj
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||||
PART=xc3s250e-cp132-4
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||||
XSTOPTS="-ifn $(PRJFILE) \
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||||
-ifmt mixed \
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||||
-top toplevel \
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||||
-ofn $(NGCFILE) \
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||||
-ofmt NGC \
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||||
-p $(PART) \
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||||
-opt_mode Speed \
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||||
-opt_level 1 \
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||||
-fsm_encoding auto \
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||||
-sd coregen/ \
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||||
-read_cores yes \
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||||
-rtlview no \
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||||
-iob auto \
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||||
-keep_hierarchy soft \
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||||
$(addprefix -uc ,$(XCF))"
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||||
NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
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||||
MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on -xe n
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||||
PAROPTS=-ol high -xe n
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||||
BITGENOPTS=
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||||
TRACEOPTS=-v -u 10
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||||
|
||||
SIM_INFILES=src/sim_bmppack.vhd
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||||
SIM_INFILES_VLOG=
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||||
VLOGCOMPOPTS=
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||||
VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental
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||||
FUSEOPTS=-L ieee_proposed=isim/ieee_proposed
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||||
|
||||
SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
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||||
SIMALLFILES=$(SIM_INFILES) $(COMMON_INFILES)
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||||
SIMALLFILESXDB=isim/ieee_proposed/std_logic_1164_additions.vdb \
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||||
$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
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||||
$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
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||||
CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
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||||
CORESNGC=$(addprefix coregen/,$(addsuffix .ngc,$(CORES)))
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||||
|
||||
XILPATH=
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||||
|
||||
COREGEN=$(XILPATH)coregen
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||||
XST=$(XILPATH)xst
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||||
NGDBUILD=$(XILPATH)ngdbuild
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||||
MAP=$(XILPATH)map
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||||
PAR=$(XILPATH)par
|
||||
BITGEN=$(XILPATH)bitgen
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||||
TRCE=$(XILPATH)trce
|
||||
VHPCOMP=$(XILPATH)vhpcomp
|
||||
VLOGCOMP=$(XILPATH)vlogcomp
|
||||
FUSE=$(XILPATH)fuse
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||||
|
||||
.SECONDARY:
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||||
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||||
all: $(BITFILE) #firmware/fw.elf
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||||
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||||
synth: $(NGCFILE)
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||||
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||||
impl: $(NCDFILE_R)
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||||
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||||
timing: $(TWRFILE)
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||||
|
||||
#firmware/fw.elf:
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# cd firmware && make fw.elf
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||||
#%.vhd: %.psm
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||||
# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
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||||
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||||
#src/wb_interconnect.vhd: src/wishbone.defines
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||||
# cd src && ../tools/wishbone.pl -nogui wishbone.defines
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||||
#
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||||
coregen/%.vhd coregen/%.ncd: coregen/%.xco coregen/coregen.cgp
|
||||
$(COREGEN) -p coregen/coregen.cgp -b $< -r
|
||||
|
||||
$(PRJFILE): Makefile
|
||||
rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done
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||||
|
||||
$(XSTFILE): Makefile
|
||||
rm -f $@; echo "run $(XSTOPTS)" > $@
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||||
|
||||
planahead_postsynth.tcl: Makefile
|
||||
rm -f $@; echo -e "create_project -force -part $(PART) postsynth planahead\n\
|
||||
set_property design_mode GateLvl [current_fileset]\n\
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||||
import_files $(NGCFILE) $(CORESNGC)\n\
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||||
import_files -fileset constrs_1 $(UCF)" > $@
|
||||
|
||||
planahead_postimpl.tcl: Makefile
|
||||
rm -f $@; echo -e "create_project -force -part $(PART) postimpl planahead\n\
|
||||
set_property design_mode GateLvl [current_fileset]\n\
|
||||
add_files $(NGCFILE) $(CORESNGC)\n\
|
||||
import_files -fileset constrs_1 $(UCF)\n\
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||||
import_as_run -run impl_1 -twx $(TWXFILE) $(NCDFILE_R)" > $@
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||||
|
||||
planahead_postsynth: planahead_postsynth.tcl $(NGCFILE) $(UCF) $(CORESNGC)
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||||
planAhead -source planahead_postsynth.tcl
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||||
|
||||
planahead_postimpl: planahead_postimpl.tcl $(NCDFILE) $(UCF) $(NCDFILE_R) $(TWXFILE) $(CORESNGC)
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||||
planAhead -source planahead_postimpl.tcl
|
||||
|
||||
$(NGCFILE): $(SYNALLFILES) $(PRJFILE) $(XSTFILE) $(XCF) $(CORESNGC)
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||||
$(XST) -ifn $(XSTFILE)
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||||
|
||||
$(NGDFILE): $(NGCFILE) $(UCF) $(CORESNGC)
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||||
$(NGDBUILD) $(NGDOPTS) $(NGCFILE) $(NGDFILE)
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||||
|
||||
$(PCFFILE) $(NCDFILE): $(NGDFILE)
|
||||
$(MAP) $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
|
||||
|
||||
$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
|
||||
$(PAR) -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
|
||||
|
||||
$(BITFILE): $(NCDFILE_R) $(PCFFILE)
|
||||
$(BITGEN) -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
|
||||
|
||||
$(TWRFILE) $(TWXFILE): $(NCDFILE_R) $(PCFFILE)
|
||||
$(TRCE) $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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||||
|
||||
isim/ieee_proposed/std_logic_1164_additions.vdb: tools/std_logic_1164_additions.vhdl
|
||||
$(VHPCOMP) --work ieee_proposed=isim/ieee_proposed $< $(VHPCOMPOPTS)
|
||||
|
||||
isim/work/%.vdb: src/%.vhd
|
||||
$(VHPCOMP) $< $(VHPCOMPOPTS)
|
||||
|
||||
isim/work/%.vdb: tb/%.vhd
|
||||
$(VHPCOMP) $< $(VHPCOMPOPTS)
|
||||
|
||||
isim/work/%.vdb: coregen/%.vhd
|
||||
$(VHPCOMP) $< $(VHPCOMPOPTS)
|
||||
|
||||
%.exe: $(SIMALLFILESXDB) $(CORESVDB) isim/work/%.vdb
|
||||
$(FUSE) work.$(@:.exe=) -o $@ $(FUSEOPTS)
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||||
|
||||
clean:
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||||
rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB)
|
||||
|
||||
.PSEUDO=all synth impl timing clean planahead_postsynth planahead_postimpl
|
||||
27
constr/willi_board.ucf
Normal file
27
constr/willi_board.ucf
Normal file
@@ -0,0 +1,27 @@
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# Locations and I/O defs
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NET "CLKIN" LOC = "B8" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50" ;
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||||
NET "LED<0>" LOC = "M5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<1>" LOC = "M11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<2>" LOC = "P7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<3>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<4>" LOC = "N5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<5>" LOC = "N4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<6>" LOC = "P4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LED<7>" LOC = "G1" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
|
||||
NET "SSEG_AN<0>" LOC = "F12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "SSEG_AN<1>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "SSEG_AN<2>" LOC = "M13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "SSEG_AN<3>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
|
||||
|
||||
NET "SSEG_CAT<0>" LOC = "L14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<1>" LOC = "H12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<2>" LOC = "N14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<3>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<4>" LOC = "P12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<5>" LOC = "L13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<6>" LOC = "M12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "SSEG_CAT<7>" LOC = "N13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
|
||||
|
||||
# Timing constraints
|
||||
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20.0 ns HIGH 40 %;
|
||||
1
constr/willi_board.xcf
Normal file
1
constr/willi_board.xcf
Normal file
@@ -0,0 +1 @@
|
||||
NET "clkin" PERIOD = 20.0ns HIGH 40%;
|
||||
129
src/sseg_ctrl.vhd
Normal file
129
src/sseg_ctrl.vhd
Normal file
@@ -0,0 +1,129 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : sseg_ctrl
|
||||
-- Project :
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : sseg_ctrl.vhd
|
||||
-- Author : Matthias Blankertz <matthias@blankertz.org>
|
||||
-- Company :
|
||||
-- Created : 2013-03-11
|
||||
-- Last update: 2013-03-11
|
||||
-- Platform :
|
||||
-- Standard : VHDL'93
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2013
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2013-03-11 1.0 matthias Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity sseg_ctrl is
|
||||
generic (
|
||||
dontcare : std_logic := '-'
|
||||
);
|
||||
port (
|
||||
-- global ports
|
||||
clk : in std_logic;
|
||||
|
||||
sseg_an : out std_logic_vector(3 downto 0);
|
||||
sseg_cat : out std_logic_vector(7 downto 0);
|
||||
|
||||
din : std_logic_vector(15 downto 0);
|
||||
dp : std_logic_vector(3 downto 0)
|
||||
);
|
||||
end sseg_ctrl;
|
||||
|
||||
architecture Behavioral of sseg_ctrl is
|
||||
type crom_a is array(0 to 15) of std_logic_vector(6 downto 0);
|
||||
|
||||
--
|
||||
-- GFEDCBA
|
||||
constant crom : crom_a := ("0111111", -- 0
|
||||
"0000110", -- 1
|
||||
"1011011", -- 2
|
||||
"1001111", -- 3
|
||||
"1100110", -- 4
|
||||
"1101101", -- 5
|
||||
"1111101", -- 6
|
||||
"0000111", -- 7
|
||||
"1111111", -- 8
|
||||
"1101111", -- 9
|
||||
"1110111", -- a
|
||||
"1111100", -- b
|
||||
"1011000", -- c
|
||||
"1011110", -- d
|
||||
"1111001", -- e
|
||||
"1110001" -- f
|
||||
);
|
||||
|
||||
signal seg_ctr : integer range 0 to 3 := 0;
|
||||
signal ctr_16ms : integer range 0 to 799999 := 0;
|
||||
signal en_16ms : std_logic;
|
||||
signal an_decode : std_logic_vector(3 downto 0);
|
||||
signal crom_adr : std_logic_vector(3 downto 0);
|
||||
signal crom_data : std_logic_vector(6 downto 0);
|
||||
signal dp_int : std_logic;
|
||||
begin
|
||||
|
||||
gen_16ms : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if ctr_16ms = 799999 then
|
||||
en_16ms <= '1';
|
||||
ctr_16ms <= 0;
|
||||
else
|
||||
en_16ms <= '0';
|
||||
ctr_16ms <= ctr_16ms + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_16ms;
|
||||
|
||||
gen_seg_ctr : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if en_16ms = '1' then
|
||||
if seg_ctr = 3 then
|
||||
seg_ctr <= 0;
|
||||
else
|
||||
seg_ctr <= seg_ctr + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_seg_ctr;
|
||||
|
||||
an_decode <= "0001" when seg_ctr = 0 else
|
||||
"0010" when seg_ctr = 1 else
|
||||
"0100" when seg_ctr = 2 else
|
||||
"1000" when seg_ctr = 3 else
|
||||
(others => dontcare);
|
||||
|
||||
crom_adr <= din(3 downto 0) when seg_ctr = 0 else
|
||||
din(7 downto 4) when seg_ctr = 1 else
|
||||
din(11 downto 8) when seg_ctr = 2 else
|
||||
din(15 downto 12) when seg_ctr = 3 else
|
||||
(others => dontcare);
|
||||
|
||||
dp_int <= dp(seg_ctr);
|
||||
|
||||
crom_read : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
crom_data <= crom(to_integer(unsigned(crom_adr)));
|
||||
end if;
|
||||
end process crom_read;
|
||||
|
||||
gen_out : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
sseg_an <= an_decode;
|
||||
sseg_cat <= not dp_int & not crom_data;
|
||||
end if;
|
||||
end process gen_out;
|
||||
|
||||
end Behavioral;
|
||||
98
src/toplevel.vhd
Normal file
98
src/toplevel.vhd
Normal file
@@ -0,0 +1,98 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Title : toplevel
|
||||
-- Project :
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : toplevel.vhd
|
||||
-- Author : Matthias Blankertz <matthias@blankertz.org>
|
||||
-- Company :
|
||||
-- Created : 2013-03-11
|
||||
-- Last update: 2013-03-11
|
||||
-- Platform :
|
||||
-- Standard : VHDL'93
|
||||
-------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2013
|
||||
-------------------------------------------------------------------------------
|
||||
-- Revisions :
|
||||
-- Date Version Author Description
|
||||
-- 2013-03-11 1.0 matthias Created
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity toplevel is
|
||||
generic (
|
||||
dontcare : std_logic := '-'
|
||||
);
|
||||
port (
|
||||
-- global ports
|
||||
clkin : in std_logic;
|
||||
|
||||
led : out std_logic_vector(7 downto 0);
|
||||
|
||||
sseg_an : out std_logic_vector(3 downto 0);
|
||||
sseg_cat : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end toplevel;
|
||||
|
||||
architecture Mixed of toplevel is
|
||||
component sseg_ctrl
|
||||
generic (
|
||||
dontcare : std_logic);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
sseg_an : out std_logic_vector(3 downto 0);
|
||||
sseg_cat : out std_logic_vector(7 downto 0);
|
||||
din : std_logic_vector(15 downto 0);
|
||||
dp : std_logic_vector(3 downto 0));
|
||||
end component;
|
||||
|
||||
signal ctr_1Hz : integer range 0 to 49999999 := 0;
|
||||
signal en_1Hz : std_logic := '0';
|
||||
signal sr : std_logic_vector(7 downto 0) := x"01";
|
||||
|
||||
signal ctr_secs : unsigned(15 downto 0) := to_unsigned(0, 16);
|
||||
|
||||
signal sseg_din : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
gen_1Hz : process(clkin)
|
||||
begin
|
||||
if rising_edge(clkin) then
|
||||
if ctr_1Hz = 49999999 then
|
||||
en_1Hz <= '1';
|
||||
ctr_1Hz <= 0;
|
||||
else
|
||||
en_1Hz <= '0';
|
||||
ctr_1Hz <= ctr_1Hz + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_1Hz;
|
||||
|
||||
gen_sr : process(clkin)
|
||||
begin
|
||||
if rising_edge(clkin) then
|
||||
if en_1Hz = '1' then
|
||||
sr <= sr(6 downto 0) & sr(7);
|
||||
ctr_secs <= ctr_secs + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_sr;
|
||||
|
||||
sseg_din <= std_logic_vector(ctr_secs);
|
||||
|
||||
sseg_ctrl_inst: sseg_ctrl
|
||||
generic map (
|
||||
dontcare => dontcare)
|
||||
port map (
|
||||
clk => clkin,
|
||||
sseg_an => sseg_an,
|
||||
sseg_cat => sseg_cat,
|
||||
din => sseg_din,
|
||||
dp => "0000" --sseg_dp
|
||||
);
|
||||
|
||||
led <= sr;
|
||||
end Mixed;
|
||||
Reference in New Issue
Block a user