Matthias Blankertz 6cd60cf263 - WIP: New cache for CPU ...

- sysClk reduced to 45 MHz

2013-06-19 15:01:32 +02:00

..

bresenham_dp_tb.vhd

- Started implementing rasterizer

2013-03-26 17:24:15 +01:00

mblite_cache_tb.vhd

- WIP: New cache for CPU

2013-06-19 15:01:32 +02:00

rasterizer_l_tb.vhd

- Rasterizer

2013-03-27 20:21:58 +01:00

spi_tb.vhd

- Debugged SPI module

2013-06-08 11:53:27 +02:00

toplevel_tb.vhd

- Debugged SPI module

2013-06-08 11:53:27 +02:00

vga_tb.vhd

- Added double buffering support to vga controller and cpu

2013-03-21 19:05:22 +01:00

wb_ddr_ctrl_tb.vhd

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_wb_sc_fe_tb.vhd

- Some optimization

2013-03-19 20:24:28 +01:00

wb_ddr_ctrl_wb_sc_tb.vhd

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

wb_mem_bridge_tb.vhd

- Replaced cache with simpler wishbone-memory bridge

2013-06-04 23:18:16 +02:00