- Testbench for toplevel
- Added missing files
This commit is contained in:
2
Makefile
2
Makefile
@@ -37,7 +37,7 @@ PAROPTS=-ol high -xe n
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BITGENOPTS=-g LCK_cycle:4
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BITGENOPTS=-g LCK_cycle:4
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TRACEOPTS=-v -u 10
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TRACEOPTS=-v -u 10
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SIM_INFILES=src/sim_bmppack.vhd
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SIM_INFILES=
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SIM_INFILES_VLOG=
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SIM_INFILES_VLOG=
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VLOGCOMPOPTS=
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VLOGCOMPOPTS=
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VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental
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VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental
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@@ -6,7 +6,7 @@
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-- Author : Matthias Blankertz <matthias@blankertz.org>
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-- Author : Matthias Blankertz <matthias@blankertz.org>
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-- Company :
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-- Company :
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-- Created : 2013-03-11
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-- Created : 2013-03-11
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-- Last update: 2013-03-11
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-- Last update: 2013-03-12
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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@@ -112,7 +112,12 @@ begin
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din(15 downto 12) when seg_ctr = 3 else
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din(15 downto 12) when seg_ctr = 3 else
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(others => dontcare);
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(others => dontcare);
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dp_int <= dp(seg_ctr);
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dp_sel : process(clk)
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begin
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if rising_edge(clk) then
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dp_int <= dp(seg_ctr);
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end if;
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end process dp_sel;
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crom_read : process(clk)
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crom_read : process(clk)
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begin
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begin
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88
tb/toplevel_tb.vhd
Normal file
88
tb/toplevel_tb.vhd
Normal file
@@ -0,0 +1,88 @@
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-------------------------------------------------------------------------------
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-- Title : Testbench for design "toplevel"
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-- Project :
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-------------------------------------------------------------------------------
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-- File : toplevel_tb.vhd
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-- Author : Matthias Blankertz <matthias@matthias-tp>
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-- Company :
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-- Created : 2013-03-12
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-- Last update: 2013-03-12
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2013
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-03-12 1.0 matthias Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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entity toplevel_tb is
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end toplevel_tb;
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-------------------------------------------------------------------------------
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architecture testbench of toplevel_tb is
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component toplevel
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generic (
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dontcare : std_logic);
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port (
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clkin : in std_logic;
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led : out std_logic_vector(7 downto 0);
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sseg_an : out std_logic_vector(3 downto 0);
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sseg_cat : out std_logic_vector(7 downto 0));
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end component;
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-- component generics
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constant dontcare : std_logic := '0';
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-- component ports
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signal clkin : std_logic := '0';
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signal led : std_logic_vector(7 downto 0);
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signal sseg_an : std_logic_vector(3 downto 0);
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signal sseg_cat : std_logic_vector(7 downto 0);
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begin -- testbench
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-- component instantiation
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DUT: toplevel
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generic map (
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dontcare => dontcare)
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port map (
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clkin => clkin,
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led => led,
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sseg_an => sseg_an,
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sseg_cat => sseg_cat);
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-- clock generation
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clkin <= not clkin after 10 ns;
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait;
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end process WaveGen_Proc;
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end testbench;
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-------------------------------------------------------------------------------
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configuration toplevel_tb_testbench_cfg of toplevel_tb is
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for testbench
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end for;
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end toplevel_tb_testbench_cfg;
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-------------------------------------------------------------------------------
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1737
tools/std_logic_1164_additions.vhdl
Normal file
1737
tools/std_logic_1164_additions.vhdl
Normal file
File diff suppressed because it is too large
Load Diff
120
toplevel_tb.wcfg
Normal file
120
toplevel_tb.wcfg
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@@ -0,0 +1,120 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="./isim.wdb" id="1" type="auto">
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<top_modules>
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<top_module name="numeric_std" />
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<top_module name="std_logic_1164" />
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<top_module name="textio" />
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<top_module name="toplevel_tb" />
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<top_module name="vcomponents" />
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<top_module name="vital_primitives" />
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<top_module name="vital_timing" />
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<top_module name="vpkg" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<WVObjectSize size="12" />
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<wvobject fp_name="/toplevel_tb/DUT/clkin" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clkin</obj_property>
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<obj_property name="ObjectShortName">clkin</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/led" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">led[7:0]</obj_property>
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<obj_property name="ObjectShortName">led[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_an" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sseg_an[3:0]</obj_property>
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<obj_property name="ObjectShortName">sseg_an[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_cat" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sseg_cat[7:0]</obj_property>
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<obj_property name="ObjectShortName">sseg_cat[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/clk50" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk50</obj_property>
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<obj_property name="ObjectShortName">clk50</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/clk25" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk25</obj_property>
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<obj_property name="ObjectShortName">clk25</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/ctr_1hz" type="other" db_ref_id="1">
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<obj_property name="ElementShortName">ctr_1hz</obj_property>
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<obj_property name="ObjectShortName">ctr_1hz</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/en_1hz" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">en_1hz</obj_property>
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<obj_property name="ObjectShortName">en_1hz</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sr" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sr[7:0]</obj_property>
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<obj_property name="ObjectShortName">sr[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/ctr_secs" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">ctr_secs[15:0]</obj_property>
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<obj_property name="ObjectShortName">ctr_secs[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_din" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sseg_din[15:0]</obj_property>
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<obj_property name="ObjectShortName">sseg_din[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="group25" type="group">
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<obj_property name="label">sseg_ctrl</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/clk" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sseg_an" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sseg_an[3:0]</obj_property>
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<obj_property name="ObjectShortName">sseg_an[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sseg_cat" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">sseg_cat[7:0]</obj_property>
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<obj_property name="ObjectShortName">sseg_cat[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/din" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">din[15:0]</obj_property>
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<obj_property name="ObjectShortName">din[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/dp" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">dp[3:0]</obj_property>
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<obj_property name="ObjectShortName">dp[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sync" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">sync</obj_property>
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<obj_property name="ObjectShortName">sync</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/seg_ctr" type="other" db_ref_id="1">
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<obj_property name="ElementShortName">seg_ctr</obj_property>
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<obj_property name="ObjectShortName">seg_ctr</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/ctr_4ms" type="other" db_ref_id="1">
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<obj_property name="ElementShortName">ctr_4ms</obj_property>
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<obj_property name="ObjectShortName">ctr_4ms</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/en_4ms" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">en_4ms</obj_property>
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<obj_property name="ObjectShortName">en_4ms</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/an_decode" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">an_decode[3:0]</obj_property>
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<obj_property name="ObjectShortName">an_decode[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/crom_adr" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">crom_adr[3:0]</obj_property>
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<obj_property name="ObjectShortName">crom_adr[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/crom_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">crom_data[6:0]</obj_property>
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<obj_property name="ObjectShortName">crom_data[6:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/dp_int" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">dp_int</obj_property>
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<obj_property name="ObjectShortName">dp_int</obj_property>
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</wvobject>
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</wvobject>
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</wave_config>
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