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- Testbench for toplevel

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- Added missing files
This commit is contained in:
Matthias Blankertz
2013-03-12 19:45:08 +01:00
parent 95ae20c728
commit 8d12981516
5 changed files with 1953 additions and 3 deletions
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2
Makefile
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@@ -37,7 +37,7 @@ PAROPTS=-ol high -xe n
BITGENOPTS=-g LCK_cycle:4
TRACEOPTS=-v -u 10
SIM_INFILES=src/sim_bmppack.vhd
SIM_INFILES=
SIM_INFILES_VLOG=
VLOGCOMPOPTS=
VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental

7
src/sseg_ctrl.vhd
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@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-03-11
-- Last update: 2013-03-11
-- Last update: 2013-03-12
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -112,7 +112,12 @@ begin
din(15 downto 12) when seg_ctr = 3 else
(others => dontcare);
dp_sel : process(clk)
begin
if rising_edge(clk) then
dp_int <= dp(seg_ctr);
end if;
end process dp_sel;
crom_read : process(clk)
begin

88
tb/toplevel_tb.vhd Normal file
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@@ -0,0 +1,88 @@
-------------------------------------------------------------------------------
-- Title : Testbench for design "toplevel"
-- Project :
-------------------------------------------------------------------------------
-- File : toplevel_tb.vhd
-- Author : Matthias Blankertz <matthias@matthias-tp>
-- Company :
-- Created : 2013-03-12
-- Last update: 2013-03-12
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 matthias Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity toplevel_tb is
end toplevel_tb;
-------------------------------------------------------------------------------
architecture testbench of toplevel_tb is
component toplevel
generic (
dontcare : std_logic);
port (
clkin : in std_logic;
led : out std_logic_vector(7 downto 0);
sseg_an : out std_logic_vector(3 downto 0);
sseg_cat : out std_logic_vector(7 downto 0));
end component;
-- component generics
constant dontcare : std_logic := '0';
-- component ports
signal clkin : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal sseg_an : std_logic_vector(3 downto 0);
signal sseg_cat : std_logic_vector(7 downto 0);
begin -- testbench
-- component instantiation
DUT: toplevel
generic map (
dontcare => dontcare)
port map (
clkin => clkin,
led => led,
sseg_an => sseg_an,
sseg_cat => sseg_cat);
-- clock generation
clkin <= not clkin after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait;
end process WaveGen_Proc;
end testbench;
-------------------------------------------------------------------------------
configuration toplevel_tb_testbench_cfg of toplevel_tb is
for testbench
end for;
end toplevel_tb_testbench_cfg;
-------------------------------------------------------------------------------

1737
tools/std_logic_1164_additions.vhdl Normal file
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120
toplevel_tb.wcfg Normal file
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@@ -0,0 +1,120 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="textio" />
<top_module name="toplevel_tb" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="12" />
<wvobject fp_name="/toplevel_tb/DUT/clkin" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clkin</obj_property>
<obj_property name="ObjectShortName">clkin</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/led" type="array" db_ref_id="1">
<obj_property name="ElementShortName">led[7:0]</obj_property>
<obj_property name="ObjectShortName">led[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_an" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sseg_an[3:0]</obj_property>
<obj_property name="ObjectShortName">sseg_an[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_cat" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sseg_cat[7:0]</obj_property>
<obj_property name="ObjectShortName">sseg_cat[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/clk50" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk50</obj_property>
<obj_property name="ObjectShortName">clk50</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/clk25" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk25</obj_property>
<obj_property name="ObjectShortName">clk25</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ctr_1hz" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctr_1hz</obj_property>
<obj_property name="ObjectShortName">ctr_1hz</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/en_1hz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">en_1hz</obj_property>
<obj_property name="ObjectShortName">en_1hz</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sr[7:0]</obj_property>
<obj_property name="ObjectShortName">sr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ctr_secs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctr_secs[15:0]</obj_property>
<obj_property name="ObjectShortName">ctr_secs[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sseg_din[15:0]</obj_property>
<obj_property name="ObjectShortName">sseg_din[15:0]</obj_property>
</wvobject>
<wvobject fp_name="group25" type="group">
<obj_property name="label">sseg_ctrl</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sseg_an" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sseg_an[3:0]</obj_property>
<obj_property name="ObjectShortName">sseg_an[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sseg_cat" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sseg_cat[7:0]</obj_property>
<obj_property name="ObjectShortName">sseg_cat[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">din[15:0]</obj_property>
<obj_property name="ObjectShortName">din[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/dp" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dp[3:0]</obj_property>
<obj_property name="ObjectShortName">dp[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/sync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sync</obj_property>
<obj_property name="ObjectShortName">sync</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/seg_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">seg_ctr</obj_property>
<obj_property name="ObjectShortName">seg_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/ctr_4ms" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctr_4ms</obj_property>
<obj_property name="ObjectShortName">ctr_4ms</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/en_4ms" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">en_4ms</obj_property>
<obj_property name="ObjectShortName">en_4ms</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/an_decode" type="array" db_ref_id="1">
<obj_property name="ElementShortName">an_decode[3:0]</obj_property>
<obj_property name="ObjectShortName">an_decode[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/crom_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">crom_adr[3:0]</obj_property>
<obj_property name="ObjectShortName">crom_adr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/crom_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">crom_data[6:0]</obj_property>
<obj_property name="ObjectShortName">crom_data[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/sseg_ctrl_inst/dp_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dp_int</obj_property>
<obj_property name="ObjectShortName">dp_int</obj_property>
</wvobject>
</wvobject>
</wave_config>