matthias/2d_display_engine-new
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- Debugged SPI module

Browse Source 
- Debugged UART
- Firmware support for SPI, UART
- Work on SD/MMC support in firmware
- Debugged mblite core/WB interface
This commit is contained in:
Matthias Blankertz
2013-06-08 11:53:27 +02:00
parent fd4e8df556
commit 0bc4815926
34 changed files with 2326 additions and 675 deletions
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27
.gitignore vendored
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@@ -7,6 +7,28 @@
*.prj
*.srp
*~
*.bgn
*.bit
*.drc
*.map
*.mrp
*.ncd
*.ngd
*.ngm
*.pcf
*.twr
*.twx
*.xst
*.xwbt
*.pad
*.par
*.ptwx
*.unroutes
*.xpi
2d_display_engine_routed_pad.csv
2d_display_engine_routed_pad.txt
*_usage.xml
*_summary.xml
netlist.lst
toplevel.lso
planAhead*.jou
@@ -17,3 +39,8 @@ planahead/
isim/
xlnx_auto_0_xdb/
vga?*.bmp
*_bd.bmm
planahead_*.tcl
*webtalk.html
fuseRelaunch.cmd
isim.wdb

12
Makefile
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@@ -37,6 +37,7 @@ src/mblite_rom_data.vhd src/mblite_rom.vhd src/mblite_wrapper.vhd src/pio.vhd \
src/uart/fifo16x8.vhd src/uart/par2ser.vhd src/uart/pulsegen325.vhd src/uart/readctrl.vhd src/uart/ser2par.vhd \
src/uart/writectrl.vhd src/uart/uart.vhd src/uart/uart_wbc.vhd \
src/ram_16x64.vhd src/wb_mem_bridge.vhd \
src/spi.vhd \
src/toplevel.vhd
MBLITE_INFILES=mblite/config_Pkg.vhd mblite/std_Pkg.vhd mblite/core_Pkg.vhd \
mblite/dsram.vhd mblite/gprf.vhd mblite/fetch.vhd mblite/decode.vhd mblite/execute.vhd mblite/mem.vhd \
@@ -206,6 +207,9 @@ isim/work/intercon_package.vdb isim/work/interconnect.vdb: src/wishbone.vhd
isim/work/vhdl_bl4_dqs_delay.vdb: ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd
$(VHPCOMP) $< $(VHPCOMPOPTS)
isim/work/mblite_rom_data_pkg_mblite_rom.vdb: src/mblite_rom_data.vhd
$(VHPCOMP) $< $(VHPCOMPOPTS)
isim/work/%.vdb: src/%.vhd
$(VHPCOMP) $< $(VHPCOMPOPTS)
@@ -240,13 +244,15 @@ isim/work/toplevel_tb.vdb: isim/work/sim_bmppack.vdb isim/work/toplevel.vdb
isim/work/wb_ddr_ctrl_wb_sc_tb.vdb: isim/work/wb_ddr_ctrl_wb_sc.vdb
isim/work/spi_tb.vdb: isim/work/intercon_package.vdb isim/work/spi.vdb
isim/work/wb_mem_bridge_tb.vdb: isim/work/intercon_package.vdb isim/work/wb_ddr_ctrl_wb_sc.vdb isim/work/wb_mem_bridge.vdb
isim/work/toplevel.vdb: isim/work/mblite_wrapper.vdb isim/work/intercon_package.vdb isim/work/interconnect.vdb isim/work/clk_reset.vdb isim/work/wb_ddr_ctrl.vdb isim/work/vga.vdb isim/work/wb_ram.vdb isim/work/pio.vdb isim/work/uart_wbc.vdb isim/work/wb_mem_bridge.vdb
isim/work/toplevel.vdb: isim/work/mblite_wrapper.vdb isim/work/intercon_package.vdb isim/work/interconnect.vdb isim/work/clk_reset.vdb isim/work/wb_ddr_ctrl.vdb isim/work/vga.vdb isim/work/wb_ram.vdb isim/work/pio.vdb isim/work/uart_wbc.vdb isim/work/wb_mem_bridge.vdb isim/work/spi.vdb
isim/work/mblite_wrapper.vdb: isim/work/intercon_package.vdb isim/work/mblite_rom.vdb isim/mblite/core_wb.vdb
isim/work/mblite_rom.vdb: isim/work/intercon_package.vdb isim/work/mblite_rom_data.vdb
isim/work/mblite_rom.vdb: isim/work/intercon_package.vdb isim/work/mblite_rom_data_pkg_mblite_rom.vdb
isim/mblite/core_wb.vdb: isim/mblite/config_Pkg.vdb isim/mblite/core_Pkg.vdb isim/mblite/std_Pkg.vdb isim/mblite/core_wb_adapter.vdb isim/mblite/core.vdb
@@ -323,3 +329,5 @@ isim/work/uart_wbc.vdb: isim/work/uart.vdb
isim/work/uart.vdb: isim/work/ser2par.vdb isim/work/readctrl.vdb isim/work/fifo16x8.vdb isim/work/pulsegen325.vdb isim/work/par2ser.vdb isim/work/writectrl.vdb
isim/work/wb_mem_bridge.vdb: isim/work/intercon_package.vdb isim/work/ram_16x64.vdb
isim/work/spi.vdb: isim/work/fifo16x8.vdb

2
constr/2d_display_engine.ucf
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@@ -53,7 +53,7 @@ NET "RS232_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
# MicroSD PMOD (in J18)
NET "SD_MISO" LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8;
NET "SD_MISO" LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | PULLUP;
NET "SD_SCK" LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8;
NET "SD_CS" LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8;
NET "SD_MOSI" LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8;

2
constr/vhdl_bl4.ucf
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@@ -372,7 +372,7 @@ NET "ddr_ctrl0/ddr_0/top_0/dqs_int_delay_in*" MAXDELAY = 580 ps;
##############################################################################################################
## Constraint from rst_dqs_div_in PAD to input of LUT delay element.
##############################################################################################################
NET "ddr_ctrl0/ddr_0/top_0/dqs_div_rst" MAXDELAY = 460 ps;
NET "ddr_ctrl0/ddr_0/top_0/dqs_div_rst" MAXDELAY = 484 ps; # Original 460 ps, always fails PAR, 484 works too
##############################################################################################################
## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.

11
coregen/.gitignore vendored Normal file
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@@ -0,0 +1,11 @@
*.asy
*.gise
*.vhd
*.vho
*.xise
*_flist.txt
*.tcl
tmp/
vga_pixeldata_fifo/
wb_ddr_ctrl_wb_from_ddr/
wb_ddr_ctrl_wb_to_ddr/

1
firmware/.gitignore vendored Normal file
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@@ -0,0 +1 @@
*.elf

8
firmware/Makefile
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@@ -1,7 +1,7 @@
C_SRCS=
S_SRCS=test.s
C_SRCS=main.c sd.c spi.c uart.c util.c
S_SRCS=
LDOPTS=-T standalone.ld
COPTS=-ffreestanding -nostdlib -nostdinc
COPTS=-std=gnu99 -O1 -Wall -Wextra -pedantic -ggdb -ffreestanding -nostdlib -mcpu=v7.10.a
ASOPTS=
OBJS=$(addprefix objs/,$(C_SRCS:.c=.o)) $(addprefix objs/,$(S_SRCS:.s=.o))
@@ -10,7 +10,7 @@ fw.elf: standalone.ld $(OBJS) objs/kcrt0.o
mb-gcc $(COPTS) $(LDOPTS) -o fw.elf $(OBJS)
objs/%.o: %.c
mb-gcc $(COPTS) -o $@ $<
mb-gcc $(COPTS) -o $@ -c $<
objs/%.o: %.s
mb-as $(ASOPTS) -o $@ $<

6
firmware/kcrt0.s
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@@ -54,4 +54,8 @@ _start_bss_loop:
_start_bss_done:
# Jump to firmware start
bri main
brlid r15, main
nop
halt:
bri halt

129
firmware/main.c Normal file
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@@ -0,0 +1,129 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#include "util.h"
#include "uart.h"
#include "spi.h"
#include "sd.h"
static unsigned int * const pio = (unsigned int *)0x10000;
void main() {
*pio = 0x000000a5u;
/* uart_writes("Hello, World!\n"); */
/* unsigned foo = 0xdeadbeef; */
/* const char *s = utox(foo); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb('\n'); */
*pio = 0x1u;
unsigned char tmp;
int i;
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
// Set SPI clock to ~400kHz
spi_setclk(63u);
*pio = 0x2u;
sd_por();
// Sleep 1 ms
for(int i = 0;i < 16667;++i) {}
*pio = 0x3u;
// Send CMD0
spi_set_ss(true);
tmp = sd_cmd(0, 0);
spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD0)\n");
return;
}
*pio = 0x4u;
unsigned rsp;
spi_set_ss(true);
tmp = sd_cmd_r7(8, 0x000001AA, &rsp);
spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD8)\n");
return;
}
unsigned char s_tmp = tmp;
*pio = 0x5u;
spi_set_ss(true);
tmp = sd_cmd_r7(58, 0x0, &rsp);
spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (CMD58)\n");
return;
}
const char *s = utox(tmp);
uart_writes("0x");
uart_writes(s);
uart_writeb(' ');
s = utox(rsp);
uart_writes("0x");
uart_writes(s);
uart_writeb('\n');
*pio = 0x6u;
if(s_tmp&0x4) { // Illegal command, not SDCv2
tmp = 0xff;
while(tmp&0x1) {
spi_set_ss(true);
tmp = sd_cmd(55, 0);
tmp = sd_cmd(41, 0);
spi_set_ss(false);
if(tmp&0x80) {
uart_writes("SD timeout (ACMD41)\n");
return;
}
uart_writeb('\n');
if(tmp != 0x1)
return;
}
if(tmp&0x4) { // Illegal command, not SDCv1
uart_writes("MMC\n");
} else {
uart_writes("SDCv1\n");
}
} else {
uart_writes("SDCv2\n");
}
*pio = 0x7u;
/* const char *s = utox(tmp); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb(' '); */
/* s = utox(rsp); */
/* uart_writes("0x"); */
/* uart_writes(s); */
/* uart_writeb('\n'); */
// Echo on uart
char c;
while(1) {
c = uart_readb();
if(c == '\r')
uart_writeb('\n');
uart_writeb(c);
}
}

92
firmware/sd.c Normal file
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@@ -0,0 +1,92 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#include <stdbool.h>
#include "spi.h"
#include "sd.h"
#include "util.h"
bool sd_por() {
// Send '1' for 80 cycles
spi_set_ss(true);
for(int i = 0;i < 10;++i)
spi_xmit(0xff);
spi_set_ss(false);
return true;
}
unsigned char sd_cmd(unsigned char cmd, unsigned param) {
spi_xmit(0x40 | cmd);
spi_xmit(param>>24);
spi_xmit(param>>16);
spi_xmit(param>>8);
spi_xmit(param&0xff);
spi_xmit(cmd==0?0x95:(cmd==41?0xe5:0x01));
unsigned char tmp;
int i = 0;
while(((tmp=spi_xmit(0xff))&0x80) && (i++<=8)) {
}
const char *s = utox(tmp);
uart_writes("0x");
uart_writes(s);
uart_writeb(' ');
return tmp;
}
unsigned char sd_acmd(unsigned char cmd, unsigned param) {
spi_xmit(0x77);
/* spi_xmit(0x00); */
/* spi_xmit(0x00); */
/* spi_xmit(0x00); */
/* spi_xmit(0x00); */
/* spi_xmit(0x95); */
spi_xmit(0x40 | cmd);
spi_xmit(param>>24);
spi_xmit(param>>16);
spi_xmit(param>>8);
spi_xmit(param&0xff);
spi_xmit(0x95);
unsigned char tmp;
int i = 0;
while(((tmp=spi_xmit(0xff))&0x80) && (i++<=8)) {
}
const char *s = utox(tmp);
uart_writes("0x");
uart_writes(s);
uart_writeb(' ');
return tmp;
}
unsigned char sd_cmd_r7(unsigned char cmd, unsigned param, unsigned *resp) {
spi_xmit(0x40 | cmd);
spi_xmit(param>>24);
spi_xmit(param>>16);
spi_xmit(param>>8);
spi_xmit(param&0xff);
spi_xmit(0x95);
unsigned char tmp;
int i = 0;
while(((tmp=spi_xmit(0xff))&0x80) && (i++<=8)) {
}
const char *s = utox(tmp);
uart_writes("0x");
uart_writes(s);
uart_writeb(' ');
if(tmp != 0xff) {
*resp = 0;
for(int i = 0;i < 4;++i) {
*resp <<= 8;
*resp |= spi_xmit(0xff);
}
}
return tmp;
}

13
firmware/sd.h Normal file
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@@ -0,0 +1,13 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#ifndef _SD_H_
#define _SD_H_
#include <stdbool.h>
bool sd_por();
unsigned char sd_cmd(unsigned char cmd, unsigned param);
unsigned char sd_cmd_r7(unsigned char cmd, unsigned param, unsigned *resp);
#endif

50
firmware/spi.c Normal file
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@@ -0,0 +1,50 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#include <stdbool.h>
#include "spi.h"
static volatile unsigned char * const spi_data = (unsigned char *)0x10030;
static volatile unsigned char * const spi_status = (unsigned char *)0x10031;
static volatile unsigned char * const spi_config = (unsigned char *)0x10032;
static volatile unsigned char * const spi_ss = (unsigned char *)0x10033;
static bool _spi_rxempty() {
return ((*spi_status&0x4)==0x4);
}
static bool _spi_txfull() {
return ((*spi_status&0x2)==0x2);
}
static bool _spi_idle() {
return ((*spi_status&0x1)==0x1);
}
void spi_write(unsigned char data) {
while(_spi_txfull()) {}
*spi_data = data;
}
unsigned char spi_read() {
while(_spi_rxempty()) {}
return *spi_data;
}
unsigned char spi_xmit(unsigned char data) {
spi_write(data);
return spi_read();
}
void spi_set_ss(bool active) {
while(!_spi_idle()) {}
if(active)
*spi_ss = 0x0;
else
*spi_ss = 0x1;
}
void spi_setclk(unsigned char div) {
while(!_spi_idle()) {}
*spi_config = div;
}

15
firmware/spi.h Normal file
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@@ -0,0 +1,15 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#ifndef _SPI_H_
#define _SPI_H_
#include <stdbool.h>
void spi_write(unsigned char data);
unsigned char spi_read();
unsigned char spi_xmit(unsigned char data);
void spi_set_ss(bool active);
void spi_setclk(unsigned char div);
#endif

5
firmware/standalone.ld
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@@ -14,7 +14,7 @@ SECTIONS {
}
/* From here on in RAM */
.data 0x1000 : AT ( _datald ) ALIGN(4) {
.data 0x8000 : AT ( _datald ) ALIGN(4) {
_data_start = .;
*(.data)
_data_end = .;
@@ -23,7 +23,8 @@ SECTIONS {
.bss (NOLOAD) : ALIGN(4) {
_bss_start = .;
*(.bss)
. = ALIGN(4);
_bss_end = .;
}
_stack = 0x1800;
_stack = 0x8800;
}

48
firmware/uart.c Normal file
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@@ -0,0 +1,48 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#include <stdbool.h>
#include "uart.h"
static volatile unsigned char *_uart_sreg = (unsigned char *)0x10021;
static volatile unsigned char *_uart_dreg = (unsigned char *)0x10020;
static bool _uart_writefull() {
return ((*_uart_sreg&0x2)==0x2);
}
static bool _uart_readempty() {
return ((*_uart_sreg&0x4)==0x4);
}
void uart_writeb(unsigned char b) {
while(_uart_writefull()) {}
*_uart_dreg = b;
}
void uart_writes(const char *str) {
while(*str)
uart_writeb(*str++);
}
unsigned char uart_readb() {
while(_uart_readempty()) {}
return *_uart_dreg;
}
// Read from uart until a newline is recvd. The recvd line is written into buf
// as a 0-terminated string. If more than max bytes are read, the bytes already
// read are returned in buf and the function returns false.
bool uart_readline(char *buf, int max) {
int i = 0;
while(i < max-1) {
buf[i] = uart_readb();
if(buf[i] == '\n') {
buf[i] = '\0';
return true;
}
++i;
}
buf[i] = '\0';
return false;
}

13
firmware/uart.h Normal file
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@@ -0,0 +1,13 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#ifndef _UART_H_
#define _UART_H_
#include <stdbool.h>
void uart_writeb(unsigned char b);
void uart_writes(const char *str);
unsigned char uart_readb();
bool uart_readline(char *buf, int max);
#endif

17
firmware/util.c Normal file
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@@ -0,0 +1,17 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
static char _str_buf[9];
const char *utox(unsigned int num) {
int i = 7;
_str_buf[8] = '\0';
while(num || (i == 7)) {
_str_buf[i] = (num&0xf)+'0';
if(_str_buf[i] > '9')
_str_buf[i] += 'A'-'9'-1;
--i;
num>>=4;
}
return _str_buf+(i+1);
}

8
firmware/util.h Normal file
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@@ -0,0 +1,8 @@
// Copyright (c) 2013 Matthias Blankertz <matthias@blankertz.org>
#ifndef _UTIL_H_
#define _UTIL_H_
const char *utox(unsigned int num);
#endif

4
mblite/config_Pkg.vhd
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@@ -36,13 +36,13 @@ package config_Pkg is
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 28; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 12; -- Instruction memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 14; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := false; -- Forward memory result in stead of introducing stalls [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)

19
mblite/core_wb_adapter.vhd
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@@ -45,17 +45,17 @@ begin
wb_o.adr_o <= dmem_o.adr_o;
wb_o.sel_o <= dmem_o.sel_o;
wb_o.we_o <= dmem_o.we_o;
dmem_i.dat_i <= wb_i.dat_i;
-- dmem_i.dat_i <= wb_i.dat_i;
dly : process(wb_i.clk_i)
begin
if rising_edge(wb_i.clk_i) then
wb_i_ack_i_dly <= wb_i.ack_i;
end if;
end process dly;
--dly : process(wb_i.clk_i)
--begin
-- if rising_edge(wb_i.clk_i) then
-- wb_i_ack_i_dly <= wb_i.ack_i;
-- end if;
--end process dly;
-- synchronous bus control connections
wb_o.cyc_o <= r_cyc_o or wb_i_ack_i_dly;
wb_o.cyc_o <= r_cyc_o or wb_i.ack_i;
wb_o.stb_o <= r_cyc_o;
-- asynchronous core enable connection
@@ -79,7 +79,7 @@ begin
elsif dmem_o.ena_o = '1' and wb_i.ack_i = '1' then
-- wishbone bus is occuppied
rin_data <= r_data;
rin_cyc_o <= '1';
rin_cyc_o <= r_cyc_o; --'1';
s_wait <= '1';
elsif r_cyc_o = '0' and dmem_o.ena_o = '1' and wb_i.ack_i = '0' then
-- start wishbone cycle
@@ -100,6 +100,7 @@ begin
if rising_edge(wb_i.clk_i) then
r_cyc_o <= rin_cyc_o;
r_data <= rin_data;
dmem_i.dat_i <= wb_i.dat_i;
end if;
end process;

12
mblite_rom.bmm
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@@ -1,6 +1,12 @@
ADDRESS_SPACE mblite_rom RAMB16 [0x00000000:0x00000FFF]
ADDRESS_SPACE mblite_rom RAMB16 [0x00000000:0x00003FFF]
BUS_BLOCK
cpu_inst/mblite_rom_inst/rom1_inst [31:16];
cpu_inst/mblite_rom_inst/rom0_inst [15:0];
cpu_inst/mblite_rom_inst/rom7_inst [31:28];
cpu_inst/mblite_rom_inst/rom6_inst [27:24];
cpu_inst/mblite_rom_inst/rom5_inst [23:20];
cpu_inst/mblite_rom_inst/rom4_inst [19:16];
cpu_inst/mblite_rom_inst/rom3_inst [15:12];
cpu_inst/mblite_rom_inst/rom2_inst [11:8];
cpu_inst/mblite_rom_inst/rom1_inst [7:4];
cpu_inst/mblite_rom_inst/rom0_inst [3:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

197
spi_tb.wcfg Normal file
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@@ -0,0 +1,197 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="intercon_package" />
<top_module name="numeric_std" />
<top_module name="spi_tb" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="36" />
<wvobject fp_name="/spi_tb/DUT/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_i</obj_property>
<obj_property name="ObjectShortName">wbs_i</obj_property>
<wvobject fp_name="/spi_tb/DUT/wbs_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_i.we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.we_i</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_i.adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.adr_i</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_i.cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_i.stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.stb_i</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_o</obj_property>
<obj_property name="ObjectShortName">wbs_o</obj_property>
<wvobject fp_name="/spi_tb/DUT/wbs_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">wbs_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wbs_o.ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_o</obj_property>
<obj_property name="ObjectShortName">wbs_o.ack_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">miso</obj_property>
<obj_property name="ObjectShortName">miso</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mosi</obj_property>
<obj_property name="ObjectShortName">mosi</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/sclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk</obj_property>
<obj_property name="ObjectShortName">sclk</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/ss" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ss</obj_property>
<obj_property name="ObjectShortName">ss</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/clk_divider" type="array" db_ref_id="1">
<obj_property name="ElementShortName">clk_divider[5:0]</obj_property>
<obj_property name="ObjectShortName">clk_divider[5:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/clk_ctr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">clk_ctr[5:0]</obj_property>
<obj_property name="ObjectShortName">clk_ctr[5:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_clk</obj_property>
<obj_property name="ObjectShortName">spi_clk</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_clk_dly" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_clk_dly</obj_property>
<obj_property name="ObjectShortName">spi_clk_dly</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_clk_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_clk_rst</obj_property>
<obj_property name="ObjectShortName">spi_clk_rst</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_clk_inv" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_clk_inv</obj_property>
<obj_property name="ObjectShortName">spi_clk_inv</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/sclk_o_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk_o_en</obj_property>
<obj_property name="ObjectShortName">sclk_o_en</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/sclk_o_d0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk_o_d0</obj_property>
<obj_property name="ObjectShortName">sclk_o_d0</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/sclk_o_d1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk_o_d1</obj_property>
<obj_property name="ObjectShortName">sclk_o_d1</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">spi_state</obj_property>
<obj_property name="ObjectShortName">spi_state</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_idle" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_idle</obj_property>
<obj_property name="ObjectShortName">spi_idle</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/indata_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">indata_pending</obj_property>
<obj_property name="ObjectShortName">indata_pending</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/spi_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">spi_ctr</obj_property>
<obj_property name="ObjectShortName">spi_ctr</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/sreg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sreg[8:0]</obj_property>
<obj_property name="ObjectShortName">sreg[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_rd" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">infifo_rd</obj_property>
<obj_property name="ObjectShortName">infifo_rd</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">infifo_wr</obj_property>
<obj_property name="ObjectShortName">infifo_wr</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">infifo_full</obj_property>
<obj_property name="ObjectShortName">infifo_full</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">infifo_empty</obj_property>
<obj_property name="ObjectShortName">infifo_empty</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">infifo_din[7:0]</obj_property>
<obj_property name="ObjectShortName">infifo_din[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/infifo_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">infifo_dout[7:0]</obj_property>
<obj_property name="ObjectShortName">infifo_dout[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_rd" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_rd</obj_property>
<obj_property name="ObjectShortName">outfifo_rd</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_wr</obj_property>
<obj_property name="ObjectShortName">outfifo_wr</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_full</obj_property>
<obj_property name="ObjectShortName">outfifo_full</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_empty</obj_property>
<obj_property name="ObjectShortName">outfifo_empty</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_din[7:0]</obj_property>
<obj_property name="ObjectShortName">outfifo_din[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/outfifo_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">outfifo_dout[7:0]</obj_property>
<obj_property name="ObjectShortName">outfifo_dout[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/wb_in_cyc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_in_cyc</obj_property>
<obj_property name="ObjectShortName">wb_in_cyc</obj_property>
</wvobject>
<wvobject fp_name="/spi_tb/DUT/ack_o_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o_int</obj_property>
<obj_property name="ObjectShortName">ack_o_int</obj_property>
</wvobject>
</wave_config>

1
src/.gitignore vendored Normal file
View File

@@ -0,0 +1 @@
mblite_rom_data.vhd

545
src/mblite_rom.vhd
View File

@@ -5,7 +5,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-02
-- Last update: 2013-06-03
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -39,7 +39,7 @@ entity mblite_rom is
port (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wbs_i : in mblite_rom_wbs_i_type;
@@ -50,17 +50,20 @@ end entity mblite_rom;
architecture Mixed of mblite_rom is
signal wb_clk : std_logic;
signal ack_o_int : std_logic := '0';
begin
wb_clk <= clka;
wb_ack : process(clka)
begin
if rising_edge(clka) then
wbs_o.ack_o <= wbs_i.stb_i and wbs_i.cyc_i;
ack_o_int <= wbs_i.stb_i and wbs_i.cyc_i;
end if;
end process wb_ack;
wbs_o.ack_o <= ack_o_int and wbs_i.stb_i;
rom0_inst : ramb16_s18_s18
rom0_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom0_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom0_inst_INIT_01,
@@ -128,20 +131,16 @@ begin
INIT_3F => cpu_inst_mblite_rom_inst_rom0_inst_INIT_3F
)
port map (
doa => douta(15 downto 0),
dopa => open,
dia => x"0000",
dipa => "00",
doa => douta(3 downto 0),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(15 downto 0),
dopb => open,
dib => x"0000",
dipb => "00",
dob => wbs_o.dat_o(3 downto 0),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
@@ -149,7 +148,7 @@ begin
clkb => wb_clk
);
rom1_inst : ramb16_s18_s18
rom1_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom1_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom1_inst_INIT_01,
@@ -217,20 +216,16 @@ begin
INIT_3F => cpu_inst_mblite_rom_inst_rom1_inst_INIT_3F
)
port map (
doa => douta(31 downto 16),
dopa => open,
dia => x"0000",
dipa => "00",
doa => douta(7 downto 4),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(31 downto 16),
dopb => open,
dib => x"0000",
dipb => "00",
dob => wbs_o.dat_o(7 downto 4),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
@@ -238,6 +233,514 @@ begin
clkb => wb_clk
);
rom2_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom2_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom2_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom2_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom2_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom2_inst_INIT_3F
)
port map (
doa => douta(11 downto 8),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(11 downto 8),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
rom3_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom3_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom3_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom3_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom3_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom3_inst_INIT_3F
)
port map (
doa => douta(15 downto 12),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(15 downto 12),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
rom4_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom4_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom4_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom4_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom4_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom4_inst_INIT_3F
)
port map (
doa => douta(19 downto 16),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(19 downto 16),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
rom5_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom5_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom5_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom5_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom5_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom5_inst_INIT_3F
)
port map (
doa => douta(23 downto 20),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(23 downto 20),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
rom6_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom6_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom6_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom6_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom6_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom6_inst_INIT_3F
)
port map (
doa => douta(27 downto 24),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(27 downto 24),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
rom7_inst : ramb16_s4_s4
generic map (
INIT_00 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_00,
INIT_01 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_01,
INIT_02 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_02,
INIT_03 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_03,
INIT_04 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_04,
INIT_05 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_05,
INIT_06 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_06,
INIT_07 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_07,
INIT_08 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_08,
INIT_09 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_09,
INIT_0A => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0A,
INIT_0B => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0B,
INIT_0C => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0C,
INIT_0D => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0D,
INIT_0E => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0E,
INIT_0F => cpu_inst_mblite_rom_inst_rom7_inst_INIT_0F,
INIT_10 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_10,
INIT_11 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_11,
INIT_12 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_12,
INIT_13 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_13,
INIT_14 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_14,
INIT_15 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_15,
INIT_16 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_16,
INIT_17 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_17,
INIT_18 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_18,
INIT_19 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_19,
INIT_1A => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1A,
INIT_1B => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1B,
INIT_1C => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1C,
INIT_1D => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1D,
INIT_1E => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1E,
INIT_1F => cpu_inst_mblite_rom_inst_rom7_inst_INIT_1F,
INIT_20 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_20,
INIT_21 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_21,
INIT_22 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_22,
INIT_23 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_23,
INIT_24 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_24,
INIT_25 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_25,
INIT_26 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_26,
INIT_27 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_27,
INIT_28 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_28,
INIT_29 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_29,
INIT_2A => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2A,
INIT_2B => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2B,
INIT_2C => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2C,
INIT_2D => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2D,
INIT_2E => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2E,
INIT_2F => cpu_inst_mblite_rom_inst_rom7_inst_INIT_2F,
INIT_30 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_30,
INIT_31 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_31,
INIT_32 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_32,
INIT_33 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_33,
INIT_34 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_34,
INIT_35 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_35,
INIT_36 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_36,
INIT_37 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_37,
INIT_38 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_38,
INIT_39 => cpu_inst_mblite_rom_inst_rom7_inst_INIT_39,
INIT_3A => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3A,
INIT_3B => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3B,
INIT_3C => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3C,
INIT_3D => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3D,
INIT_3E => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3E,
INIT_3F => cpu_inst_mblite_rom_inst_rom7_inst_INIT_3F
)
port map (
doa => douta(31 downto 28),
dia => "0000",
addra => addra,
wea => '0',
ena => ena,
ssra => '0',
clka => clka,
dob => wbs_o.dat_o(31 downto 28),
dib => "0000",
addrb => wbs_i.adr_i,
web => '0',
enb => '1',
ssrb => '0',
clkb => wb_clk
);
end Mixed;

4
src/mblite_wrapper.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-02
-- Last update: 2013-06-03
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -71,7 +71,7 @@ begin
port map (
clka => clk_i,
ena => mb_imem_o.ena_o,
addra => mb_imem_o.adr_o(11 downto 2),
addra => mb_imem_o.adr_o(13 downto 2),
douta => mb_imem_i.dat_i,
wbs_i => rom_wbs_i,
wbs_o => rom_wbs_o

106
src/spi.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-05
-- Last update: 2013-06-05
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -36,9 +36,16 @@ use work.intercon_package.all;
-- Register map
-- 0 : data in/out register
-- 1 : status register
-- 7..3: reserved
-- 2: RX FIFO empty
-- 1: TX FIFO full
-- 0: idle
-- 2 : config1 register
-- 7..6: reserved
-- 5..0: output clock divider
-- 3 : slave select register
-- 7..1: reserved
-- 0: slave select
entity spi is
generic (
@@ -51,33 +58,38 @@ entity spi is
rst_i : in std_logic;
-- Wishbone slave port
dat_i : in std_logic_vector(7 downto 0);
we_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(1 downto 0);
dat_o : out std_logic_vector(7 downto 0);
ack_o : out std_logic;
wbs_i : in spi_wbs_i_type;
wbs_o : out spi_wbs_o_type;
-- SPI Master
miso : in std_logic;
mosi : out std_logic;
sclk : out std_logic;
ss : out std_logic
ss : out std_logic := '1'
);
end spi;
architecture Behavioral of spi is
constant sclk_obuf_init : std_logic := not clock_pol;
signal spi_clk, spi_clk_dly : std_logic := '0';
signal spi_clk_inv : std_logic;
type spi_states is (S_IDLE, S_XFER_START, S_XFER, S_WAITFALLING, S_WAITINFIFO);
signal spi_state : spi_states := S_IDLE;
constant sclk_obuf_init : bit := to_bit(not clock_pol);
signal clk_divider, clk_ctr : unsigned(5 downto 0) := to_unsigned(0, 6);
signal spi_clk, spi_clk_dly, spi_clk_rst : std_logic := '0';
signal spi_clk_inv : std_logic;
signal sclk_o_en, sclk_o_d0, sclk_o_d1 : std_logic := '0';
type spi_states is (S_IDLE, S_XFER_START1, S_XFER_START2, S_XFER, S_WAITFALLING, S_WAITINFIFO);
signal spi_state : spi_states := S_IDLE;
signal spi_idle, indata_pending : std_logic;
signal spi_ctr : integer range 0 to 7;
signal sreg : std_logic_vector(8 downto 0);
signal infifo_rd, infifo_wr, infifo_full, infifo_empty : std_logic := '0';
signal infifo_din, infifo_dout : std_logic_vector(7 downto 0);
signal outfifo_rd, outfifo_wr, outfifo_full, outfifo_empty : std_logic := '0';
signal outfifo_din, outfifo_dout : std_logic_vector(7 downto 0);
signal wb_in_cyc, ack_o_int : std_logic := '0';
begin
spi_clk_gen : process(clk_i)
begin
@@ -98,13 +110,13 @@ begin
sclk_obuf : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
-- DDR_ALIGNMENT => "C0",
INIT => sclk_obuf_init
)
port map (
Q => sclk,
C0 => spi_clk_dly,
C1 => spi_clk_inv,
C0 => spi_clk_inv,
C1 => spi_clk_dly,
CE => sclk_o_en,
D0 => sclk_o_d0,
D1 => sclk_o_d1,
@@ -118,6 +130,7 @@ begin
spi_sreg : process(clk_i)
begin
if rising_edge(clk_i) then
spi_clk_rst <= '0';
infifo_wr <= '0';
infifo_din <= (others => dontcare);
outfifo_rd <= '0';
@@ -130,13 +143,17 @@ begin
if clock_phase = '0' then
mosi <= outfifo_dout(7);
end if;
spi_state <= S_XFER_START;
spi_clk_rst <= '1';
spi_ctr <= 0;
indata_pending <= '0';
spi_state <= S_XFER_START1;
end if;
when S_XFER_START =>
if spi_clk_dly = '1' and spi_clk = '0' then
when S_XFER_START1 =>
spi_clk_rst <= '1';
spi_state <= S_XFER_START2;
when S_XFER_START2 =>
sclk_o_en <= '1';
spi_state <= S_XFER;
end if;
when S_XFER =>
if ((spi_clk_dly = '0' and spi_clk = '1' and clock_phase = '0') or
(spi_clk_dly = '1' and spi_clk = '0' and clock_phase = '1')) then
@@ -172,14 +189,16 @@ begin
spi_state <= S_WAITFALLING;
end if;
end if;
else
spi_ctr <= spi_ctr + 1;
end if;
elsif (spi_clk_dly = '1' and spi_clk = '0' and clock_phase = '0') then
-- Data out
mosi <= sreg(8);
mosi <= sreg(7);
sreg <= sreg(7 downto 0) & "0";
elsif (spi_clk_dly = '0' and spi_clk = '1' and clock_phase = '1') then
-- Data out
mosi <= sreg(8);
mosi <= sreg(7);
sreg <= sreg(7 downto 0) & "0";
end if;
when S_WAITFALLING =>
@@ -209,6 +228,28 @@ begin
end if;
end process spi_sreg;
infifo : entity work.fifo16x8
port map (
clk => clk_i,
writestb => infifo_wr,
readstb => infifo_rd,
datain => infifo_din,
dataout => infifo_dout,
full => infifo_full,
empty => infifo_empty
);
outfifo : entity work.fifo16x8
port map (
clk => clk_i,
writestb => outfifo_wr,
readstb => outfifo_rd,
datain => outfifo_din,
dataout => outfifo_dout,
full => outfifo_full,
empty => outfifo_empty
);
spi_idle <= '1' when spi_state = S_IDLE and outfifo_empty = '1' else
'0';
@@ -220,16 +261,17 @@ begin
outfifo_din <= (others => dontcare);
if rst_i = '1' then
wbs_o.ack_o <= '0';
ack_o_int <= '0';
wb_in_cyc <= '0';
wbs_o.dat_o <= (others => dontcare);
else
if wb_in_cyc = '1' and wbs_i.stb_i = '0' then
wbs_o.dat_o <= (others => dontcare);
ack_o_int <= '0';
wb_in_cyc <= '0';
elsif wb_in_cyc = '0' and wbs_i.stb_i = '1' and wbs_i.cyc_i = '1' then
wb_in_cyc <= '1';
wbs_o.ack_o <= '1';
ack_o_int <= '1';
if wbs_i.we_i = '0' then
if wbs_i.adr_i = "00" then
@@ -240,7 +282,7 @@ begin
end if;
elsif wbs_i.adr_i = "01" then
-- read status reg
wbs_o.dat_o(7 downto 3) <= (others => dontcare)
wbs_o.dat_o(7 downto 3) <= (others => dontcare);
wbs_o.dat_o(2 downto 0) <= infifo_empty & outfifo_full & spi_idle;
elsif wbs_i.adr_i = "10" then
-- read config reg
@@ -260,11 +302,17 @@ begin
elsif wbs_i.adr_i = "10" then
-- write config reg
clk_divider <= unsigned(wbs_i.dat_i(5 downto 0));
elsif wbs_i.adr_i = "11" then
-- write slave select
if spi_idle = '1' then
ss <= wbs_i.dat_i(0);
end if;
end if;
end if;
end if;
end if;
end if;
end process wb;
wbs_o.ack_o <= (ack_o_int or wbs_i.we_i) and wbs_i.stb_i;
end Behavioral;

28
src/toplevel.vhd
View File

@@ -74,7 +74,12 @@ entity toplevel is
-- RS232
rs232_txd : out std_logic;
rs232_rxd : in std_logic
rs232_rxd : in std_logic;
sd_miso : in std_logic;
sd_mosi : out std_logic;
sd_cs : out std_logic;
sd_sck : out std_logic
);
end toplevel;
@@ -91,6 +96,8 @@ architecture Mixed of toplevel is
signal pio_led_wbs_o : pio_led_wbs_o_type;
signal uart_wbs_i : uart_wbs_i_type;
signal uart_wbs_o : uart_wbs_o_type;
signal spi_sd_wbs_i : spi_wbs_i_type;
signal spi_sd_wbs_o : spi_wbs_o_type;
signal mem_bridge_wbs_o : mem_bridge_wbs_o_type;
signal mem_bridge_wbs_i : mem_bridge_wbs_i_type;
@@ -231,6 +238,9 @@ pio_led: entity work.pio
);
uart_inst: entity work.uart_wbc
generic map (
dontcare => dontcare
)
port map (
CLK_I => sysClk,
RST_I => sysRst,
@@ -246,6 +256,20 @@ uart_inst: entity work.uart_wbc
SERIALOUT => rs232_txd
);
spi_sd_inst : entity work.spi
port map (
clk_i => sysClk,
rst_i => sysRst,
wbs_i => spi_sd_wbs_i,
wbs_o => spi_sd_wbs_o,
miso => sd_miso,
mosi => sd_mosi,
ss => sd_cs,
sclk => sd_sck
);
mem_bridge_inst : entity work.wb_mem_bridge
port map (
clk_i => sysClk,
@@ -291,6 +315,8 @@ intercon_1: entity work.interconnect
pio_led_wbs_i => pio_led_wbs_i,
uart_wbs_o => uart_wbs_o,
uart_wbs_i => uart_wbs_i,
spi_sd_wbs_o => spi_sd_wbs_o,
spi_sd_wbs_i => spi_sd_wbs_i,
clk => sysClk,
reset => sysRst);

2
src/uart/readctrl.vhd
View File

@@ -59,7 +59,7 @@ begin
sr8 <= sr8(6 downto 0) & start;
sr16 <= sr16(14 downto 0) & ((sr8(7) or sr16(15)) and (not dly10_sr10(8)));
if (sr8(7) or sr16(15)) = '1' then
if (sr8(7) or sr16(15) or not running) = '1' then
dly10_sr10 <= dly10_sr10(8 downto 0) & sr8(7);
end if;
end if;

14
src/uart/uart_wbc.vhd
View File

@@ -30,6 +30,9 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- 57600 baud with 50 MHz clk
-- 115200 baud with 100 MHz clk
entity uart_wbc is
generic (
dontcare : std_logic := '-'
);
Port (
-- Wishbone slave
DAT_O : out STD_LOGIC_VECTOR (7 downto 0);
@@ -67,7 +70,7 @@ signal uart_dataout, uart_datain: std_logic_vector(7 downto 0);
signal uart_readfifostb, uart_writefifostb: std_logic := '0';
signal uart_readfull, uart_readempty, uart_writefull, uart_writeempty: std_logic;
signal in_cyc : std_logic := '0';
signal in_cyc, ACK_O_int : std_logic := '0';
begin
uart_inst: uart
port map (
@@ -93,7 +96,7 @@ begin
else
if STB_I = '0' then
in_cyc <= '0';
ACK_O <= '0';
ACK_O_int <= '0';
elsif STB_I = '1' and in_cyc = '0' then
if ADR_I(0) = '0' and WE_I = '1' then
uart_writefifostb <= '1';
@@ -101,15 +104,18 @@ begin
uart_readfifostb <= '1';
DAT_O <= uart_dataout;
elsif ADR_I(0) = '1' then
DAT_O <= "----" & uart_readfull & uart_readempty & uart_writefull & uart_writeempty;
DAT_O(7 downto 4) <= (others => dontcare);
DAT_O(3 downto 0) <= uart_readfull & uart_readempty & uart_writefull & uart_writeempty;
end if;
in_cyc <= '1';
ACK_O <= '1';
ACK_O_int <= '1';
end if;
end if;
end if;
end process wb;
ACK_O <= ACK_O_int and STB_I;
uart_datain <= DAT_I;
SERIALOUT <= serialout_o;
end Behavioral;

6
src/wb_ram.vhd
View File

@@ -49,6 +49,8 @@ architecture Behavioral of wb_ram is
signal di3, di2, di1, di0 : std_logic_vector(7 downto 0);
signal bwe : std_logic_vector(3 downto 0) := (others => '0');
signal ack_o_int : std_logic := '0';
begin
readport : process(clk_i)
@@ -98,8 +100,10 @@ begin
ack : process(clk_i)
begin
if rising_edge(clk_i) then
wbs_o.ack_o <= wbs_i.stb_i and wbs_i.cyc_i;
ack_o_int <= wbs_i.stb_i and wbs_i.cyc_i;
end if;
end process ack;
wbs_o.ack_o <= (ack_o_int or wbs_i.we_i) and wbs_i.stb_i;
--wbs_o.ack_o <= ack_o_int;
end Behavioral;

55
src/wishbone.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-06-03
-- Last update: 2013-06-04
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -50,7 +50,7 @@ package intercon_package is
type mblite_rom_wbs_i_type is record
sel_i : std_logic_vector(3 downto 0);
adr_i : std_logic_vector(11 downto 2);
adr_i : std_logic_vector(13 downto 2);
cyc_i : std_logic;
stb_i : std_logic;
end record;
@@ -96,6 +96,18 @@ package intercon_package is
ack_o : std_logic;
end record;
type spi_wbs_i_type is record
dat_i : std_logic_vector(7 downto 0);
we_i : std_logic;
adr_i : std_logic_vector(1 downto 0);
cyc_i : std_logic;
stb_i : std_logic;
end record;
type spi_wbs_o_type is record
dat_o : std_logic_vector(7 downto 0);
ack_o : std_logic;
end record;
type mem_bridge_wbs_i_type is record
dat_i : std_logic_vector(31 downto 0);
we_i : std_logic;
@@ -145,6 +157,9 @@ entity interconnect is
-- uart
uart_wbs_i : out uart_wbs_i_type;
uart_wbs_o : in uart_wbs_o_type;
-- SPI
spi_sd_wbs_i : out spi_wbs_i_type;
spi_sd_wbs_o : in spi_wbs_o_type;
-- sdram_ctrl
mem_bridge_wbs_i : out mem_bridge_wbs_i_type;
mem_bridge_wbs_o : in mem_bridge_wbs_o_type;
@@ -170,9 +185,9 @@ architecture Behavioral of interconnect is
signal buss_bte_o : std_logic_vector(1 downto 0);
signal buss_cti_o : std_logic_vector(2 downto 0);
signal mblite_rom_ss, ram_ss, pio_led_ss, uart_ss, mem_bridge_ss : std_logic;
signal mblite_rom_ss_r, ram_ss_r, pio_led_ss_r, uart_ss_r, mem_bridge_ss_r : std_logic;
signal uart_cs : std_logic;
signal mblite_rom_ss, ram_ss, pio_led_ss, uart_ss, spi_sd_ss, mem_bridge_ss : std_logic;
signal mblite_rom_ss_r, ram_ss_r, pio_led_ss_r, uart_ss_r, spi_sd_ss_r, mem_bridge_ss_r : std_logic;
signal uart_cs, spi_sd_cs : std_logic;
signal byte_sel : integer range 0 to 3;
signal hword_sel : integer range 0 to 1;
@@ -208,10 +223,11 @@ begin
-- Slave select gen
mblite_rom_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 12) & x"000") = 16#00000000# else '0';
ram_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 11) & "00000000000") = 16#00001000# else '0';
pio_led_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 2) & "00") = 16#00004000# else '0';
uart_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 1) & "0") = 16#00004020# else '0';
mblite_rom_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 14) & "00" & x"000") = 16#00000000# else '0';
ram_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 11) & "00000000000") = 16#00008000# else '0';
pio_led_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 2) & "00") = 16#00010000# else '0';
uart_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 1) & "0") = 16#00010020# else '0';
spi_sd_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 2) & "00") = 16#00010030# else '0';
mem_bridge_ss <= '1' when unsigned(buss_adr_o((wb_addr_width-1) downto 26) & "00" & x"000000") = 16#08000000# else '0';
byte_sel <= to_integer(unsigned(buss_adr_o(1 downto 0)));
@@ -226,6 +242,7 @@ begin
ram_ss_r <= ram_ss;
pio_led_ss_r <= pio_led_ss;
uart_ss_r <= uart_ss;
spi_sd_ss_r <= spi_sd_ss;
mem_bridge_ss_r <= mem_bridge_ss;
end if;
end process ss_regs;
@@ -235,23 +252,25 @@ begin
ram_wbs_o.dat_o when ram_ss_r = '1' else
pio_led_wbs_o.dat_o when pio_led_ss_r = '1' else
uart_wbs_o.dat_o & uart_wbs_o.dat_o & uart_wbs_o.dat_o & uart_wbs_o.dat_o when uart_ss_r = '1' else
spi_sd_wbs_o.dat_o & spi_sd_wbs_o.dat_o & spi_sd_wbs_o.dat_o & spi_sd_wbs_o.dat_o when spi_sd_ss_r = '1' else
mem_bridge_wbs_o.dat_o when mem_bridge_ss_r = '1' else
(others => '-');
buss_ack_i <= mblite_rom_wbs_o.ack_o when mblite_rom_ss_r = '1' else
ram_wbs_o.ack_o when ram_ss_r = '1' else
pio_led_wbs_o.ack_o when pio_led_ss_r = '1' else
uart_wbs_o.ack_o when uart_ss_r = '1' else
spi_sd_wbs_o.ack_o when spi_sd_ss_r = '1' else
mem_bridge_wbs_o.ack_o when mem_bridge_ss_r = '1' else
'0';
-- Slave modules
-- mblite_rom (32bit, 0x00000000 - 0x00001000)
-- mblite_rom (32bit, 0x00000000 - 0x00004000)
mblite_rom_wbs_i.sel_i <= buss_sel_o;
mblite_rom_wbs_i.adr_i <= buss_adr_o(11 downto 2);
mblite_rom_wbs_i.adr_i <= buss_adr_o(13 downto 2);
mblite_rom_wbs_i.cyc_i <= buss_cyc_o and mblite_rom_ss;
mblite_rom_wbs_i.stb_i <= buss_stb_o and mblite_rom_ss;
-- ram (32bit, 0x00001000 - 0x00001800)
-- ram (32bit, 0x00008000 - 0x00008800)
ram_wbs_i.sel_i <= buss_sel_o;
ram_wbs_i.adr_i <= buss_adr_o(10 downto 2);
ram_wbs_i.cyc_i <= buss_cyc_o and ram_ss;
@@ -259,14 +278,14 @@ begin
ram_wbs_i.we_i <= buss_we_o;
ram_wbs_i.dat_i <= buss_dat_o;
-- PIO led (32bit, 0x00004000 - 0x00004004)
-- PIO led (32bit, 0x00010000 - 0x00010004)
pio_led_wbs_i.sel_i <= buss_sel_o;
pio_led_wbs_i.cyc_i <= buss_cyc_o and pio_led_ss;
pio_led_wbs_i.stb_i <= buss_stb_o and pio_led_ss;
pio_led_wbs_i.we_i <= buss_we_o;
pio_led_wbs_i.dat_i <= buss_dat_o;
-- UART (8bit, 0x00004020 - 0x00004022)
-- UART (8bit, 0x00010020 - 0x00010022)
uart_cs <= buss_sel_o(3-byte_sel);
uart_wbs_i.cyc_i <= buss_cyc_o and uart_ss;
uart_wbs_i.stb_i <= buss_stb_o and uart_ss and uart_cs;
@@ -274,6 +293,14 @@ begin
uart_wbs_i.dat_i <= buss_dat_o(8*(3-byte_sel)+7 downto 8*(3-byte_sel));
uart_wbs_i.adr_i <= buss_adr_o(0 downto 0);
-- SPI (8bit, 0x00010030 - 0x00010034)
spi_sd_cs <= buss_sel_o(3-byte_sel);
spi_sd_wbs_i.cyc_i <= buss_cyc_o and spi_sd_ss;
spi_sd_wbs_i.stb_i <= buss_stb_o and spi_sd_ss and spi_sd_cs;
spi_sd_wbs_i.we_i <= buss_we_o;
spi_sd_wbs_i.dat_i <= buss_dat_o(8*(3-byte_sel)+7 downto 8*(3-byte_sel));
spi_sd_wbs_i.adr_i <= buss_adr_o(1 downto 0);
-- mem_bridge (32bit, 0x08000000 - 0x0C000000)
mem_bridge_wbs_i.sel_i <= buss_sel_o;
mem_bridge_wbs_i.adr_i <= buss_adr_o(25 downto 2);

227
tb/spi_tb.vhd Normal file
View File

@@ -0,0 +1,227 @@
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi"
-- Project :
-------------------------------------------------------------------------------
-- File : spi_tb.vhd
-- Author : <matthias@pc>
-- Company :
-- Created : 2013-06-07
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-06-07 1.0 matthias Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.intercon_package.all;
-------------------------------------------------------------------------------
entity spi_tb is
end entity spi_tb;
-------------------------------------------------------------------------------
architecture testbench of spi_tb is
-- component generics
constant dontcare : std_logic := '-';
constant clock_pol : std_logic := '1';
constant clock_phase : std_logic := '0';
-- component ports
signal clk_i : std_logic;
signal rst_i : std_logic := '1';
signal wbs_i : spi_wbs_i_type;
signal wbs_o : spi_wbs_o_type;
signal miso : std_logic;
signal mosi : std_logic;
signal sclk : std_logic;
signal ss : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- architecture testbench
-- component instantiation
DUT: entity work.spi
generic map (
dontcare => dontcare,
clock_pol => clock_pol,
clock_phase => clock_phase)
port map (
clk_i => clk_i,
rst_i => rst_i,
wbs_i => wbs_i,
wbs_o => wbs_o,
miso => miso,
mosi => mosi,
sclk => sclk,
ss => ss);
-- clock generation
clk <= not clk after 10 ns;
clk_i <= clk;
wb_gen : process
variable got_data : boolean := false;
begin
wait for 100 ns;
rst_i <= '0';
wait until rising_edge(clk_i);
wait until rising_edge(clk_i);
-- Set output clock divider
wbs_i.we_i <= '1';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "10";
wbs_i.dat_i <= x"03";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
-- Select slave
wbs_i.we_i <= '1';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "11";
wbs_i.dat_i <= x"00";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
-- Send data
wbs_i.we_i <= '1';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "00";
wbs_i.dat_i <= x"5a";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
-- Wait for recvd data
while not got_data loop
wbs_i.we_i <= '0';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "01";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
if wbs_o.dat_o(2) = '0' then
got_data := true;
end if;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
end loop;
-- Check recvd data
wbs_i.we_i <= '0';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "00";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
assert wbs_o.dat_o = x"a5" report "Received data incorrect" severity error;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
-- Deselect slave
wbs_i.we_i <= '1';
wbs_i.stb_i <= '1';
wbs_i.cyc_i <= '1';
wbs_i.adr_i <= "11";
wbs_i.dat_i <= x"01";
wait until rising_edge(clk_i);
while wbs_o.ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
wbs_i.stb_i <= '0';
while wbs_o.ack_o = '1' loop
wait until rising_edge(clk_i);
end loop;
wait until rising_edge(clk_i);
wait;
end process wb_gen;
spi_gen : process
variable sreg : std_logic_vector(7 downto 0) := x"a5";
variable cap : std_logic;
begin
wait until rst_i = '0';
wait until rising_edge(clk_i);
wait until ss = '0';
miso <= sreg(7);
for i in 7 downto 1 loop
wait until rising_edge(sclk);
sreg(i) := mosi;
wait until falling_edge(sclk);
miso <= sreg(i-1);
end loop;
wait until rising_edge(sclk);
sreg(0) := mosi;
wait until ss = '1';
assert sreg = x"5a" report "Transmitted data incorrect" severity error;
wait;
end process spi_gen;
end architecture testbench;
-------------------------------------------------------------------------------
configuration spi_tb_testbench_cfg of spi_tb is
for testbench
end for;
end spi_tb_testbench_cfg;
-------------------------------------------------------------------------------

16
tb/toplevel_tb.vhd
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@@ -6,7 +6,7 @@
-- Author : <Matthias@MATTHIAS-PC>
-- Company :
-- Created : 2013-03-02
-- Last update: 2013-06-03
-- Last update: 2013-06-07
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -63,7 +63,11 @@ architecture testbench of toplevel_tb is
ddr2_ck : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
rs232_txd : out std_logic;
rs232_rxd : in std_logic
rs232_rxd : in std_logic;
sd_miso : in std_logic;
sd_mosi : out std_logic;
sd_cs : out std_logic;
sd_sck : out std_logic
);
end component;
@@ -116,6 +120,7 @@ architecture testbench of toplevel_tb is
signal ddr2_ck_n : std_logic_vector(0 downto 0);
signal rs232_txd, rs232_rxd : std_logic := '1';
signal sd_mosi, sd_miso, sd_cs, sd_sck : std_logic := '0';
signal sim_done : boolean := false;
@@ -159,9 +164,14 @@ begin -- testbench
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n,
rs232_txd => rs232_txd,
rs232_rxd => rs232_rxd);
rs232_rxd => rs232_rxd,
sd_mosi => sd_mosi,
sd_miso => sd_miso,
sd_cs => sd_cs,
sd_sck => sd_sck);
rst_dqs_div_in <= rst_dqs_div_out after 100 ps;
rs232_rxd <= rs232_txd;
ddr2_model_inst : ddr2_model port map (
ck => ddr2_ck(0),

1300
toplevel_tb.wcfg
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