|
|
0bc4815926
|
- Debugged SPI module
- Debugged UART
- Firmware support for SPI, UART
- Work on SD/MMC support in firmware
- Debugged mblite core/WB interface
|
2013-06-08 11:53:27 +02:00 |
|
|
|
882ec0a33f
|
- Integrated MBlite CPU
- Integrated UART
- Various bug fixes
|
2013-06-03 19:36:51 +02:00 |
|
|
|
f501602ad6
|
- Added LEDs to ucf
|
2013-06-02 11:56:10 +02:00 |
|
|
|
a75ce72129
|
- Fixed address generation bug for manual cache flush
- Made some constants in cpu.vhd more readable
- Fixed buffer flipping in cpu.vhd
|
2013-05-31 16:42:22 +02:00 |
|
|
|
a6b20d3311
|
- Fixed wishbone interconnect generator
- Fixed accidental latches in wb_ddr_ctrl_wb_sc.vhd
- Updated cpu for new manual cache flush
|
2013-03-21 16:06:53 +01:00 |
|
|
|
973513900d
|
- Work on simulator
- Optimized wb_ddr_ctrl_wb_sc_fe and wb_ddr_ctrl_wb_dc[_fsm]
|
2013-03-18 15:27:18 +01:00 |
|
|
|
077bef75d3
|
- System integration & debugging
|
2013-03-09 14:14:22 +01:00 |
|
|
|
34bec7d6c7
|
- Begun implementing VGA out
- Integrated wishbone interconnect generator
- Debugging
|
2013-03-02 21:27:54 +01:00 |
|
