Matthias Blankertz 922e103f41 - Always convert wishbone.defines to unix line endings so interconnect is ...

correctly build on windows
- Removed TK dependency from tools/wishbone.pl

2013-03-21 19:57:49 +01:00

constr

- System integration & debugging

2013-03-09 14:14:22 +01:00

coregen

- Work on simulator

2013-03-18 15:27:18 +01:00

ddr2_sdram/vhdl_bl4/example_design

- System integration & debugging

2013-03-09 14:14:22 +01:00

sim

- Added double buffering support to vga controller and cpu

2013-03-21 19:05:22 +01:00

src

- Added double buffering support to vga controller and cpu

2013-03-21 19:05:22 +01:00

tb

- Added double buffering support to vga controller and cpu

2013-03-21 19:05:22 +01:00

tools

- Always convert wishbone.defines to unix line endings so interconnect is

2013-03-21 19:57:49 +01:00

zy2000

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

.gitignore

- Reworked VGA

2013-03-07 20:55:58 +01:00

Makefile

- Always convert wishbone.defines to unix line endings so interconnect is

2013-03-21 19:57:49 +01:00

toplevel_tb.wcfg

- Fixed wishbone interconnect generator

2013-03-21 16:06:53 +01:00

vga_tb.wcfg

- Reworked VGA

2013-03-07 20:55:58 +01:00

vga.bmp

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_tb.wcfg

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_wb_sc_fe_tb.wcfg

- Some optimization

2013-03-19 20:24:28 +01:00

wb_ddr_ctrl_wb_sc_tb.wcfg

- Integrated DDR controller with VGA and cache controller

2013-03-08 21:43:43 +01:00

Description

No description provided

372 KiB

Languages

VHDL 69.1%

Verilog 10.1%

SystemVerilog 8%

Raku 7.9%

C++ 2.6%

Other 2.2%