37 lines
1.2 KiB
Plaintext
Executable File
37 lines
1.2 KiB
Plaintext
Executable File
The following files were generated for 'distram16x8' in directory
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c:\vhdl\nascom2\coregen\:
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distram16x8.ngc:
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Binary Xilinx implementation netlist file containing the information
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required to implement the module in a Xilinx (R) FPGA.
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distram16x8.vhd:
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VHDL wrapper file provided to support functional simulation. This
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file contains simulation model customization data that is passed to
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a parameterized simulation model for the core.
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distram16x8.vho:
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VHO template file containing code that can be used as a model for
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instantiating a CORE Generator module in a VHDL design.
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distram16x8.xco:
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CORE Generator input file containing the parameters used to
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regenerate a core.
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distram16x8_flist.txt:
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Text file listing all of the output files produced when a customized
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core was generated in the CORE Generator.
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distram16x8_readme.txt:
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Text file indicating the files generated and how they are used.
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distram16x8_xmdf.tcl:
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ISE Project Navigator interface file. ISE uses this file to determine
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how the files output by CORE Generator for the core can be integrated
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into your ISE project.
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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