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matthias
2009-01-15 19:17:56 +00:00
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8192
coregen/basic_rom.mif Executable file
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coregen/basic_rom.ngc Executable file
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coregen/basic_rom.vhd Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file basic_rom.vhd when simulating
-- the core, basic_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY basic_rom IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(12 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
END basic_rom;
ARCHITECTURE basic_rom_a OF basic_rom IS
-- synthesis translate_off
component wrapped_basic_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(12 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_basic_rom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "basic_rom.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 8192,
c_write_depth_a => 8192,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 13,
c_addrb_width => 13,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 8192,
c_read_depth_a => 8192,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 1,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_basic_rom
port map (
clka => clka,
addra => addra,
ena => ena,
douta => douta);
-- synthesis translate_on
END basic_rom_a;

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coregen/basic_rom.vho Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component basic_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(12 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : basic_rom
port map (
clka => clka,
addra => addra,
ena => ena,
douta => douta);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file basic_rom.vhd when simulating
-- the core, basic_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

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coregen/basic_rom.xco Executable file
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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Fri Jan 09 14:26:54 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=C:/vhdl/Basic.coe
CSET collision_warnings=ALL
CSET component_name=basic_rom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=8192
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: 1cd67ff3

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coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj Executable file
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vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\basic_rom_blk_mem_gen_v2_6_xst_1.vhd"

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coregen/basic_rom_flist.txt Executable file
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# Output products list for <basic_rom>
basic_rom.mif
basic_rom.ngc
basic_rom.vhd
basic_rom.vho
basic_rom.xco
basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
basic_rom_flist.txt
basic_rom_xmdf.tcl

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coregen/basic_rom_readme.txt Executable file
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The following files were generated for 'basic_rom' in directory
C:\vhdl\nascom2_t80\coregen\:
basic_rom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
basic_rom.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
basic_rom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
basic_rom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
basic_rom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
Please see the core data sheet.
basic_rom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
basic_rom_readme.txt:
Text file indicating the files generated and how they are used.
basic_rom_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

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coregen/basic_rom_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide basic_rom_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::basic_rom_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::basic_rom_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name basic_rom
}
# ::basic_rom_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::basic_rom_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module basic_rom
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

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coregen/blk_mem_gen_ds512.pdf Executable file
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coregen/blk_mem_gen_v2_6.mif Executable file
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coregen/blk_mem_gen_v2_6.ngc Executable file
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coregen/blk_mem_gen_v2_6.vhd Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating
-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v2_6 IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END blk_mem_gen_v2_6;
ARCHITECTURE blk_mem_gen_v2_6_a OF blk_mem_gen_v2_6 IS
-- synthesis translate_off
component wrapped_blk_mem_gen_v2_6
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_blk_mem_gen_v2_6 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "blk_mem_gen_v2_6.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v2_6
port map (
clka => clka,
addra => addra,
douta => douta);
-- synthesis translate_on
END blk_mem_gen_v2_6_a;

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coregen/blk_mem_gen_v2_6.vho Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component blk_mem_gen_v2_6
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_gen_v2_6
port map (
clka => clka,
addra => addra,
douta => douta);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating
-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

78
coregen/blk_mem_gen_v2_6.xco Executable file
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@@ -0,0 +1,78 @@
##############################################################
#
# Xilinx Core Generator version J.40
# Date: Sat Jan 03 11:55:39 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe
CSET collision_warnings=ALL
CSET component_name=blk_mem_gen_v2_6
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=2048
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: 686b742a

24
coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj Executable file
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vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1.vhd"

9
coregen/blk_mem_gen_v2_6_flist.txt Executable file
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# Output products list for <blk_mem_gen_v2_6>
blk_mem_gen_v2_6.mif
blk_mem_gen_v2_6.ngc
blk_mem_gen_v2_6.vhd
blk_mem_gen_v2_6.vho
blk_mem_gen_v2_6.xco
blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
blk_mem_gen_v2_6_flist.txt
blk_mem_gen_v2_6_xmdf.tcl

45
coregen/blk_mem_gen_v2_6_readme.txt Executable file
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The following files were generated for 'blk_mem_gen_v2_6' in directory
C:\vhdl\nascom2_t80\coregen\:
blk_mem_gen_v2_6.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
blk_mem_gen_v2_6.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
blk_mem_gen_v2_6.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
blk_mem_gen_v2_6.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
blk_mem_gen_v2_6.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj:
Please see the core data sheet.
blk_mem_gen_v2_6_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
blk_mem_gen_v2_6_readme.txt:
Text file indicating the files generated and how they are used.
blk_mem_gen_v2_6_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

72
coregen/blk_mem_gen_v2_6_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide blk_mem_gen_v2_6_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::blk_mem_gen_v2_6_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::blk_mem_gen_v2_6_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v2_6
}
# ::blk_mem_gen_v2_6_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::blk_mem_gen_v2_6_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v2_6
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

2048
coregen/charrom.mif Executable file
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3
coregen/charrom.ngc Executable file
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118
coregen/charrom.vhd Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file charrom.vhd when simulating
-- the core, charrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY charrom IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END charrom;
ARCHITECTURE charrom_a OF charrom IS
-- synthesis translate_off
component wrapped_charrom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_charrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "charrom.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_charrom
port map (
clka => clka,
addra => addra,
douta => douta);
-- synthesis translate_on
END charrom_a;

56
coregen/charrom.vho Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component charrom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : charrom
port map (
clka => clka,
addra => addra,
douta => douta);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file charrom.vhd when simulating
-- the core, charrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

78
coregen/charrom.xco Executable file
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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Sat Jan 03 11:56:55 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe
CSET collision_warnings=ALL
CSET component_name=charrom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=2048
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: 55453eb

24
coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj Executable file
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vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\charrom_blk_mem_gen_v2_6_xst_1.vhd"

10
coregen/charrom_flist.txt Executable file
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# Output products list for <charrom>
blk_mem_gen_v2_6.mif
charrom.mif
charrom.ngc
charrom.vhd
charrom.vho
charrom.xco
charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
charrom_flist.txt
charrom_xmdf.tcl

51
coregen/charrom_readme.txt Executable file
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The following files were generated for 'charrom' in directory
C:\vhdl\nascom2_t80\coregen\:
blk_mem_gen_v2_6.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
charrom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
charrom.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
charrom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
charrom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
charrom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
Please see the core data sheet.
charrom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
charrom_readme.txt:
Text file indicating the files generated and how they are used.
charrom_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

76
coregen/charrom_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide charrom_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::charrom_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::charrom_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name charrom
}
# ::charrom_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::charrom_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module charrom
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

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# Date: Wed Dec 31 13:09:41 2008
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = c:\vhdl\nascom2\coregen\tmp

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coregen/dcm_in50.vhd Executable file
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.2.04i
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm_in50.vhd
-- /___/ /\ Timestamp : 01/03/2009 16:40:00
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\vhdl\nascom2_t80\coregen\\dcm_in50.xaw C:\vhdl\nascom2_t80\coregen\\dcm_in50
--Design Name: dcm_in50
--Device: xc3s700an-4fgg484
--
-- Module dcm_in50
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.88 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm_in50 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm_in50;
architecture BEHAVIORAL of dcm_in50 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => TRUE,
CLKIN_PERIOD => 40.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => TRUE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;

3
coregen/dcm_in50.xaw Executable file
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
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17
coregen/dcm_in50_arwz.ucf Executable file
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# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 25;
INST DCM_SP_INST CLKFX_MULTIPLY = 16;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = TRUE;
INST DCM_SP_INST CLKIN_PERIOD = 40.000;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = TRUE;

BIN
coregen/dist_mem_gen_ds322.pdf Executable file
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99
coregen/dist_mem_gen_release_notes.txt Executable file
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COPYRIGHT (c) 2007 XILINX, INC.
ALL RIGHTS RESERVED
Core name : Distributed Memory Generator
Version : v3.3
Release Date : April 2, 2007
File : distributed_memory_generator_release_notes.txt
Revision History
Date By Version Change Description
========================================================================
4/2007 Xilinx, Inc. 3.3 Initial creation.
========================================================================
INTRODUCTION
RELEASE NOTES
1. General Core Design
1.1 Enhancements
1.2 Resolved Issues
1.3 Outstanding Issues
2. General Simulation
2.1 Enhancements
2.2 Resolved Issues
2.3 Outstanding Issues
3. Documentation
3.1 Enhancements
3.2 Resolved Issues
3.3 Outstanding Issues
OTHER GENERAL INFORMATION
TECHNICAL SUPPORT
========================================================================
INTRODUCTION
============
Thank you using the Distributed Memory Generator core from Xilinx!
In order to obtain the latest core updates and documentation,
please visit the Intellectual Property page located at:
http://www.xilinx.com/ipcenter/index.htm
This document contains the release notes for Distributed Memory Generator v3.3
which includes enhancements, resolved issues and outstanding known
issues. For release notes and known issues for CORE Generator 9.1i
IP Update and Distributed Memory Generator v3.3 please see Answer Record 24307.
RELEASE NOTES
=============
This section lists any enhancements, resolved issues and outstanding
known issues.
1. General Core Design
1.1 Enhancements
1.1.1 Support for Spartan(TM) - 3A DSP
time.
1.2 Resolved Issues
1.2.1 Solved excessive register duplication in distributed memory synthesis.
Change request: 326740
1.3 Outstanding Issues
1.3.1 When a large Distributed Memory Generator IP is generated, CORE ,
Generator runs out of memory and fails to generate.
Change request: 431917
2. General Simulation
2.1 Enhancements
None at this time.
2.2 Resolved Issues
None at this time.
2.3 Outstanding Issues
None at this time.
3. Documentation
3.1 Enhancements
None at this time.
3.2 Resolved Issues
None at this time.
3.3 Outstanding Issues
None at this time.
TECHNICAL SUPPORT
=================
The fastest method for obtaining specific technical support for the
Distributed Memory Generator core is through the http://support.xilinx.com/
website. Questions are routed to a team of engineers with specific
expertise in using the Distributed Memory Generator core. Xilinx will provide
technical support for use of this product as described in the Distributed
Memory Generator Datasheet. Xilinx cannot guarantee timing,
functionality, or support of this product for designs that do not
follow these guidelines.

3
coregen/distram16x8.ngc Executable file
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115
coregen/distram16x8.vhd Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file distram16x8.vhd when simulating
-- the core, distram16x8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY distram16x8 IS
port (
a: IN std_logic_VECTOR(3 downto 0);
d: IN std_logic_VECTOR(7 downto 0);
dpra: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
we: IN std_logic;
spo: OUT std_logic_VECTOR(7 downto 0);
dpo: OUT std_logic_VECTOR(7 downto 0));
END distram16x8;
ARCHITECTURE distram16x8_a OF distram16x8 IS
-- synthesis translate_off
component wrapped_distram16x8
port (
a: IN std_logic_VECTOR(3 downto 0);
d: IN std_logic_VECTOR(7 downto 0);
dpra: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
we: IN std_logic;
spo: OUT std_logic_VECTOR(7 downto 0);
dpo: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_distram16x8 use entity XilinxCoreLib.dist_mem_gen_v3_3(behavioral)
generic map(
c_has_clk => 1,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_has_d => 1,
c_has_spo => 1,
c_read_mif => 0,
c_has_qspo => 0,
c_width => 8,
c_reg_a_d_inputs => 0,
c_has_we => 1,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_sync_enable => 1,
c_depth => 16,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 1,
c_qce_joined => 0,
c_mem_type => 2,
c_has_i_ce => 0,
c_has_dpo => 1,
c_mem_init_file => "no_coe_file_loaded",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 4,
c_has_qdpo => 0,
c_has_qspo_rst => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_distram16x8
port map (
a => a,
d => d,
dpra => dpra,
clk => clk,
we => we,
spo => spo,
dpo => dpo);
-- synthesis translate_on
END distram16x8_a;

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coregen/distram16x8.vho Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component distram16x8
port (
a: IN std_logic_VECTOR(3 downto 0);
d: IN std_logic_VECTOR(7 downto 0);
dpra: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
we: IN std_logic;
spo: OUT std_logic_VECTOR(7 downto 0);
dpo: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : distram16x8
port map (
a => a,
d => d,
dpra => dpra,
clk => clk,
we => we,
spo => spo,
dpo => dpo);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file distram16x8.vhd when simulating
-- the core, distram16x8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

63
coregen/distram16x8.xco Executable file
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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Wed Dec 31 13:10:21 2008
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.3
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=no_coe_file_loaded
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=distram16x8
CSET data_width=8
CSET default_data=0
CSET default_data_radix=16
CSET depth=16
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=dual_port_ram
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qspo=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qspo=false
# END Parameters
GENERATE
# CRC: 79e446fd

7
coregen/distram16x8_flist.txt Executable file
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# Output products list for <distram16x8>
distram16x8.ngc
distram16x8.vhd
distram16x8.vho
distram16x8.xco
distram16x8_flist.txt
distram16x8_xmdf.tcl

36
coregen/distram16x8_readme.txt Executable file
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The following files were generated for 'distram16x8' in directory
c:\vhdl\nascom2\coregen\:
distram16x8.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
distram16x8.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
distram16x8.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
distram16x8.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
distram16x8_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
distram16x8_readme.txt:
Text file indicating the files generated and how they are used.
distram16x8_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

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coregen/distram16x8_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide distram16x8_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::distram16x8_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::distram16x8_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name distram16x8
}
# ::distram16x8_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::distram16x8_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module distram16x8
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

17
coregen/monitorrom.asy Executable file
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 monitorrom
RECTANGLE Normal 32 32 544 576
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[10:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[7:0]
PINATTR Polarity OUT

2048
coregen/monitorrom.mif Executable file
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File diff suppressed because it is too large Load Diff

3
coregen/monitorrom.ngc Executable file
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27
coregen/monitorrom.sym Executable file
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VERSION 5
BEGIN SYMBOL monitorrom
SYMBOLTYPE BLOCK
TIMESTAMP 2008 12 31 13 31 1
SYMPIN 0 80 Input addra[10:0]
SYMPIN 0 272 Input clka
SYMPIN 576 80 Output douta[7:0]
BEGIN DISPLAY 32 32 TEXT monitorrom
FONT 40 "Arial"
END DISPLAY
RECTANGLE N 32 32 544 576
BEGIN LINE W 0 80 32 80
END LINE
BEGIN DISPLAY 36 80 PIN addra[10:0] ATTR PinName
FONT 24 "Arial"
END DISPLAY
LINE N 0 272 32 272
BEGIN DISPLAY 36 272 PIN clka ATTR PinName
FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 576 80 544 80
END LINE
BEGIN DISPLAY 540 80 PIN douta[7:0] ATTR PinName
ALIGNMENT RIGHT
FONT 24 "Arial"
END DISPLAY
END SYMBOL

126
coregen/monitorrom.v Executable file
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file monitorrom.v when simulating
// the core, monitorrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module monitorrom(
clka,
addra,
douta);
input clka;
input [10 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V2_6 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("monitorrom.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3a"))
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.DINA(),
.ENA(),
.REGCEA(),
.WEA(),
.SSRA(),
.CLKB(),
.DINB(),
.ADDRB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DOUTB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of monitorrom is "black_box"
endmodule

45
coregen/monitorrom.veo Executable file
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
monitorrom YourInstanceName (
.clka(clka),
.addra(addra), // Bus [10 : 0]
.douta(douta)); // Bus [7 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file monitorrom.v when simulating
// the core, monitorrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

121
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file monitorrom.vhd when simulating
-- the core, monitorrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY monitorrom IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
END monitorrom;
ARCHITECTURE monitorrom_a OF monitorrom IS
-- synthesis translate_off
component wrapped_monitorrom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "monitorrom.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 1,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_monitorrom
port map (
clka => clka,
addra => addra,
ena => ena,
douta => douta);
-- synthesis translate_on
END monitorrom_a;

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coregen/monitorrom.vhd.bak Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file monitorrom.vhd when simulating
-- the core, monitorrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY monitorrom IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END monitorrom;
ARCHITECTURE monitorrom_a OF monitorrom IS
-- synthesis translate_off
component wrapped_monitorrom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "monitorrom.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_monitorrom
port map (
clka => clka,
addra => addra,
douta => douta);
-- synthesis translate_on
END monitorrom_a;

58
coregen/monitorrom.vho Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component monitorrom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : monitorrom
port map (
clka => clka,
addra => addra,
ena => ena,
douta => douta);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file monitorrom.vhd when simulating
-- the core, monitorrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

78
coregen/monitorrom.xco Executable file
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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Thu Jan 08 11:30:25 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=C:/vhdl/nascom2_t80/NASSYSI.coe
CSET collision_warnings=ALL
CSET component_name=monitorrom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=true
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=2048
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: b5ba28bc

24
coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj Executable file
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vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\monitorrom_blk_mem_gen_v2_6_xst_1.vhd"

9
coregen/monitorrom_flist.txt Executable file
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# Output products list for <monitorrom>
monitorrom.mif
monitorrom.ngc
monitorrom.vhd
monitorrom.vho
monitorrom.xco
monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
monitorrom_flist.txt
monitorrom_xmdf.tcl

45
coregen/monitorrom_readme.txt Executable file
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The following files were generated for 'monitorrom' in directory
C:\vhdl\nascom2_t80\coregen\:
monitorrom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
monitorrom.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
monitorrom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
monitorrom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
monitorrom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
Please see the core data sheet.
monitorrom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
monitorrom_readme.txt:
Text file indicating the files generated and how they are used.
monitorrom_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

72
coregen/monitorrom_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide monitorrom_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::monitorrom_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::monitorrom_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name monitorrom
}
# ::monitorrom_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::monitorrom_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module monitorrom
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

3
coregen/ram2kx8.ngc Executable file
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142
coregen/ram2kx8.vhd Executable file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram2kx8.vhd when simulating
-- the core, ram2kx8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY ram2kx8 IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
clkb: IN std_logic;
dinb: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(10 downto 0);
web: IN std_logic_VECTOR(0 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
END ram2kx8;
ARCHITECTURE ram2kx8_a OF ram2kx8 IS
-- synthesis translate_off
component wrapped_ram2kx8
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
clkb: IN std_logic;
dinb: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(10 downto 0);
web: IN std_logic_VECTOR(0 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_ram2kx8 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 2,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 8,
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "READ_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "READ_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3a",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 0,
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 1,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram2kx8
port map (
clka => clka,
dina => dina,
addra => addra,
ena => ena,
wea => wea,
douta => douta,
clkb => clkb,
dinb => dinb,
addrb => addrb,
web => web,
doutb => doutb);
-- synthesis translate_on
END ram2kx8_a;

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ram2kx8
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(10 downto 0);
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
clkb: IN std_logic;
dinb: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(10 downto 0);
web: IN std_logic_VECTOR(0 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ram2kx8
port map (
clka => clka,
dina => dina,
addra => addra,
ena => ena,
wea => wea,
douta => douta,
clkb => clkb,
dinb => dinb,
addrb => addrb,
web => web,
doutb => doutb);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file ram2kx8.vhd when simulating
-- the core, ram2kx8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

78
coregen/ram2kx8.xco Executable file
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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Sat Jan 03 15:42:53 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=ram2kx8
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=true
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=READ_FIRST
CSET operating_mode_b=READ_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=2048
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: bde5567c

24
coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj Executable file
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vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd"
vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\ram2kx8_blk_mem_gen_v2_6_xst_1.vhd"

8
coregen/ram2kx8_flist.txt Executable file
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# Output products list for <ram2kx8>
ram2kx8.ngc
ram2kx8.vhd
ram2kx8.vho
ram2kx8.xco
ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
ram2kx8_flist.txt
ram2kx8_xmdf.tcl

39
coregen/ram2kx8_readme.txt Executable file
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The following files were generated for 'ram2kx8' in directory
C:\vhdl\nascom2_t80\coregen\:
ram2kx8.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ram2kx8.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ram2kx8.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ram2kx8.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj:
Please see the core data sheet.
ram2kx8_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
ram2kx8_readme.txt:
Text file indicating the files generated and how they are used.
ram2kx8_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

68
coregen/ram2kx8_xmdf.tcl Executable file
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# The package naming convention is <core_name>_xmdf
package provide ram2kx8_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::ram2kx8_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::ram2kx8_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name ram2kx8
}
# ::ram2kx8_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::ram2kx8_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram2kx8
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams