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coregen/monitorrom_readme.txt

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+The following files were generated for 'monitorrom' in directory 
+C:\vhdl\nascom2_t80\coregen\:
+
+monitorrom.mif:
+   Memory Initialization File which is automatically generated by the
+   CORE Generator System for some modules when a simulation flow is
+   specified. A MIF data file is used to support HDL functional
+   simulation of modules which use arrays of values.
+
+monitorrom.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+monitorrom.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+monitorrom.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+monitorrom.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj:
+   Please see the core data sheet.
+
+monitorrom_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+monitorrom_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+monitorrom_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+