Initial commit

textgen.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    16:50:00 12/08/2008 
+-- Design Name: 
+-- Module Name:    textgen - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity textgen is
+    Port ( OE : in STD_LOGIC;
+           CHRX : in  STD_LOGIC_VECTOR (2 downto 0);
+           CHRY : in  STD_LOGIC_VECTOR (3 downto 0);
+           SCRADR : in  STD_LOGIC_VECTOR (11 downto 0);
+           RED : out  STD_LOGIC_VECTOR (3 downto 0);
+           GREEN : out  STD_LOGIC_VECTOR (3 downto 0);
+           BLUE : out  STD_LOGIC_VECTOR (3 downto 0);
+           CLK : in  STD_LOGIC);
+end textgen;
+
+architecture Behavioral of textgen is
+
+component charrom IS
+	port (
+	clka: IN std_logic;
+	addra: IN std_logic_VECTOR(11 downto 0);
+	douta: OUT std_logic_VECTOR(7 downto 0));
+END component;
+
+component textram IS
+	port (
+	clka: IN std_logic;
+	dina: IN std_logic_VECTOR(7 downto 0);
+	addra: IN std_logic_VECTOR(11 downto 0);
+	wea: IN std_logic_VECTOR(0 downto 0);
+	douta: OUT std_logic_VECTOR(7 downto 0));
+END component;
+signal out_i, oe_i: std_logic := '0';
+signal charrom_adr, textram_adr: std_logic_vector(11 downto 0);
+signal charrom_data, textram_data: std_logic_vector(7 downto 0);
+signal oe_d1, oe_d2, oe_d3: std_logic := '0';
+begin
+	textram_adr <= SCRADR;
+	
+	textram_inst: textram port map(	clka => CLK,
+                                        dina => "00000000",
+                                        addra => textram_adr,
+                                        wea => "0",
+                                        douta => textram_data);
+	
+	charrom_adr(11 downto 4) <= textram_data;
+	charrom_adr(3 downto 0) <= CHRY;
+	
+	charrom_inst: charrom port map(	clka => CLK,
+                                        addra => charrom_adr,
+                                        douta => charrom_data);
+	
+
+	process (CLK)
+	variable bitmap: std_logic_vector(7 downto 0) := "00000000";
+	begin
+          if rising_edge(CLK) then
+            if CHRX = 3 then
+              bitmap := charrom_data;
+            end if;
+            out_i <= bitmap((conv_integer(2 - CHRX)));
+          end if;
+	end process;
+
+oe_delay: process (CLK)
+	begin
+          if rising_edge(CLK) then
+            oe_d1 <= OE;
+            oe_d2 <= oe_d1;
+            oe_d3 <= oe_d2;
+            oe_i <= oe_d3;
+          end if;
+	end process;
+
+RED <= (others => out_i) when oe_i = '1' else "0000";
+GREEN <= (others => out_i) when oe_i = '1' else "0000";
+BLUE <= (others => out_i) when oe_i = '1' else "0000";
+end Behavioral;
+