Matthias Blankertz 0080ec255d WIP

2017-02-01 12:07:10 +01:00

constr

- WIP: New cache for CPU

2013-06-19 15:01:32 +02:00

coregen

WIP

2017-02-01 12:07:10 +01:00

ddr2_sdram/vhdl_bl4/example_design

- System integration & debugging

2013-03-09 14:14:22 +01:00

firmware

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

mblite

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

sim

- Simulator rasterizer working

2013-03-22 20:12:20 +01:00

src

WIP

2017-02-01 12:07:10 +01:00

tb

- WIP: New cache for CPU

2013-06-19 15:01:32 +02:00

tools

- Always convert wishbone.defines to unix line endings so interconnect is

2013-03-21 19:57:49 +01:00

.gitignore

- Debugged SPI module

2013-06-08 11:53:27 +02:00

bresenham_dp_tb.wcfg

- Started implementing rasterizer

2013-03-26 17:24:15 +01:00

impact.cmd

- Replaced cache with simpler wishbone-memory bridge

2013-06-04 23:18:16 +02:00

Makefile

- WIP: New cache for CPU

2013-06-19 15:01:32 +02:00

mblite_cache_tb.wcfg

- WIP: New cache for CPU

2013-06-19 15:01:32 +02:00

mblite_rom.bmm

- Debugged SPI module

2013-06-08 11:53:27 +02:00

rasterizer_l_tb.wcfg

- Rasterizer

2013-03-27 20:21:58 +01:00

spi_tb.wcfg

- Debugged SPI module

2013-06-08 11:53:27 +02:00

toplevel_tb.wcfg

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

vga_tb.wcfg

- Reworked VGA

2013-03-07 20:55:58 +01:00

vga.bmp

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_tb.wcfg

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_wb_sc_fe_tb.wcfg

- Some optimization

2013-03-19 20:24:28 +01:00

wb_ddr_ctrl_wb_sc_tb.wcfg

- New Wishbone master for CPU

2013-06-19 09:16:36 +02:00

wb_mem_bridge_tb.wcfg

- Replaced cache with simpler wishbone-memory bridge

2013-06-04 23:18:16 +02:00

Description

No description provided

372 KiB

Languages

VHDL 69.1%

Verilog 10.1%

SystemVerilog 8%

Raku 7.9%

C++ 2.6%

Other 2.2%