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0080ec255d
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WIP
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2017-02-01 12:07:10 +01:00 |
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6cd60cf263
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- WIP: New cache for CPU
- sysClk reduced to 45 MHz
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2013-06-19 15:01:32 +02:00 |
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0a96ce78f0
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- New Wishbone master for CPU
- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...
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2013-06-19 09:16:36 +02:00 |
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0bc4815926
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- Debugged SPI module
- Debugged UART
- Firmware support for SPI, UART
- Work on SD/MMC support in firmware
- Debugged mblite core/WB interface
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2013-06-08 11:53:27 +02:00 |
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fd4e8df556
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- Started implementing SPI controller
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2013-06-05 15:40:06 +02:00 |
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1807fb99b5
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- Replaced cache with simpler wishbone-memory bridge
- Redesign wishbone interconnect
- Changed wb_ddr_ctrl_wb_sc to allow easier addition of ports
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2013-06-04 23:18:16 +02:00 |
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882ec0a33f
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- Integrated MBlite CPU
- Integrated UART
- Various bug fixes
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2013-06-03 19:36:51 +02:00 |
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f501602ad6
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- Added LEDs to ucf
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2013-06-02 11:56:10 +02:00 |
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a75ce72129
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- Fixed address generation bug for manual cache flush
- Made some constants in cpu.vhd more readable
- Fixed buffer flipping in cpu.vhd
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2013-05-31 16:42:22 +02:00 |
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66105bec04
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- Rasterizer
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2013-03-27 20:21:58 +01:00 |
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a279c63df6
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- Started implementing rasterizer
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2013-03-26 17:24:15 +01:00 |
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1d71dfc308
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- Simulator rasterizer working
- Beginning hardware rasterizer implementation
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2013-03-22 20:12:20 +01:00 |
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922e103f41
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- Always convert wishbone.defines to unix line endings so interconnect is
correctly build on windows
- Removed TK dependency from tools/wishbone.pl
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2013-03-21 19:57:49 +01:00 |
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19e97ad179
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- Added double buffering support to vga controller and cpu
- Removed an unused output in wb_ddr_ctrl_wb_dc_fsm
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2013-03-21 19:05:22 +01:00 |
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a6b20d3311
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- Fixed wishbone interconnect generator
- Fixed accidental latches in wb_ddr_ctrl_wb_sc.vhd
- Updated cpu for new manual cache flush
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2013-03-21 16:06:53 +01:00 |
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37d63b062d
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- Some optimization
- Cache manual flush/invalidate is now whole cache instead of by address
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2013-03-19 20:24:28 +01:00 |
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973513900d
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- Work on simulator
- Optimized wb_ddr_ctrl_wb_sc_fe and wb_ddr_ctrl_wb_dc[_fsm]
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2013-03-18 15:27:18 +01:00 |
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be7f1337f2
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- Work on simulator
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2013-03-14 13:06:42 +01:00 |
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2cdd255433
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- Corrected memory width to 64 bit
- Read/WritePipe (without latency modelling) implemented
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2013-03-13 18:35:06 +01:00 |
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1cb700f0c3
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- Simulator for shader core started
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2013-03-12 19:43:57 +01:00 |
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d6c83c5105
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- Makefile now generates xst file and has targets to open planahead (planahead_post{synth,impl})
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2013-03-11 21:23:04 +01:00 |
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077bef75d3
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- System integration & debugging
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2013-03-09 14:14:22 +01:00 |
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861cd1e00d
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- Integrated DDR controller with VGA and cache controller
- Debugged the above
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2013-03-08 21:43:43 +01:00 |
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90631f89bd
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- Reworked VGA
- Started changing DDR controller interface to 64 bit bus width
- Debugging
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2013-03-07 20:55:58 +01:00 |
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17835c4f7f
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- Debugging
- Added manual flush/invalidate to cache
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2013-03-05 22:49:30 +01:00 |
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321ea30ed8
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- Added synthesis contraints
- Added ZPU processor
- Optimized wb_ddr_ctrl_wb_dc* to meet timing
- Added cache frontend
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2013-03-04 12:55:59 +01:00 |
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34bec7d6c7
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- Begun implementing VGA out
- Integrated wishbone interconnect generator
- Debugging
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2013-03-02 21:27:54 +01:00 |
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f65882554d
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- Debugged write burst
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2013-03-02 12:29:47 +01:00 |
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cac9a8a60f
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- Corrected write timing
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2013-03-02 12:29:07 +01:00 |
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c04775d4a7
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- Made build rule for testbenches generic
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2013-03-02 12:26:58 +01:00 |
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95aa43b2d5
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- Debugging wb_ddr_ctrl
- Changed wb_ddr_ctrl_wb FIFO to 64 bit data width
- Added write burst support to wb_ddr_ctrl_wb_sc
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2013-02-28 21:10:44 +01:00 |
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56930a80c3
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- Seperated control and data path in wb_ddr_ctrl_wb_dc
- Debugging wb_ddr_ctrl
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2013-02-28 15:54:48 +01:00 |
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70aaa51615
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- Fixed DDR reset polarity
- Added planAhead script
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2013-02-27 12:13:26 +01:00 |
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dd2c99b93f
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- Import project
- Clean up
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2013-02-26 23:54:37 +01:00 |
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